US20140368960A1 - Over-voltage tolerant circuit and method - Google Patents
Over-voltage tolerant circuit and method Download PDFInfo
- Publication number
- US20140368960A1 US20140368960A1 US14/037,023 US201314037023A US2014368960A1 US 20140368960 A1 US20140368960 A1 US 20140368960A1 US 201314037023 A US201314037023 A US 201314037023A US 2014368960 A1 US2014368960 A1 US 2014368960A1
- Authority
- US
- United States
- Prior art keywords
- circuit
- pull
- transistor
- gate
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000008878 coupling Effects 0.000 description 13
- 238000010168 coupling process Methods 0.000 description 13
- 238000005859 coupling reaction Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 8
- 230000000630 rising effect Effects 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 208000032368 Device malfunction Diseases 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
Definitions
- This disclosure relates to the field of electronic circuits and more particularly to over-voltage tolerant circuits and methods.
- a hot-swap is an operation to add or remove a circuit or electronic device from an already powered system, normally without disturbing the rest of the system. This may cause some I/O to connect to powered signals in the system before the device is connected to a power supply.
- I 2 C inter-integrated circuit
- coupling of integrated circuits (ICs) that run at different supply voltages can cause input/output (I/O) pads of the IC or device to connect to a higher voltage than a supply voltage of the IC or device, potentially damaging the device or causing excessive loading or leakage currents in some I/O.
- Such excessive current leakage through the I/O pad can adversely impact signals on the I 2 C bus.
- a hot-swap or over-voltage tolerant circuit is desirable to enable the IC or device to be connected to a system, or to other ICs and devices, while the system is powered, without risk of damage to the IC or the system, without excessive leakage, and without interruption of communication.
- the hot-swap circuit 100 typically includes a pull-up p-channel metal-oxide-semiconductor field effect transistor (PMOS 102 ) formed in an n-well and coupled to the I/O pad 104 , an n-well selection circuit 106 , a sensing circuit 108 , and a latch 110 configured to retain a state of the sensing circuit, the latch coupled to the sensing circuit and the n-well selection circuit through a PMOS drive circuit 112 .
- vpb_drvr is connected to either a supply voltage (Vcc) or a voltage applied to the pad (Vpad), depending on Vpad.
- Vcc supply voltage
- Vpad voltage applied to the pad
- vpb_drvr is also indirectly connected to a gate of the pull-up PMOS 102 through a gate drive 114 .
- the gate drive 114 may be further connected to a control circuit to turn the pull-up PMOS on or off when it is not used.
- FIG. 1B illustrates the I/O pad voltage, n-well resistance and the latch state during example operation of the circuit of FIG. 1A .
- the I/O pad voltage may rise from a ground voltage (Vgnd) to Vcc ⁇ Vtp, where Vtp is a threshold voltage of the PMOS transistors P 1 and P 2 .
- Vgnd ground voltage
- Vtp is a threshold voltage of the PMOS transistors P 1 and P 2 .
- sense transistor P 3 is ON and sense transistor P 4 is OFF, and the latch 110 is in a normal state, which forces the gate of transistor P 1 to Vgnd, turning it ON.
- Transistor P 2 is OFF because Vpad is lower than Vcc, and hence the n-well node, vpb_drvr, of the pull-up PMOS is connected to Vcc. During a second time period the I/O pad voltage is rising from Vcc ⁇ Vtp to Vcc+Vtp. Both sense transistors P 3 and P 4 are OFF while the latch 110 retains the normal state and drives gate of transistor P 1 to Vgnd. Transistor P 2 is OFF and hence vpb_drvr is connected to Vcc.
- the I/O pad voltage is rising from Vcc+Vtp to an external voltage (Vext) coupled to the I/O pad 104 and then falling back to Vcc+Vtp.
- the sense transistor P 4 turns ON while sense transistor P 3 is OFF, which forces the latch 110 into a hot-swap state.
- the flipped latch 110 drives the gate of transistor P 1 high turning it OFF, transistor P 2 is automatically turned ON as the I/O pad 104 rises above transistor P 2 's gate voltage and hence vpb_drvr is connected to the I/O pad external voltage (Vext).
- the pad voltage is falling first from Vcc+Vtp to Vcc ⁇ Vtp.
- Latch 110 remains in the hot-swap state and drives gate of transistor P 1 high turning it OFF, while transistor P 2 is also automatically turned OFF, and hence vpb_drvr is neither connected to Vcc nor to the pad voltage (Vext).
- the n-well of the pull-up PMOS 102 floats when the I/O pad 104 is within a Vtp of Vcc as the pad voltage falls from a voltage above Vcc+Vtp.
- the risk of latch-up and associated device malfunction and interruption in communication is high.
- the resistance of the N-well connection varies with the pad voltage.
- the risk of latch-up is increased.
- the turn-on and turn-off of P 1 and P 2 has been described as changing abruptly at Vcc ⁇ Vtp and Vcc+Vtp, but in actual operation these changes will have a gradual transition and the effective on resistance of P 1 and P 2 will vary as the voltage varies.
- the hot-swap circuits and methods of the present disclosure reduces or eliminates completely the dead-zone, thereby substantially eliminating the risk of latch-up, any associated device malfunction including interruption in communication.
- the over-voltage tolerant circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch.
- the selection circuit includes a first bias circuit to apply Vcc to a well and, indirectly, to the gate of the pull-up transistor, a second bias circuit to apply Vpad to the well and, indirectly, to the gate of the pull-up transistor, and a non-overlap circuit configured to ensure the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.
- FIG. 1A is a block diagram illustrating conventional hot-swap circuit
- FIG. 1B illustrates a pad voltage, n-well resistance and latch state during operation of the circuit of FIG. 1A ;
- FIG. 2 is a block diagram illustrating an embodiment of a hot-swap circuit including a non-overlap circuit according to the present disclosure
- FIG. 3 is a schematic diagram illustrating an embodiment of a hot-swap circuit including a non-overlap circuit according to the present disclosure
- FIG. 4 is a schematic block diagram illustrating an embodiment of a non-overlap circuit according to the present disclosure
- FIGS. 5A and 5B are schematic block diagrams illustrating embodiments of a pull-down driver circuit according to the present disclosure to reduce the gate-pad coupling and hence reduce I/O pad leakage during power-up or power-down of the I/O pad;
- FIG. 6 is a flowchart illustrating an embodiment of a hot-swap method according to the present disclosure.
- Over-voltage tolerant circuits and methods are described herein.
- the circuit and method are particularly useful for preventing input/output (I/O) pad leakage and providing uninterrupted communication on a bus such as an inter-integrated circuit (I 2 C) bus, when an integrated circuit (IC) including the over-voltage tolerant circuit connected to the I 2 C bus is powered up or down.
- I 2 C inter-integrated circuit
- IC integrated circuit
- CMOS complementary metal-oxide-semiconductor
- CMOS circuit can become vulnerable to latch up when a well of a transistor in a pull-up driver coupled to the I/O pad is left in a high resistance state for more than a brief time, which can occur as a result of the overvoltage condition. Both of these phenomena can result in malfunction or destruction of the circuit.
- the over-voltage tolerant circuit 200 is fabricated using CMOS technology in a common substrate or semiconductor layer with an I/O pad 204 of an electronic device (not shown in this figure).
- the over-voltage tolerant circuit 200 generally includes a pull-up driver 202 coupled to the I/O pad 204 of the electronic device, a sensing circuit 206 coupled to the I/O pad and to a voltage supply (Vcc), a latch 208 coupled to the sensing circuit and a selection circuit 210 coupled to the sensing circuit through the latch.
- Vcc voltage supply
- the pull-up driver 202 includes at least one pull-up transistor 212 formed in a well in the substrate (not shown in this figure).
- the pull-up transistor 212 includes a P-type MOS (PMOS) transistor fabricated in an N-Well formed in P-type substrate or semiconductor layer.
- PMOS P-type MOS
- the sensing circuit 206 is configured to sense a voltage (Vpad) at the I/O pad 204 .
- the latch 208 is configured to retain an output of the sensing circuit, and to couple a p-gate hot-swap or more simply a gate hot-swap (pghs_h) signal indicating a high voltage on the I/O pad (Vpad) greater than Vcc, and/or a pad low voltage signal (padlo) indicating a voltage on the I/O pad (Vpad) less than Vcc to the selection circuit 210 .
- hot-swap signal or pghs_h it is meant a signal indicating an over-voltage condition has been sensed on the I/O pad 204 .
- this over-voltage condition can be the result of a hot-swap operation or a system to which the I/O pad of the electronic device is coupled being turned on or off.
- the selection circuit 210 is configured to apply a bias to the well and, indirectly, to the gate of the pull-up transistor 212 to prevent an undesirably large leakage current from the I/O pad 204 and also to provide a low resistance connection to the well that otherwise may result in latch up vulnerability of the electronic device in which the over-voltage tolerant circuit 200 is included, or in an already powered system (not shown) or separate device to which the electronic device is being added or removed.
- the gate of the pull-up transistor 212 is indirectly coupled to the selection circuit 210 through a gate drive 214 .
- the gate drive 214 operated by control signal from a control circuit (not shown) to enable the pull-up transistor 212 to be turned on or off in certain applications, such as non-I 2 C applications or when the electronic device is not coupled or connected to an I 2 C bus.
- the over-voltage tolerant circuit 200 further includes a pull-down driver 216 coupled between the I/O pad 204 of the electronic device and a circuit ground (Vgnd) to reduce I/O pad leakage during power-up or power-down of the device.
- the pull-down driver 216 includes at least one pull-down transistor (not shown in this figure).
- One problem with conventional pull-down drivers is that when an external I 2 C pull-up supply (Vext) is applied to the I/O pad 204 and the device is unpowered, a gate of the pull-down transistor may not be strongly driven, so that the gate of the pull-down transistor can capacitively couple to the I/O pad.
- the gate voltage the of the pull-down transistor can rise due to the capacitive coupling and weakly turn ON the pull-down transistor. This in turn causes I/O pad 204 loading, and hence undesired I 2 C bus distortion.
- the pull-down driver 216 of the present disclosure is driven during power-up or power-down of the device by an existing pghs_h signal in the over-voltage tolerant circuit 200 to drive the gate of pull-down transistor to Vgnd, thus overriding the capacitive coupling between I/O pad 204 and gate of the pull-down transistor, thereby eliminating I/O pad loading, and undesired I 2 C bus distortion. Details of the pull-down driver 216 will be described below in greater detail with reference to FIGS. 5A and 5B .
- the selection circuit 210 includes a first bias circuit 218 configured to apply Vcc to the well and, indirectly, to the gate of the pull-up transistor 212 , a second bias circuit 220 configured to apply Vpad to the well and, indirectly, to the gate of the pull-up transistor, and a non-overlap circuit 222 configured to ensure the well and gate of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit 206 .
- the over-voltage tolerant circuit 300 includes a sensing circuit 302 coupled to an I/O pad 304 and to a voltage supply (Vcc), a latch 306 coupled to the sensing circuit, a selection circuit 308 coupled to the sensing circuit through the latch, and a non-overlap circuit 310 coupled to the latch and the selection circuit.
- Vcc voltage supply
- the over-voltage tolerant circuit 300 further includes a gate drive 312 or interface circuitry to interface between a pull-up driver 314 and the rest of the over-voltage tolerant circuit 300 , and logic block or logic 316 to drive or control the pull-up driver 314 in applications that do not experience hot-swap or over-voltage conditions.
- the logic 316 provides an output that is low to turn on the pull-up driver 314 , and high to turn it off. In over-voltage applications such as I 2 C, the pull-up driver 314 is turned off and the logic 316 output drives high at Vcc.
- Transistors P 5 and N 5 in the gate drive 312 function as a switch to enable logic 316 to output or pass Vcc to a gate of a pull-up transistor P 7 in the pull-up driver 314 in normal operation but to block it in over-voltage conditions, so that the pull-up driver's input can rise above Vcc.
- Device P 6 couples between vpb_drvr and the gate of the pull-up transistor P 7 in the pull-up driver 314 to provide a pull-up gate hot-swap (pug_h) signal. P 6 is turned on when the P 2 device turns on. This allows pug_h to rise to vpb_drvr which will be at Vpad, which can be a higher voltage than the supply voltage Vcc.
- the over-voltage tolerant circuit 300 further includes a pull-down driver 318 coupled between the I/O pad 304 of the electronic device and a circuit ground (Vgnd) to reduce I/O pad leakage during power-up or power-down of the device.
- the pull-down driver 318 includes at least one pull-down transistor (not shown in this figure). Details of the pull-down driver 318 will be described below in greater detail with reference to FIGS. 5A and 5B .
- the sensing circuit 302 includes cross-coupled first and second sense transistors, P 3 and P 4 respectively.
- sense transistors P 3 and P 4 are PMOS transistors.
- the selection circuit 308 includes first and second select transistors, P 1 and P 2 respectively.
- sense transistor P 1 is a PMOS transistor with a gate connected to the Non-Overlap Circuit 310 and to the gate drive 312
- sense transistor P 2 is also a PMOS transistor with a gate connected to Vcc and to the Non-Overlap Circuit 310 .
- the sensing circuit 302 monitors the I/O pad 304 constantly and updates the state of latch 306 , which in turn signals the non-overlap circuit 310 through a pad low voltage (padlo) signal.
- the latch 306 may be connected to the sense transistors 302 through switches, S 1 and S 2 , that toggle such that the latch only receives input from the sense transistor that can change the latch state.
- the Non-Overlap Circuit 310 generates one of two mutually exclusive signals, P 1 g and P 2 g , which ensures that either select transistor P 1 or P 2 is substantially always turned ON and hence the at-risk N-well of a PMOS pull-up transistor in a pull-up driver (not shown in this figure) is substantially always driven by relatively low impedance.
- the latch 306 when the I/O pad 304 is rising from Vgnd to Vcc ⁇ Vtp sense transistor P 3 is ON and while Vcc is applied to a gate of sense transistor P 4 forcing it OFF, the latch 306 is in a normal state, and the non-overlap circuit 310 outputs a P 1 g signal to a gate of the select transistor P 1 turning it ON while select transistor P 2 remains off, and hence coupling output node vpb_drvr to Vcc, connecting a gate and the N-well of the PMOS pull-up transistor to Vcc.
- sense transistor P 4 turns ON while P 3 is OFF, forcing the latch 306 into a hot-swap state, signaling the non-overlap circuit 310 to assert the P 2 g signal to a gate of the select transistor P 2 turning it ON while select transistor P 1 turns off, and hence coupling output node vpb_drvr to a voltage on the I/O pad 304 (Vpad), and connecting the N-well and, indirectly, the gate of the PMOS pull-up transistor to Vpad.
- the latch 110 retains the hot-swap state and drives the gate of select transistor P 1 to high thus also turning it OFF, with the undesirable result that node vpb_drvr is neither connected to Vcc nor to Vpad with a low resistance, causing the N-well and, indirectly, the gate of the PMOS pull-up transistor to float, resulting in the risk of latch-up of the electronic device, the consequent malfunction and possible interruption in communication on an I 2 C bus to which the I/O pad 104 is connected.
- the non-overlap circuit 310 continues to output the P 2 g signal to the gate of the select transistor P 2 maintaining it ON until Vpad goes below Vcc ⁇ Vtp to change the latch state, discontinuing or removing the P 2 g signal to the gate of the select transistor P 2 turning it OFF and asserting the P 1 g signal to the gate of the select transistor P 1 turning it ON.
- the N-well and, indirectly, the gate of the PMOS pull-up transistor P 7 are substantially always driven by a relatively low impedance, reducing if not eliminating entirely the float or the dead zone described above, thereby removing in the risk of latch-up of the electronic device, avoiding associated malfunction and interruption in communication on an I 2 C bus to which the I/O pad 304 is connected.
- the non-overlap circuit 400 includes a dual input nand gate 402 and a dual input nor gate 404 , each having a first cross-coupled input coupled to the output of the other through first or second inverters 406 , 408 , and a second input coupled to the latch (not shown in this figure) to receive a padlo signal therefrom and to generate P 1 g and P 2 g signals as appropriate.
- the padlo signal on the second input of nand gate 402 is low and outputs a high P 1 g signal, turning off select transistor P 1 .
- nor gate 404 receives on the first input an inverted P 1 g signal, a logic 0, so nor gate 404 output is high, inverter 408 output is low, and signal P 2 g is low, turning on select transistor P 2 , coupling the vpb_drvr to Vpad.
- the padlo signal on the second input of nor gate 404 goes high and nor gate 404 outputs a low and signal P 2 g , the output of inverter 408 , goes high turning off the select transistor P 2 .
- nand gate 402 receiving high signal on both inputs, i.e., a high padlo signal and a high P 2 g signal, outputs a logic 0, which generates a low P 1 g signal, turning on select transistor P 1 and coupling the vpb_drvr to Vcc.
- a pull-down driver circuit is provided to reduce a gate-pad coupling of transistors in the pull-down driver circuit and hence reduce I/O pad leakage during power-up or power-down of the I/O pad.
- Embodiments of a pull-down driver circuit according to the present disclosure will now be described in greater detail with reference to the schematic diagram of FIGS. 5A and 5B .
- the pull-down driver circuit 500 includes at least one leg 502 including a N-type MOS (NMOS) pull-down transistor 504 coupled between the I/O pad 506 and a circuit ground.
- NMOS N-type MOS
- a logic pre-driver or block such as logic 316 in FIG. 3
- each leg 502 of the pull-down circuit 500 further includes a second NMOS transistor 508 coupled between the gate of the pull-down transistor 504 and circuit ground and configured to receive a pghs_h signal from an over-voltage tolerant circuit, such as described above with respect to FIG. 2 or 3 , to drive the gate of the NMOS pull-down transistor low enough that any coupling from the I/O PAD does not turn on devices 504 sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally.
- a second NMOS transistor 508 coupled between the gate of the pull-down transistor 504 and circuit ground and configured to receive a pghs_h signal from an over-voltage tolerant circuit, such as described above with respect to FIG. 2 or 3 , to drive the gate of the NMOS pull-down transistor low enough that any coupling from the I/O PAD does not turn on devices 504 sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally
- the pull-down driver circuit 500 includes multiple legs 502 a - 502 c coupled in parallel between the I/O pad 506 and circuit ground.
- the pull-down transistors 504 in each of these legs can be independently turned on during normal operation of the pull-down circuit 504 by application of an appropriate pull-down signal, shown here as pd_n ⁇ 0> to pd_n ⁇ 2>, from the logic pre-driver. Additionally, as in the embodiment of FIG.
- a second NMOS transistor 508 is coupled between the gate of the pull-down transistor 504 and circuit ground to drive the gate of the NMOS pull-down transistor low enough that any coupling from the I/O PAD does not turn on the pull-down transistors 504 sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally.
- the pull-down circuit 500 includes multiple staggered legs 502 a - 502 c having increasing or unequal sizes or pull-down capabilities or impedance.
- the first of the multiple legs, leg 502 a further includes a resistance element 510 in series with the pull-down transistor 504 to implement slew-rate control.
- This is shown as optionally implemented for a single leg and hence does not affect any other parameter during normal (non-over-voltage) operation, such as slew-rate control. It has been found that a pull-down circuit including multiple staggered legs according to the present disclosure can decrease an I 2 C pad distortion due to pad loading by up to about 20%.
- the transistors 508 are used to drive the gates of associated pull-down transistors 504 low enough that any coupling from the I/O PAD does not turn on the pull-down transistors sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally.
- a method using an over-voltage tolerant circuit including a non-overlap circuit and a pull-down driver will now be described with reference to the flowchart of FIG. 6 .
- the method begins with applying a first gate signal (P 1 g ) from a non-overlap circuit to a gate of a first select transistor (P 1 ) to couple a supply voltage (Vcc) to an N-well and, indirectly, a gate of a PMOS pull-up transistor coupled to an I/O pad of an electronic device (step 602 ).
- a sensing circuit then senses a voltage applied to the I/O pad (Vpad) is greater than Vcc+a threshold voltage of the PMOS pull-up transistor (Vtp) (step 604 ).
- the first gate signal (P 1 g ) is removed from the gate of the first select transistor (P 1 ) and applying a second gate signal (P 2 g ) to a second select transistor (P 2 ) to couple Vpad to the gate and N-well of the PMOS pull-up transistor (step 606 ).
- the second gate signal (P 2 g ) is removed from the gate of the second select transistor (P 2 ) and applies P 1 g to couple Vcc to the gate and N-well of the PMOS pull-up transistor (step 610 ).
- the time between removing the second gate signal (P 2 g ) from the gate of the second select transistor (P 2 ) and applying to couple Vcc to the N-well and, indirectly, the gate of the PMOS pull-up transistor, while not instantaneous is less than about 10 ns.
- the over-voltage tolerant circuit further includes a pull-down driver according to the present disclosure coupled between the I/O pad and a circuit ground
- the method further includes sending a pghs_h signal from the sensing circuit to the pull-down driver, and providing a current path to the circuit ground through the pull-down driver to reduce I/O pad leakage during power-up or power-down of the device (step 612 ).
- Vcc+Vtp and Vcc ⁇ Vtp alternative approaches may be used to accomplish the same purpose with different sensing mechanisms and sense points.
- one or more comparators may be used to sense voltages that are closer to Vcc, such as Vcc+100 mV and Vcc ⁇ 100 mV to reduce the voltage difference between the two sense points.
- the sense points may both occur above Vcc, such as at Vcc+200 mV and Vcc+100 mV.
- a single sense point may be used, such as at Vcc+100 mV.
Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 61/834,061, filed on Jun. 12, 2013, which is incorporated by reference herein.
- This disclosure relates to the field of electronic circuits and more particularly to over-voltage tolerant circuits and methods.
- There are several circumstances in which a circuit or electronic device may experience may experience voltages higher than the connected supply voltage. For example, a hot-swap is an operation to add or remove a circuit or electronic device from an already powered system, normally without disturbing the rest of the system. This may cause some I/O to connect to powered signals in the system before the device is connected to a power supply. In some applications, such as inter-integrated circuit (I2C) communication, coupling of integrated circuits (ICs) that run at different supply voltages can cause input/output (I/O) pads of the IC or device to connect to a higher voltage than a supply voltage of the IC or device, potentially damaging the device or causing excessive loading or leakage currents in some I/O. Such excessive current leakage through the I/O pad can adversely impact signals on the I2C bus. In addition, when a device is connected to a system and power to the system is turned on or turned off, there may be voltages on I/O pins of the device that are higher than the supply during either a turning-on transition, a turning-off transition, or when the power is stably off. Thus, a hot-swap or over-voltage tolerant circuit is desirable to enable the IC or device to be connected to a system, or to other ICs and devices, while the system is powered, without risk of damage to the IC or the system, without excessive leakage, and without interruption of communication.
- One such circuit is illustrated in
FIG. 1A . Referring toFIG. 1A , the hot-swap circuit 100 typically includes a pull-up p-channel metal-oxide-semiconductor field effect transistor (PMOS 102) formed in an n-well and coupled to the I/O pad 104, an n-well selection circuit 106, asensing circuit 108, and alatch 110 configured to retain a state of the sensing circuit, the latch coupled to the sensing circuit and the n-well selection circuit through aPMOS drive circuit 112. The n-well node, labeled vpb_drvr inFIG. 1A , of the pull-up PMOS 102 is driven by PMOS transistors P1 and P2 in the n-well selection circuit 106 such that vpb_drvr is connected to either a supply voltage (Vcc) or a voltage applied to the pad (Vpad), depending on Vpad. Typically, vpb_drvr is also indirectly connected to a gate of the pull-up PMOS 102 through agate drive 114. In certain non-I2C applications thegate drive 114 may be further connected to a control circuit to turn the pull-up PMOS on or off when it is not used. -
FIG. 1B , illustrates the I/O pad voltage, n-well resistance and the latch state during example operation of the circuit ofFIG. 1A . Referring toFIG. 1B , the I/O pad voltage may rise from a ground voltage (Vgnd) to Vcc−Vtp, where Vtp is a threshold voltage of the PMOS transistors P1 and P2. During this time sense transistor P3 is ON and sense transistor P4 is OFF, and thelatch 110 is in a normal state, which forces the gate of transistor P1 to Vgnd, turning it ON. Transistor P2 is OFF because Vpad is lower than Vcc, and hence the n-well node, vpb_drvr, of the pull-up PMOS is connected to Vcc. During a second time period the I/O pad voltage is rising from Vcc−Vtp to Vcc+Vtp. Both sense transistors P3 and P4 are OFF while thelatch 110 retains the normal state and drives gate of transistor P1 to Vgnd. Transistor P2 is OFF and hence vpb_drvr is connected to Vcc. During a third time period the I/O pad voltage is rising from Vcc+Vtp to an external voltage (Vext) coupled to the I/O pad 104 and then falling back to Vcc+Vtp. The sense transistor P4 turns ON while sense transistor P3 is OFF, which forces thelatch 110 into a hot-swap state. The flippedlatch 110 drives the gate of transistor P1 high turning it OFF, transistor P2 is automatically turned ON as the I/O pad 104 rises above transistor P2's gate voltage and hence vpb_drvr is connected to the I/O pad external voltage (Vext). Finally, in a fourth time period the pad voltage is falling first from Vcc+Vtp to Vcc−Vtp. Both sense transistors P3 and P4 are OFF. Latch 110 remains in the hot-swap state and drives gate of transistor P1 high turning it OFF, while transistor P2 is also automatically turned OFF, and hence vpb_drvr is neither connected to Vcc nor to the pad voltage (Vext). Thus, the n-well of the pull-upPMOS 102 floats when the I/O pad 104 is within a Vtp of Vcc as the pad voltage falls from a voltage above Vcc+Vtp. During this period in which the n-well of the pull-up PMOS 102 is floating, commonly called a dead-zone, the risk of latch-up and associated device malfunction and interruption in communication is high. As shown in the N-well drive resistance plot at the bottom ofFIG. 1B , the resistance of the N-well connection varies with the pad voltage. When the resistance is high, the risk of latch-up is increased. Although the turn-on and turn-off of P1 and P2 has been described as changing abruptly at Vcc−Vtp and Vcc+Vtp, but in actual operation these changes will have a gradual transition and the effective on resistance of P1 and P2 will vary as the voltage varies. - The hot-swap circuits and methods of the present disclosure reduces or eliminates completely the dead-zone, thereby substantially eliminating the risk of latch-up, any associated device malfunction including interruption in communication.
- In one embodiment, the over-voltage tolerant circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and, indirectly, to the gate of the pull-up transistor, a second bias circuit to apply Vpad to the well and, indirectly, to the gate of the pull-up transistor, and a non-overlap circuit configured to ensure the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.
- The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
-
FIG. 1A is a block diagram illustrating conventional hot-swap circuit; -
FIG. 1B illustrates a pad voltage, n-well resistance and latch state during operation of the circuit ofFIG. 1A ; -
FIG. 2 is a block diagram illustrating an embodiment of a hot-swap circuit including a non-overlap circuit according to the present disclosure; -
FIG. 3 is a schematic diagram illustrating an embodiment of a hot-swap circuit including a non-overlap circuit according to the present disclosure; -
FIG. 4 is a schematic block diagram illustrating an embodiment of a non-overlap circuit according to the present disclosure; -
FIGS. 5A and 5B are schematic block diagrams illustrating embodiments of a pull-down driver circuit according to the present disclosure to reduce the gate-pad coupling and hence reduce I/O pad leakage during power-up or power-down of the I/O pad; and -
FIG. 6 is a flowchart illustrating an embodiment of a hot-swap method according to the present disclosure. - Over-voltage tolerant circuits and methods are described herein. The circuit and method are particularly useful for preventing input/output (I/O) pad leakage and providing uninterrupted communication on a bus such as an inter-integrated circuit (I2C) bus, when an integrated circuit (IC) including the over-voltage tolerant circuit connected to the I2C bus is powered up or down. In particular, a large leakage current from an I/O pad of a complementary metal-oxide-semiconductor (CMOS) circuit may arise as a result of an overvoltage condition where I/O pad voltage is higher than the supply voltage. Additionally, the CMOS circuit can become vulnerable to latch up when a well of a transistor in a pull-up driver coupled to the I/O pad is left in a high resistance state for more than a brief time, which can occur as a result of the overvoltage condition. Both of these phenomena can result in malfunction or destruction of the circuit.
- In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.
- Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term to couple as used herein may include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components.
- One embodiment of a hot-swap or over-voltage
tolerant circuit 200 according to the present disclosure is illustrated in the block diagram ofFIG. 2 . Generally, the over-voltagetolerant circuit 200 is fabricated using CMOS technology in a common substrate or semiconductor layer with an I/O pad 204 of an electronic device (not shown in this figure). Referring toFIG. 2 , the over-voltagetolerant circuit 200 generally includes a pull-updriver 202 coupled to the I/O pad 204 of the electronic device, asensing circuit 206 coupled to the I/O pad and to a voltage supply (Vcc), alatch 208 coupled to the sensing circuit and aselection circuit 210 coupled to the sensing circuit through the latch. The pull-updriver 202 includes at least one pull-uptransistor 212 formed in a well in the substrate (not shown in this figure). In certain embodiments, such as that shown, the pull-uptransistor 212 includes a P-type MOS (PMOS) transistor fabricated in an N-Well formed in P-type substrate or semiconductor layer. - The
sensing circuit 206 is configured to sense a voltage (Vpad) at the I/O pad 204. Thelatch 208 is configured to retain an output of the sensing circuit, and to couple a p-gate hot-swap or more simply a gate hot-swap (pghs_h) signal indicating a high voltage on the I/O pad (Vpad) greater than Vcc, and/or a pad low voltage signal (padlo) indicating a voltage on the I/O pad (Vpad) less than Vcc to theselection circuit 210. By hot-swap signal or pghs_h it is meant a signal indicating an over-voltage condition has been sensed on the I/O pad 204. It will be understood that as noted above this over-voltage condition can be the result of a hot-swap operation or a system to which the I/O pad of the electronic device is coupled being turned on or off. Theselection circuit 210 is configured to apply a bias to the well and, indirectly, to the gate of the pull-uptransistor 212 to prevent an undesirably large leakage current from the I/O pad 204 and also to provide a low resistance connection to the well that otherwise may result in latch up vulnerability of the electronic device in which the over-voltagetolerant circuit 200 is included, or in an already powered system (not shown) or separate device to which the electronic device is being added or removed. - Generally, as in the embodiment shown and as noted above the gate of the pull-up
transistor 212 is indirectly coupled to theselection circuit 210 through agate drive 214. Thegate drive 214 operated by control signal from a control circuit (not shown) to enable the pull-uptransistor 212 to be turned on or off in certain applications, such as non-I2C applications or when the electronic device is not coupled or connected to an I2C bus. - Optionally, the over-voltage
tolerant circuit 200 further includes a pull-downdriver 216 coupled between the I/O pad 204 of the electronic device and a circuit ground (Vgnd) to reduce I/O pad leakage during power-up or power-down of the device. Typically, the pull-downdriver 216 includes at least one pull-down transistor (not shown in this figure). One problem with conventional pull-down drivers is that when an external I2C pull-up supply (Vext) is applied to the I/O pad 204 and the device is unpowered, a gate of the pull-down transistor may not be strongly driven, so that the gate of the pull-down transistor can capacitively couple to the I/O pad. As a result, the gate voltage the of the pull-down transistor, normally held low during power-up or power-down of the pull-down transistor by a CMOS logic pre-driver to place the I/O pad 204 in a high impedance mode, can rise due to the capacitive coupling and weakly turn ON the pull-down transistor. This in turn causes I/O pad 204 loading, and hence undesired I2C bus distortion. - In contrast to conventional pull-down drivers, the pull-down
driver 216 of the present disclosure is driven during power-up or power-down of the device by an existing pghs_h signal in the over-voltagetolerant circuit 200 to drive the gate of pull-down transistor to Vgnd, thus overriding the capacitive coupling between I/O pad 204 and gate of the pull-down transistor, thereby eliminating I/O pad loading, and undesired I2C bus distortion. Details of the pull-downdriver 216 will be described below in greater detail with reference toFIGS. 5A and 5B . - Referring again to
FIG. 2 , theselection circuit 210 includes afirst bias circuit 218 configured to apply Vcc to the well and, indirectly, to the gate of the pull-uptransistor 212, asecond bias circuit 220 configured to apply Vpad to the well and, indirectly, to the gate of the pull-up transistor, and anon-overlap circuit 222 configured to ensure the well and gate of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of thesensing circuit 206. By substantially always it is meant a time during which the well and gate of the pull-up transistor is not driven by either the first or the second bias circuit is less than about 10 microseconds (μs), and more preferably less than about 10 nanoseconds (ns). Because the well and gate of the pull-uptransistor 212 is substantially always driven, a dead-zone when the I/O pad 204 is within a threshold voltage of the PMOS transistors (Vtp) of Vcc is reduced or eliminated completely, thereby substantially eliminating the risk of latch-up in the electronic device including the over-voltagetolerant circuit 200, and the consequent malfunction and interruption in communication. - An embodiment of an over-voltage tolerant circuit including a non-overlap circuit according to the present disclosure will now be described in greater detail with reference to the schematic diagram of
FIG. 3 . Referring toFIG. 3 , the over-voltagetolerant circuit 300 includes asensing circuit 302 coupled to an I/O pad 304 and to a voltage supply (Vcc), alatch 306 coupled to the sensing circuit, aselection circuit 308 coupled to the sensing circuit through the latch, and anon-overlap circuit 310 coupled to the latch and the selection circuit. - Generally, as in the embodiment shown, the over-voltage
tolerant circuit 300 further includes agate drive 312 or interface circuitry to interface between a pull-updriver 314 and the rest of the over-voltagetolerant circuit 300, and logic block orlogic 316 to drive or control the pull-updriver 314 in applications that do not experience hot-swap or over-voltage conditions. Thelogic 316 provides an output that is low to turn on the pull-updriver 314, and high to turn it off. In over-voltage applications such as I2C, the pull-updriver 314 is turned off and thelogic 316 output drives high at Vcc. Transistors P5 and N5 in thegate drive 312 function as a switch to enablelogic 316 to output or pass Vcc to a gate of a pull-up transistor P7 in the pull-updriver 314 in normal operation but to block it in over-voltage conditions, so that the pull-up driver's input can rise above Vcc. Device P6 couples between vpb_drvr and the gate of the pull-up transistor P7 in the pull-updriver 314 to provide a pull-up gate hot-swap (pug_h) signal. P6 is turned on when the P2 device turns on. This allows pug_h to rise to vpb_drvr which will be at Vpad, which can be a higher voltage than the supply voltage Vcc. - The over-voltage
tolerant circuit 300 further includes a pull-downdriver 318 coupled between the I/O pad 304 of the electronic device and a circuit ground (Vgnd) to reduce I/O pad leakage during power-up or power-down of the device. Typically, the pull-downdriver 318 includes at least one pull-down transistor (not shown in this figure). Details of the pull-downdriver 318 will be described below in greater detail with reference toFIGS. 5A and 5B . - The
sensing circuit 302 includes cross-coupled first and second sense transistors, P3 and P4 respectively. In some embodiments, such as that shown, sense transistors P3 and P4 are PMOS transistors. Theselection circuit 308 includes first and second select transistors, P1 and P2 respectively. In some embodiments, such as that shown, sense transistor P1 is a PMOS transistor with a gate connected to theNon-Overlap Circuit 310 and to thegate drive 312, and sense transistor P2 is also a PMOS transistor with a gate connected to Vcc and to theNon-Overlap Circuit 310. Thesensing circuit 302 monitors the I/O pad 304 constantly and updates the state oflatch 306, which in turn signals thenon-overlap circuit 310 through a pad low voltage (padlo) signal. As in the embodiment shown, thelatch 306 may be connected to thesense transistors 302 through switches, S1 and S2, that toggle such that the latch only receives input from the sense transistor that can change the latch state. TheNon-Overlap Circuit 310 generates one of two mutually exclusive signals, P1 g and P2 g, which ensures that either select transistor P1 or P2 is substantially always turned ON and hence the at-risk N-well of a PMOS pull-up transistor in a pull-up driver (not shown in this figure) is substantially always driven by relatively low impedance. - In particular, when the I/
O pad 304 is rising from Vgnd to Vcc−Vtp sense transistor P3 is ON and while Vcc is applied to a gate of sense transistor P4 forcing it OFF, thelatch 306 is in a normal state, and thenon-overlap circuit 310 outputs a P1 g signal to a gate of the select transistor P1 turning it ON while select transistor P2 remains off, and hence coupling output node vpb_drvr to Vcc, connecting a gate and the N-well of the PMOS pull-up transistor to Vcc. - When the I/
O pad 304 is rising from Vcc−Vtp to Vcc+Vtp both sense transistors P3 and P4 are OFF. However, thelatch 306 retains the normal state, and thenon-overlap circuit 310 continues to output the P1 g signal to the gate of the select transistor P1 maintaining it ON while select transistor P2 remains off, and hence coupling output node vpb_drvr to Vcc. - When the I/
O pad 304 is rising from Vcc+Vtp to a higher external I/O pad voltage (Vext) and then falling back to Vcc+Vtp, sense transistor P4 turns ON while P3 is OFF, forcing thelatch 306 into a hot-swap state, signaling thenon-overlap circuit 310 to assert the P2 g signal to a gate of the select transistor P2 turning it ON while select transistor P1 turns off, and hence coupling output node vpb_drvr to a voltage on the I/O pad 304 (Vpad), and connecting the N-well and, indirectly, the gate of the PMOS pull-up transistor to Vpad. - In a conventional hot-
swap circuit 100, such as described above with reference toFIG. 1 , as the voltage on the I/O pad 104 continues falling from Vcc+Vtp to Vcc−Vtp both sense transistors P3 and P4 are OFF, and select transistor P2 automatically turned OFF as Vpad drops below the P2 gate signal. Thelatch 110 retains the hot-swap state and drives the gate of select transistor P1 to high thus also turning it OFF, with the undesirable result that node vpb_drvr is neither connected to Vcc nor to Vpad with a low resistance, causing the N-well and, indirectly, the gate of the PMOS pull-up transistor to float, resulting in the risk of latch-up of the electronic device, the consequent malfunction and possible interruption in communication on an I2C bus to which the I/O pad 104 is connected. - In contrast, in the over-voltage
tolerant circuit 300 ofFIG. 3 , thenon-overlap circuit 310 continues to output the P2 g signal to the gate of the select transistor P2 maintaining it ON until Vpad goes below Vcc−Vtp to change the latch state, discontinuing or removing the P2 g signal to the gate of the select transistor P2 turning it OFF and asserting the P1 g signal to the gate of the select transistor P1 turning it ON. Thus, the N-well and, indirectly, the gate of the PMOS pull-up transistor P7 are substantially always driven by a relatively low impedance, reducing if not eliminating entirely the float or the dead zone described above, thereby removing in the risk of latch-up of the electronic device, avoiding associated malfunction and interruption in communication on an I2C bus to which the I/O pad 304 is connected. - An embodiment of a non-overlap circuit according to the present disclosure will now be described in greater detail with reference to the schematic diagram of
FIG. 4 . Referring toFIG. 4 , in one embodiment thenon-overlap circuit 400 includes a dualinput nand gate 402 and a dual input norgate 404, each having a first cross-coupled input coupled to the output of the other through first orsecond inverters nand gate 402 is low and outputs a high P1 g signal, turning off select transistor P1. At substantially the same time norgate 404 receives on the first input an inverted P1 g signal, alogic 0, so norgate 404 output is high,inverter 408 output is low, and signal P2 g is low, turning on select transistor P2, coupling the vpb_drvr to Vpad. When the latch is no longer in the hot-swap state, the padlo signal on the second input of norgate 404 goes high and norgate 404 outputs a low and signal P2 g, the output ofinverter 408, goes high turning off the select transistor P2. Immediately or shortly thereafternand gate 402 receiving high signal on both inputs, i.e., a high padlo signal and a high P2 g signal, outputs alogic 0, which generates a low P1 g signal, turning on select transistor P1 and coupling the vpb_drvr to Vcc. - Because generation of the two signals P1 g and P2 g are mutually exclusive, it is ensured that one and only one of select transistor P1 or P2 is turned ON and hence the at-risk N-well of a PMOS pull-up transistor in a pull-up driver (not shown in this figure) is always driven by a relatively low impedance. Because of time delays arising from propagation of the signals through the
nand gate 402, the norgate 404, andinverters - In another aspect, a pull-down driver circuit is provided to reduce a gate-pad coupling of transistors in the pull-down driver circuit and hence reduce I/O pad leakage during power-up or power-down of the I/O pad. Embodiments of a pull-down driver circuit according to the present disclosure will now be described in greater detail with reference to the schematic diagram of
FIGS. 5A and 5B . - Referring to
FIG. 5A , in one embodiment the pull-downdriver circuit 500 includes at least oneleg 502 including a N-type MOS (NMOS) pull-down transistor 504 coupled between the I/O pad 506 and a circuit ground. A pull-down signal (PD) applied to a gate of the NMOS pull-down transistor 504 from a logic pre-driver or block, such aslogic 316 inFIG. 3 , places the I/O pad in a high impedance mode. As noted above one problem with conventional pull-down drivers is that when an external I2C pull-up supply (Vext) is applied to the I/O pad 506 and the device is unpowered, the gate of the pull-down transistor 504 may not be strongly driven, and can capacitively couple to the I/O 506 pad through a parasitic capacitor C. As a result, a gate voltage of the pull-down transistor 504, normally held low during power-up or power-down, can rise weakly turning ON the pull-down transistor, and causing I/O pad 506 loading and I2C bus distortion. However, in the embodiment shown inFIG. 5A eachleg 502 of the pull-down circuit 500 further includes asecond NMOS transistor 508 coupled between the gate of the pull-down transistor 504 and circuit ground and configured to receive a pghs_h signal from an over-voltage tolerant circuit, such as described above with respect toFIG. 2 or 3, to drive the gate of the NMOS pull-down transistor low enough that any coupling from the I/O PAD does not turn ondevices 504 sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally. - In another embodiment, shown in
FIG. 5B , the pull-downdriver circuit 500 includesmultiple legs 502 a-502 c coupled in parallel between the I/O pad 506 and circuit ground. The pull-downtransistors 504 in each of these legs can be independently turned on during normal operation of the pull-down circuit 504 by application of an appropriate pull-down signal, shown here as pd_n<0> to pd_n<2>, from the logic pre-driver. Additionally, as in the embodiment ofFIG. 5A described above, in eachleg 502 a-502 c asecond NMOS transistor 508 is coupled between the gate of the pull-down transistor 504 and circuit ground to drive the gate of the NMOS pull-down transistor low enough that any coupling from the I/O PAD does not turn on the pull-downtransistors 504 sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally. - Optionally, in some embodiments the pull-
down circuit 500 includes multiplestaggered legs 502 a-502 c having increasing or unequal sizes or pull-down capabilities or impedance. For example in the embodiment shown inFIG. 5B the first of the multiple legs,leg 502 a, further includes aresistance element 510 in series with the pull-down transistor 504 to implement slew-rate control. This is shown as optionally implemented for a single leg and hence does not affect any other parameter during normal (non-over-voltage) operation, such as slew-rate control. It has been found that a pull-down circuit including multiple staggered legs according to the present disclosure can decrease an I2C pad distortion due to pad loading by up to about 20%. Since the pghs_h signal is asserted during over-voltage conditions on the pad, thetransistors 508 are used to drive the gates of associated pull-downtransistors 504 low enough that any coupling from the I/O PAD does not turn on the pull-down transistors sufficiently to cause excessive I/O leakage that could otherwise occur when the PAD voltage is being driven high externally. - A method using an over-voltage tolerant circuit including a non-overlap circuit and a pull-down driver according to embodiments of the present disclosure will now be described with reference to the flowchart of
FIG. 6 . Referring toFIG. 6 the method begins with applying a first gate signal (P1 g) from a non-overlap circuit to a gate of a first select transistor (P1) to couple a supply voltage (Vcc) to an N-well and, indirectly, a gate of a PMOS pull-up transistor coupled to an I/O pad of an electronic device (step 602). A sensing circuit then senses a voltage applied to the I/O pad (Vpad) is greater than Vcc+a threshold voltage of the PMOS pull-up transistor (Vtp) (step 604). Next, the first gate signal (P1 g) is removed from the gate of the first select transistor (P1) and applying a second gate signal (P2 g) to a second select transistor (P2) to couple Vpad to the gate and N-well of the PMOS pull-up transistor (step 606). When the sensing circuit senses Vpad is less than Vcc−Vtp (step 608), the second gate signal (P2 g) is removed from the gate of the second select transistor (P2) and applies P1 g to couple Vcc to the gate and N-well of the PMOS pull-up transistor (step 610). As noted above, the time between removing the second gate signal (P2 g) from the gate of the second select transistor (P2) and applying to couple Vcc to the N-well and, indirectly, the gate of the PMOS pull-up transistor, while not instantaneous is less than about 10 ns. - Optionally, where the over-voltage tolerant circuit further includes a pull-down driver according to the present disclosure coupled between the I/O pad and a circuit ground, the method further includes sending a pghs_h signal from the sensing circuit to the pull-down driver, and providing a current path to the circuit ground through the pull-down driver to reduce I/O pad leakage during power-up or power-down of the device (step 612).
- While the discussion has described a sense circuit operating with thresholds of PMOS devices, for transitions at Vcc+Vtp and Vcc−Vtp, alternative approaches may be used to accomplish the same purpose with different sensing mechanisms and sense points. For example, one or more comparators may be used to sense voltages that are closer to Vcc, such as Vcc+100 mV and Vcc−100 mV to reduce the voltage difference between the two sense points. In addition, the sense points may both occur above Vcc, such as at Vcc+200 mV and Vcc+100 mV. In another embodiment, a single sense point may be used, such as at Vcc+100 mV.
- Thus, embodiments of over-voltage tolerant circuits and methods have been described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
- The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
- Reference in the description to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the circuit or method. The appearances of the phrase one embodiment in various places in the specification do not necessarily all refer to the same embodiment.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/037,023 US8902554B1 (en) | 2013-06-12 | 2013-09-25 | Over-voltage tolerant circuit and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361834061P | 2013-06-12 | 2013-06-12 | |
US14/037,023 US8902554B1 (en) | 2013-06-12 | 2013-09-25 | Over-voltage tolerant circuit and method |
Publications (2)
Publication Number | Publication Date |
---|---|
US8902554B1 US8902554B1 (en) | 2014-12-02 |
US20140368960A1 true US20140368960A1 (en) | 2014-12-18 |
Family
ID=51948430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/037,023 Active 2033-10-07 US8902554B1 (en) | 2013-06-12 | 2013-09-25 | Over-voltage tolerant circuit and method |
Country Status (1)
Country | Link |
---|---|
US (1) | US8902554B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108255753B (en) * | 2016-12-28 | 2020-05-19 | 中芯国际集成电路制造(上海)有限公司 | I/O receiver and receiving circuit thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6781416B1 (en) * | 2001-12-19 | 2004-08-24 | Rambus Inc. | Push-pull output driver |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4140927A (en) | 1977-04-04 | 1979-02-20 | Teletype Corporation | Non-overlapping clock generator |
US5966036A (en) * | 1997-09-09 | 1999-10-12 | S3 Incorporated | System and method for a mixed voltage drive system for floating substrate technology |
US6979908B1 (en) * | 2000-01-11 | 2005-12-27 | Texas Instruments Incorporated | Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements |
US6664815B2 (en) | 2000-12-08 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Output driver circuit with current detection |
US20040255193A1 (en) | 2003-06-12 | 2004-12-16 | Larson Thane M. | Inter integrated circuit router error management system and method |
FR2875950B1 (en) * | 2004-09-28 | 2008-04-04 | Atmel Corp | TOLERANT STRUCTURE AT VOLTAGE FOR INPUT / OUTPUT CELLS |
US7138830B2 (en) * | 2004-12-29 | 2006-11-21 | Texas Instrument Incorporated | Supply enabled optimization output buffer |
US7348803B2 (en) | 2005-06-24 | 2008-03-25 | Integrated Electronic Solutions Pty. Ltd. | Bi-directional bus buffer |
CN102099993B (en) * | 2008-07-17 | 2014-10-29 | 亚德诺半导体股份有限公司 | A controlled overlap driver circuit |
CN102629241B (en) | 2012-03-13 | 2015-04-15 | 华为技术有限公司 | Isolation circuit of inter-integrated circuit (I2C) bus and I2C bus system |
-
2013
- 2013-09-25 US US14/037,023 patent/US8902554B1/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6781416B1 (en) * | 2001-12-19 | 2004-08-24 | Rambus Inc. | Push-pull output driver |
US7015721B2 (en) * | 2001-12-19 | 2006-03-21 | Rambus Inc. | Push-pull output driver |
Also Published As
Publication number | Publication date |
---|---|
US8902554B1 (en) | 2014-12-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9257973B1 (en) | Supply-state-enabled level shifter interface circuit and method | |
US10305474B2 (en) | High voltage output driver with low voltage devices | |
US20070247772A1 (en) | Esd clamp control by detection of power state | |
US8395433B2 (en) | Input-output device protection | |
US9748957B2 (en) | Voltage level shifter circuit, system, and method for wide supply voltage applications | |
US8395870B2 (en) | Input/output circuit | |
US20060181322A1 (en) | Input circuits configured to operate using a range of supply voltages | |
KR20140129159A (en) | Surge protection for differential input/output interfaces | |
US8004313B2 (en) | Methods, devices, and systems for a high voltage tolerant buffer | |
US7355447B2 (en) | Level shifter circuit | |
US6313672B1 (en) | Over-voltage tolerant integrated circuit I/O buffer | |
US6225824B1 (en) | High speed output buffer for high/low voltage operation | |
US7652511B2 (en) | Slew-rate control circuitry with output buffer and feedback | |
US6313661B1 (en) | High voltage tolerant I/O buffer | |
US7659748B2 (en) | Electronic device and integrated circuit | |
US7239177B2 (en) | High voltage tolerant off chip driver circuit | |
JP2009514436A (en) | High voltage tolerance port driver | |
US8018268B1 (en) | Over-voltage tolerant input circuit | |
US6222387B1 (en) | Overvoltage tolerant integrated circuit input/output interface | |
US6313671B1 (en) | Low-power integrated circuit I/O buffer | |
US8902554B1 (en) | Over-voltage tolerant circuit and method | |
KR20010040990A (en) | Overvoltage-protected i/o buffer | |
EP0735686B1 (en) | Three-state CMOS output buffer circuit | |
KR19980033221A (en) | High-Voltage Tolerant Tri-State Output Buffers | |
US6040711A (en) | CMOS output buffer having a switchable bulk line |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DEO, SUPREET BHANJA;WILLIAMS, TIMOTHY;MADDEN, PAT;SIGNING DATES FROM 20130924 TO 20130925;REEL/FRAME:031281/0039 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:035240/0429 Effective date: 20150312 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MUFG UNION BANK, N.A., CALIFORNIA Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050896/0366 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:058002/0470 Effective date: 20150312 |
|
AS | Assignment |
Owner name: SPANSION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |