US20170048430A1 - Solid-state imaging element and camera system - Google Patents
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Definitions
- the present technology relates to a solid-state imaging element represented by a CMOS image sensor and a camera system.
- a solid-state imaging element is configured to have a photoelectric conversion unit, a charge voltage conversion unit which converts accumulated charges into a voltage, and a unit pixel with an amplifying circuit for reading the voltage of the charge voltage conversion unit.
- FIG. 1 is a diagram showing a basic configuration of a solid-state imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2006-049361.
- pixel cells 2 are arranged in an array shape on a first semiconductor layer 1 - 1 in the light sensing part side, row scanning circuits 3 - 1 and 3 - 2 are arranged in both sides of the array part, and pixel driving circuits 4 - 1 and 4 - 2 are arranged corresponding to the rows of the pixel cells 2 .
- FIG. 2 is a diagram showing an example of a pixel of a CMOS image sensor which includes four transistors.
- the pixel cells 2 include a photoelectric conversion unit (photoelectric conversion element) 21 composed of, for example, a photodiode (PD).
- a photoelectric conversion unit (photoelectric conversion element) 21 composed of, for example, a photodiode (PD).
- the pixel cells 2 include four transistors including a transfer transistor 22 , a reset transistor 23 , an amplifying transistor 24 , and a selection transistor 25 for the one photoelectric conversion unit 21 as active elements.
- the photoelectric conversion unit 21 performs photoelectric conversion of incident light into charges (herein, electrons) in an amount corresponding to the quantity of the light.
- the transfer transistor 22 is connected between the photoelectric conversion unit 21 and a floating diffusion FD as an output node, and the gate thereof (transfer gate) is given a transfer signal TRG that is a control signal through a transfer control line LTRG.
- the transfer transistor 22 transfers the electrons photoelectrically converted in the photoelectric conversion unit 21 to the floating diffusion FD.
- the reset transistor 23 is connected between a power supply line LVDD and the floating diffusion FD, and the gate thereof is given a reset signal RST that is a control signal through a reset control line LRST.
- the reset transistor 23 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD.
- the gate of the amplifying transistor 24 is connected to the floating diffusion FD.
- the amplifying transistor 24 is connected to an output signal line 6 through the selection transistor 25 , and constitutes a source follower as a constant current source outside the pixel part.
- the amplifying transistor 24 and the selection transistor 25 form an amplifying circuit 7 .
- a selection signal SEL that is a control signal is given to the gate of the selection transistor 25 through a selection control line LSEL according to an address signal to turn on the selection transistor 25 .
- the amplifying transistor 24 amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to the output signal line 6 .
- FIG. 3 is a diagram showing an example of pixel sharing of a COMS image sensor.
- the pixel cells of FIG. 2 that have one amplifying circuit 7 for one photoelectric conversion unit 21 formed on the first semiconductor layer 1 - 1 , the pixel cells of FIG. 3 that have one amplifying circuit 7 for a plurality of photoelectric conversion units 21 , or the like is applied as shown in FIG. 1 .
- the solid-state imaging element in Japanese Unexamined Patent Application Publication No. 2006-049361 has a structure in which stack-connecting terminals (micro-bumps or through holes VIA) 8 that propagate signals to a different stacked second semiconductor layer 1 - 2 are connected in the pixel cells 2 .
- each of the stack-connecting terminals 8 is connected to the amplifying circuit 7 that reads signals.
- a bias transistor (load MOS) 9 that functions as a constant current source of a source follower is formed on the second semiconductor layer 1 - 2 .
- the output of the amplifying circuits of a plurality of pixel cells shares an output signal line connected to the stack-connecting terminals as shown in FIG. 4 .
- FIG. 5 is a diagram showing an example of principal circuits of the solid-state imaging element of FIG. 4 .
- output terminals of the amplifying circuits 7 reading the plurality of pixel cells are connected to the same output signal line 6 , and the connection node thereof is connected to the second semiconductor layer 1 - 2 through the stack-connecting terminal 8 .
- the pixel cells 2 include a plurality of photoelectric conversion units (PD) as shown in FIG. 2 , and it does not matter to share the amplifying circuit 7 .
- PD photoelectric conversion units
- the amplifying circuit 7 includes the selection transistor 25 in addition to the amplifying transistor 24 , and is connected to the output signal line 6 through the selection transistor 25 .
- parasitic capacitance of a source terminal of the amplifying transistor 24 parasitic capacitance of a source terminal of the selection transistor 25 , or parasitic capacitance of wiring is added as load capacity.
- the time necessary for converging an output signal after the selection of a pixel on a target value is lengthened, thereby obstructing speed-up.
- a solid-state imaging element which includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, and in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line which is wired from the stack-connecting part, and the output signal line has a separation part which can separate each output signal line that is arbitrarily branched at all or some locations branched from the stack-connecting part.
- a camera system which includes a solid-state imaging element, an optical system which forms an image of a subject on the imaging element, and a signal processing circuit which processes an output image signal of the imaging element
- the solid-state imaging element includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that have a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals by the signal output part of the pixel cells are propagated
- the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells is arrayed in a two-dimensional shape, a signal output part of a pixel group formed with the plurality of pixel cells shares the output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each
- FIG. 1 is a diagram showing a basic configuration of a solid-state imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2006-049361;
- FIG. 2 is a diagram showing an example of a pixel of a CMOS image sensor including four transistors
- FIG. 3 is a diagram showing an example of pixel sharing of a CMOS image sensor
- FIG. 4 is a diagram showing a configuration example of a solid-state imaging element in which the output of amplifying circuits of a plurality of pixel cells shares an output signal line connected to stack-connecting terminals;
- FIG. 5 is a diagram showing an example of principal circuits of the solid-state imaging element of FIG. 4 ;
- FIG. 6 is a diagram showing a configuration example of a CMOS image sensor (solid-state imaging element) according to an embodiment of the present technology
- FIG. 7 is a diagram showing an example of a pixel of the CMOS image sensor including four transistors according to the embodiment.
- FIG. 8 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a first embodiment of the technology;
- FIG. 9 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) of FIG. 8 ;
- FIG. 10 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according to a second embodiment of the technology
- FIG. 11 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a third embodiment of the technology;
- FIG. 12 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according of FIG. 11 ;
- FIG. 13 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fourth embodiment of the technology;
- FIGS. 14A to 14D-3 are diagrams illustrating an arrangement example of the pixels, the stack-connecting terminals, and the separation parts in detail according to the fourth embodiment
- FIGS. 15A and 15B are diagrams showing examples in which the elements are arranged so that switches and dummy transistors of the separation parts at branch points hold periodicity;
- FIG. 16 is a diagram showing an example in which the elements are arranged so that switches and dummy transistors of the separations part at branch points hold periodicity, and the dummy transistors have a predetermined function;
- FIG. 17 is a diagram showing a layout example when a stack-connecting terminal is shared in 4 ⁇ 4 pixel cells
- FIG. 18 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fifth embodiment of the technology;
- FIG. 19 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a sixth embodiment of the technology;
- FIG. 20 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a seventh embodiment of the technology;
- FIG. 21 is a diagram showing a stacking structure example of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a eighth embodiment of the technology;
- FIG. 22 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a ninth embodiment of the technology.
- FIG. 23 is a diagram showing an example of a configuration of a camera system to which the solid-state imaging elements according to the embodiments of the technology are applied.
- FIG. 6 is a diagram showing a configuration example of a CMOS image sensor (solid-state imaging element) according to an embodiment of the technology.
- the CMOS image sensor 100 includes a pixel array part 110 , a row selection circuit (Vdec) 120 as a pixel driving unit, and a readout circuit (AFE) 130 .
- Vdec row selection circuit
- AFE readout circuit
- the pixel array part 110 is arranged with a plurality of pixel cells 110 A in a two-dimensional shape (matrix shape) with M rows ⁇ N columns.
- FIG. 7 is a diagram showing an example of a pixel of the CMOS image sensor including four transistors according to the embodiment.
- the pixel cell 110 A includes a photoelectric conversion unit (photoelectric conversion element) 111 including, for example, a photodiode (PD).
- a photoelectric conversion unit photoelectric conversion element 111 including, for example, a photodiode (PD).
- the pixel cell 110 A has four transistors including a transfer transistor 112 , a reset transistor 113 , an amplifying transistor 114 , and a selection transistor 115 as active elements for the one photoelectric conversion unit 111 .
- the photoelectric conversion unit 111 performs photoelectric conversion for incident light into charges (herein, electrons) in an amount corresponding to the quantity of the light.
- the transfer transistor 112 is connected between the photoelectric conversion unit 111 and a floating diffusion FD as an output node, and the gate thereof (transfer gate) is given a transfer signal TRG that is a control signal through a transfer control line LTRG.
- the transfer transistor 112 transfers the electrons photoelectrically converted in the photoelectric conversion unit 111 to the floating diffusion FD.
- the reset transistor 113 is connected between a power supply line LVREF and the floating diffusion FD, and the gate thereof is given a reset signal RST that is a control signal through a reset control line LRST.
- the reset transistor 113 resets the potential of the floating diffusion FD to the potential of the power supply line LVREF.
- the floating diffusion FD is connected to the gate of the amplifying transistor 114 .
- the amplifying transistor 114 is connected to an output signal line 116 through the selection transistor 115 , and constitutes a source follower as a constant current source outside the pixel part.
- An amplifying circuit 117 is formed with the amplifying transistor 114 and the selection transistor 115 as a signal output part.
- a selection signal SEL that is a control signal corresponding to an address signal is given to the gate of the selection transistor 115 through a selection control line LSEL to turn on the selection transistor 115 .
- the amplifying transistor 114 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the output signal line 116 .
- the voltage output from each pixel is output to a readout circuit 130 through the output signal line 116 .
- the amplifying circuit 117 includes the selection transistor 115 in addition to the amplifying transistor 114 , and is connected to the output signal line 116 via the selection transistor 115 .
- the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired in the pixel array part 110 are wired in a row unit of the pixel array.
- the reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are driven by the row selection circuit 120 .
- the row selection circuit 120 controls an operation of a pixel arranged in an arbitrary row in the pixel array part 110 .
- the row selection circuit 120 functions as a pixel driving unit which controls the driving of a pixel through the control lines LSEL, LRST, and LTRG.
- the readout circuit 130 performs a predetermined process for a signal VSL output through the output signal line 116 from each pixel cell 110 A in a read row that is selected or pre-selected by driving of the row selection circuit 120 , and temporarily retains a pixel signal that is, for example, subjected to a signal processing.
- the readout circuit 130 is applicable to a configuration of a circuit including a sample-and-hold circuit that performs sampling and holding for a signal output through the output signal line 116 .
- the readout circuit 130 includes a sample-and-hold circuit, and is applicable to a configuration of a circuit with a function of removing a reset noise and a fixed-pattern noise specified for a pixel such as unevenness in threshold values of the amplifying transistor 114 by a CDS (Correlated Double Sampling) process.
- CDS Correlated Double Sampling
- the readout circuit 130 is equipped with an analog and digital (AD) converting function, and is applicable to a configuration in which a signal level is set to a digital signal.
- AD analog and digital
- CMOS image sensor (solid-state imaging element) 100 basically, a plurality of stacked semiconductor layers is electrically connected to one another with a plurality of stack-connecting terminals (stack-connecting part).
- the photoelectric conversion unit 111 and unit pixel cells 110 A having signal output parts are two-dimensionally arrayed on a first semiconductor layer.
- the signal output parts of a pixel group including a plurality of pixel cells share the output signal line 116 wired from the stack-connecting terminal.
- the output signal line 116 has a separation part which can separate each output signal line 116 that is arbitrarily branched in all or some of the locations branched from the stack-connecting terminal.
- an output of the amplifying circuit 117 that includes a plurality of amplifying transistors is connected to the stack-connecting terminal, and some or all of branch points between stack-connecting terminals and the amplifying circuits 117 have a separation part which separates the output signal line 116 .
- the CMOS image sensor (solid-state imaging element) 100 has a light-irradiated face, for example, at the opposite side of the face where transistors and wires are arranged.
- CMOS image sensor 100 when an output signal is propagated to the first semiconductor layer and a different semiconductor layer that are stacked through stack-connecting terminals, the degree of freedom for arranging the stack-connecting terminals rises, and transistors can be additionally arranged within a pixel array in small numbers without downscaling the photoelectric conversion unit.
- a stack-connecting terminal is characteristic in that the terminal is arranged in the vicinity of the center of the pixel group connected thereto.
- the stack-connecting terminal can evenly divide parasitic capacitance of each wiring separated at a separation part by being arranged in the vicinity of the center of the pixel group connected thereto in the range of intervals in which stack-connecting terminals can be satisfactorily arranged.
- the branch point is characteristic in that the branch point is arranged in the vicinity of the center of the pixel group which is connected after the branch point.
- the branch point can evenly divide parasitic capacitance of each wiring separated at the separation part by arranging the branch point in the vicinity of the center of the pixel group which is connected after the branch point.
- the separation part arranged in the branch point is characteristic in that an element same as the separation part is dummy-arranged in an area where a separation part is not arranged so as to have periodicity in arrangement.
- the pixel group that is two-dimensionally arrayed is connected to the same stack-connecting terminal.
- the amplifying transistor 114 in a pixel, and the source follower circuit including a constant current source by the bias transistor connected to the output signal line 116 can be exemplified.
- the parasitic capacitance of the output signal line 116 is discharged with a constant current, particularly, capacitance components are dominant at a convergence time of output, it is possible to attain speed-up or low power consumption in proportion to the separation of the capacitance.
- An input voltage of a source follower circuit is output to a source terminal of the amplifying transistor 114 .
- the output voltage in the stack-connecting terminal is offset by a product of wiring resistance from the amplifying transistor 114 to the stack-connecting terminal as an output terminal and a constant current generated in the load MOS (bias transistor) that is the current source.
- the offset voltage can be easily cancelled by a CDS unit such as a correlated double sampling, but if the voltage differs for each pixel, a sufficient margin is necessary for a voltage range that can be input to an analog signal processing circuit such as an analog and digital conversion circuit after the output terminal.
- FIG. 8 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a first embodiment of the technology.
- CMOS image sensor solid-state imaging element
- FIG. 9 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) of FIG. 8 .
- pixel cells 110 A are arranged on a first semiconductor layer 200 in an array shape.
- Row scanning circuits 121 - 1 and 121 - 2 are arranged on the both sides of the pixel array part 110 , and pixel driving circuits 122 - 1 and 122 - 2 are arranged corresponding to rows of the pixel cells 110 A.
- an amplifying circuit 117 of the pixel cell 110 A shares the output signal lines 116 in the column direction and is connected to a stack-connecting terminal 118 .
- a separation part 140 of the output signal line 116 is provided on a location where the output signal line 116 branches between the stack-connecting terminal 118 and the amplifying circuit 117 of each pixel cell.
- pixel cells are arranged in a 6 ⁇ 6 matrix shape.
- the stack-connecting terminal 118 may be arranged at the center of a pixel group of a plurality of pixel cells 110 A connected thereto in the range of a minimum interval between stack-connecting terminals that can be produced.
- the stack-connecting terminals 118 are positioned in between the formation locations of the third and fourth pixel cells in columns CL 0 to CL 5 , that is, at the center of each column, in the pixel array of FIG. 8 .
- the stack-connecting terminals are arranged in the vicinity of the center within the range where the terminals can be arranged as shown in FIG. 8 .
- the stack-connecting terminals 118 are arranged in between the formation locations of the fourth and the fifth pixel cells, that is, in the vicinity of the center within the range where the terminals can be arranged, in the even columns CL 0 , CL 2 , and CL 4 .
- the stack-connecting terminals 118 are arranged in between the formation locations of the second and the third pixel cells, that is, in the vicinity of the center within the range where the terminals can be arranged, in the odd columns CL 1 , CL 3 , and CL 5 .
- the separation part 140 is arranged so as to be separated in the stacking direction and to overlap the stack-connecting terminal 118 .
- FIG. 9 includes four pixel cells 110 A- 1 to 110 A- 4 for simplification, and shows an example where the stack-connecting terminal 118 and the separation part 140 are arranged substantially at the center of the pixel group.
- the separation part 140 at the branch point includes a switch 141 , and separates the output signal line 116 into two output signal line 116 - 1 and 116 - 2 .
- the output signal line 116 - 1 is connected to the amplifying circuits 117 of the pixel cells 110 A- 1 and 110 A- 2 and the output signal line 116 - 2 is connected to the amplifying circuits 117 of the pixel cells 110 A- 3 and 110 A- 4 .
- the switch 141 that constitutes the separation part 140 includes a pair of terminals a and b and a pair of terminals c and d.
- the terminal a is connected to the stack-connecting terminal 118 and the terminal b is connected to the one output signal line 116 - 1 .
- the terminal c is connected to the stack-connecting terminal 118 and the terminal d is connected to the other output signal line 116 - 2 .
- the terminals a and b and the terminals c and d are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing.
- the switch 141 can be realized with a sample circuit in which either or both a NMOS transistor and a PMOS transistor are connected thereto in parallel, or the like.
- a bias transistor (load MOS) 119 which functions as a constant current source of the source follower is formed on the second semiconductor layer 210 .
- the bias transistor 119 has a function of inputting a bias voltage Vb to a gate so that a constant current flows from the output signal line 116 .
- the bias transistor 119 may be arranged in the first semiconductor layer 200 .
- FIG. 10 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according to a second embodiment.
- a point that the CMOS image sensor 100 B according to the second embodiment differs from the CMOS image sensor 100 A according to the first embodiment is that the number of branches of the output signal line 116 by a separation part 140 B is not two but more than that (herein, three branches).
- the output signal line 116 is branched into three output signal lines 116 - 1 , 116 - 2 , and 116 - 3 .
- the amplifying circuits 117 of the pixel cells 110 A- 5 and 110 A- 6 are connected to the output signal line 116 - 3 .
- a switch 141 B includes a pair of terminals e and f in addition to the configuration of FIG. 9 .
- terminal e is connected to the stack-connecting terminal 118 and the terminal f is connected to the output signal line 116 - 3 .
- the terminals a and b, the terminals c and d, and the terminals e and f are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing.
- FIG. 11 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts on a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a third embodiment of the technology.
- CMOS image sensor solid-state imaging element
- FIG. 12 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) of FIG. 11 .
- the CMOS image sensor 100 C is configured to have pixel groups sharing the stack-connecting terminals 118 , including pixels arranged perpendicular (the horizontal direction in FIG. 11 ) to the readout scanning direction of pixels (the vertical direction in FIG. 11 ).
- each of two columns of the zeroth and the first columns, the second and the third columns, and the fourth and the fifth columns shares one stack-connecting terminal 118 .
- an output line L 141 which extends from the output of the separation part 140 - 1 that is arranged in the middle of the even-numbered column and an output line L 142 wired so as to return to the even-numbered column side from the output of the separation part 140 - 2 in the odd-numbered column side are connected to the separation part 140 - 3 arranged at a first branch point.
- the separation parts 140 - 0 and 140 - 1 form a second branch point, and basically have the same configuration as in the first embodiment.
- a switch 141 - 3 constituting the separation part 140 - 3 at the first branch point includes a pair of terminals g and h, and a pair of terminals i and j.
- the terminal g is connected to the stack-connecting terminal 118 and the terminal h is connected to the one output line L 141 .
- the terminal i is connected to the stack-connecting terminal 118 and the terminal j is connected to the other output line L 142 .
- the terminals g and h and the terminals i and j are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing.
- the first separation part 140 - 3 is positioned at the first branch point that branches first from the stack-connecting terminal 118 and the second separation parts 140 - 1 and 140 - 2 are positioned at the second branch point that branches after that.
- a plurality of pixels included in the same pixel group is simultaneously selected by readout scanning, but any one of the pixels that is simultaneously selected is connected to the stack-connecting terminal 118 by the first or the second separation part.
- the number of pixel cells connected to the stack-connecting terminal 118 during reading of pixels is reduced to one fourth of a case where a separation part is not provided, whereby it is possible to speed-up and low power consumption by a decrease in parasitic capacitance.
- both the first and the second branch points have separation parts, but it does not matter that either of the branch points has a separation part.
- FIG. 13 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts on a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fourth embodiment of the technology.
- CMOS image sensor solid-state imaging element
- FIGS. 14A to 14D-3 are diagrams illustrating an arrangement example of the pixels, the stack-connecting terminals, and the separation parts in detail according to the fourth embodiment.
- pixel cells are arranged in a 6 ⁇ 6 matrix shape.
- FIG. 13 shows an arrangement example when a 4 ⁇ 4 pixel cell group GRP shares one stack-connecting terminal 11 as an example.
- the stack-connecting terminal 118 In order to minimize the length of wiring to the furthest pixel, it is preferable to arrange the stack-connecting terminal 118 in the vicinity of the center of the 4 ⁇ 4 pixel cell group GRP.
- the first branch point at which the first separation part 140 - 3 is arranged in the vicinity of the center of the pixel cell group GRP, as shown in FIG. 14A .
- the second separation parts 140 - 1 and 140 - 2 of the second branch point are arranged around of the center of each pixel cell group GRP separated by the first branch point.
- a third separation part 140 - 4 of a third branch point is arranged around the center of each pixel cell group GRP separated by the second branch points 140 - 1 and 140 - 2 .
- the configuration of the arrangement of the separation parts and the output single lines 116 as shown in FIG. 14D is preferable to minimize wiring capacity or wiring resistance.
- a dummy transistor DMT as a dummy element at a location where separation means is not arranged in consideration of periodicity in the arrangement of the separation means.
- the dummy transistors DMT are arranged instead of the second separation parts 140 - 1 and 140 - 2 .
- FIGS. 15A and 15B are diagrams showing an example in which elements are arranged so that switches of separation parts at branch points and dummy transistors hold periodicity.
- FIGS. 15A and 15B are circuit diagrams corresponding to FIG. 14D-3 , and the elements are arranged therein so that the switches of the separation parts at the branch points and the dummy transistors hold periodicity.
- the dummy transistor DMT of FIG. 15B is configured such that, as an example, the gates, the drains, and the sources of two NMOS transistors NT 1 and NT 2 which form the switch of the separation part and are cascade-connected to each other are grounded.
- FIG. 16 is a diagram showing an example in which the elements are arranged so that the switches of the separation parts at the branch points and the dummy transistors hold periodicity and the dummy transistors have a predetermined function.
- the dummy transistor DMT can be configured to have any function.
- the dummy transistor DMT is caused to function as a constant current source I 1 of a source follower.
- the source of the NMOS transistor NT 1 is grounded, the drain of the NMOS transistor NT 2 is connected to the output signal line 116 , and the gates of both NMOS transistors NT 1 and NT 2 are connected to the power supply for the bias voltage Vb to constitute the constant current source I 1 .
- FIG. 17 is a diagram showing a layout example when a 4 ⁇ 4 pixel cells share the stack-connecting terminal.
- a separation part without reducing the area of a light sensing part in a rear surface irradiation type image sensor in which photoelectric conversion is performed by irradiating a surface opposite to a transistor-arranged surface with light, or an image sensor in which a photoelectric conversion film is formed upper than a wiring layer.
- FIG. 18 is a diagram showing a stacking structure example of a first semiconductor layer and the second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fifth embodiment of the technology.
- CMOS image sensor solid-state imaging element
- a wiring layer 202 is formed on a silicon (Si) substrate (p-well) 201 .
- n-type diffusion region 2011 is formed on the Si substrate 201 as a photoelectric conversion unit (PD) 111 , and a p+ type diffusion region 2012 is formed over the surface part of the photoelectric conversion unit 111 (the boundary between the wiring layer 202 ).
- n+ diffusion regions 2013 of FDs and n+ diffusion regions 2014 of the transistors for the switches of the separation parts 140 are formed in plural over the surface part in the Si substrate 201 .
- a gate wiring 2021 and a signal propagation wiring 2022 of each transistor are formed in an insulating layer such as SiO 2 , and a micro-pad 2023 formed of Cu, or the like is formed over the surface part thereof.
- a via (VIA) 2024 is formed in the wiring layer 202 in order to connect a n+ diffusion region 2014 of the separation part 140 to the micro-pad 2023 .
- a wiring layer 212 is formed on a Si substrate 211 .
- Diffusion regions 2111 and 2112 of transistors are formed in the surface part on the Si substrate 211 .
- a gate wiring 2121 and a signal propagation wiring 2122 of each transistor are formed in an insulating layer such as SiO 2 , and a micro-pad 2123 formed of Cu, or the like is formed over the surface part thereof.
- a via (VIA) 2124 is formed in the wiring layer 212 in order to connect a diffusion region 2111 and the like to a micro-pad 2123 .
- a CMOS image sensor (solid-state imaging element) 100 E of FIG. 18 is an image sensor in which the photoelectric conversion unit 111 is formed on the semiconductor face opposite to the transistors and the wiring layers and the rear surface is irradiated with light, using a micro-bump BMP as the stack-connecting terminal 118 .
- the surface part of the wiring layer 202 of the first semiconductor layer 200 and the surface part of the wiring layer 212 of the second semiconductor part 210 are opposed to each other to connect the micro-pad 2023 and the micro-pad 2123 with the micro-bump BMP.
- FIG. 19 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a sixth embodiment of the technology.
- CMOS image sensor solid-state imaging element
- a point that an image sensor 100 F according to the sixth embodiment differs from the image sensor 100 E according to the fifth embodiment is that the micro-pad 2023 and the micro-pad 2123 as the uppermost wiring are connected to each other without using a micro-bump.
- FIG. 20 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a seventh embodiment of the technology.
- CMOS image sensor solid-state imaging element
- Point that an image sensor 100 G according to the seventh embodiment differs from the image sensor 100 F according to the sixth embodiment are as follows.
- the Si substrate 211 of the second semiconductor layer 210 is arranged in the surface side of the wiring 202 of the first semiconductor layer 200 .
- micro-pad 2123 of the wiring layer 212 of the second semiconductor layer 210 is connected to the micro-pad 2023 of the wiring layer 202 of the first semiconductor layer 200 by a through hole VIA electrode 213 that penetrates the second semiconductor layer 210 .
- the wiring 2122 of the wiring layer 212 of the second semiconductor layer 210 is connected to the wiring 2022 of the wiring layer 202 of the first semiconductor layer 200 by a through hole VIA electrode 214 that penetrates the second semiconductor layer 210 .
- FIG. 21 is a diagram showing a stacking structure example of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer of a CMOS image sensor (solid-state imaging element) according to an eighth embodiment of the technology.
- CMOS image sensor solid-state imaging element
- the CMOS image sensor 100 H has a stacking structure of the first semiconductor layer 200 , the second semiconductor layer 210 , and a third semiconductor layer 230 .
- a wiring layer 222 is formed on a Si substrate 221 .
- diffusion regions 2211 and 2212 of transistors are formed in the surface part.
- a gate wiring 2221 and a signal propagation wiring 2222 of each transistor are formed in an insulating layer such as SiO 2 , and a micro-pad 2223 formed of Cu, or the like is formed over the surface part thereof.
- a via (VIA) 2224 is formed in the wiring layer 222 in order to connect the diffusion region 2211 and the wiring 2222 or the wiring 2222 and the micro-pad 2223 .
- a photoelectric conversion film 240 is formed on the wiring layer 202 of the first semiconductor layer 200 , and the wiring 2022 of the first semiconductor layer 200 and the wiring 2122 of the second semiconductor layer 210 are connected by a through hole VIA 203 which penetrates the first semiconductor layer 200 .
- micro-pad 2123 of the wiring layer 212 of the second semiconductor layer 210 and the micro-pad 2223 of the wiring layer 222 of the third semiconductor layer 220 are connected by a through hole VIA electrode 213 H which penetrates the second semiconductor layer 210 .
- the semiconductor layer may be stacked with any number of layers.
- a photoelectric conversion layer is formed on a layer different from the transistors within the first semiconductor layer 200 , it is possible to arrange separation means and stack-connecting terminals with a high degree of freedom without reducing the area of light sensing elements.
- FIG. 22 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a ninth embodiment of the technology.
- CMOS image sensor solid-state imaging element
- the first semiconductor layer 200 is formed in the same layout as in FIG. 13
- the second semiconductor layer 210 is formed with an AD conversion unit 150 and a signal processing unit 160 .
- one signal processing unit 160 is arranged in the center part, and respective two AD conversion units 150 are arranged in both sides of long edge parts.
- AD conversion circuits 151 , 152 , 153 , and 154 are arranged in respectively parallel with each stack-connecting terminal 118 .
- the pixel cells have amplifying circuits for signal output, a pixel sharing type in which a plurality of light sensing elements shares the amplifying circuits, a pixel configuration in which a charge holding region that realizes batch exposure is provided in a pixel, or the like is also acceptable.
- a solid-state imaging element that brings the above effects can be applied as an imaging device of a digital camera or a video camera.
- FIG. 23 is a diagram showing an example of a configuration of a camera system to which the solid-state imaging elements according to the embodiments of the technology are applied.
- the camera system 300 is provided with an imaging device 310 to which one of the CMOS image sensors (solid-state imaging elements) 100 and 100 A to 100 I according to the embodiments is applicable, as shown in FIG. 23 .
- CMOS image sensors solid-state imaging elements
- the camera system 300 includes an optical system that leads incident light to a pixel region of the imaging device 310 (forms the image of a subject), for example, a lens 320 that forms an image on an imaging plane with the incident light (image light).
- the camera system 300 includes a driving circuit (DRV) 330 which drives the imaging device 310 and a signal processing circuit (PRC) 340 which processes output signals of the imaging device 310 .
- DUV driving circuit
- PRC signal processing circuit
- the driving circuit 330 has a timing generator (not shown in the drawing) which generates various timing signals including start pulses and clock pulses that drive circuits in the imaging device 310 and drives the imaging device 310 with a predetermined time signal.
- the signal processing circuit 340 performs a predetermined signal process for output signals of the imaging device 310 .
- the image signals processed in the signal processing circuit 340 are recorded on a recording medium, for example, a memory, or the like. Image information recorded on the recording medium is made into hard copy by a printer, or the like. In addition, the image signals processed in the signal processing circuit 340 are displayed as moving images on a monitor including a liquid crystal display or the like.
Abstract
A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.
Description
- This application is a continuation of U.S. patent application Ser. No. 13/218,979 filed Aug. 26, 2011, the entirety of which is incorporated herein by reference to the extent permitted by law. The present application claims the benefit of priority to Japanese Patent Application No. JP 2010-197734 filed on Sep. 3, 2010 in the Japan Patent Office, the entirety of which is incorporated by reference herein to the extent permitted by law.
- The present technology relates to a solid-state imaging element represented by a CMOS image sensor and a camera system.
- A solid-state imaging element is configured to have a photoelectric conversion unit, a charge voltage conversion unit which converts accumulated charges into a voltage, and a unit pixel with an amplifying circuit for reading the voltage of the charge voltage conversion unit.
- There has been a proposed technology with regard to such a solid-state imaging element in which the opposite side (=back face) of a face where transistors are arranged is set to a light-irradiated face, and a plurality of semiconductor layers is stacked to read an output signal of pixels, thereby improving the degree of integration and parallelism.
- The technology is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2006-049361.
-
FIG. 1 is a diagram showing a basic configuration of a solid-state imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2006-049361. - In
FIG. 1 ,pixel cells 2 are arranged in an array shape on a first semiconductor layer 1-1 in the light sensing part side, row scanning circuits 3-1 and 3-2 are arranged in both sides of the array part, and pixel driving circuits 4-1 and 4-2 are arranged corresponding to the rows of thepixel cells 2. -
FIG. 2 is a diagram showing an example of a pixel of a CMOS image sensor which includes four transistors. - The
pixel cells 2 include a photoelectric conversion unit (photoelectric conversion element) 21 composed of, for example, a photodiode (PD). - In addition, the
pixel cells 2 include four transistors including atransfer transistor 22, areset transistor 23, anamplifying transistor 24, and aselection transistor 25 for the onephotoelectric conversion unit 21 as active elements. - The
photoelectric conversion unit 21 performs photoelectric conversion of incident light into charges (herein, electrons) in an amount corresponding to the quantity of the light. - The
transfer transistor 22 is connected between thephotoelectric conversion unit 21 and a floating diffusion FD as an output node, and the gate thereof (transfer gate) is given a transfer signal TRG that is a control signal through a transfer control line LTRG. - Accordingly, the
transfer transistor 22 transfers the electrons photoelectrically converted in thephotoelectric conversion unit 21 to the floating diffusion FD. - The
reset transistor 23 is connected between a power supply line LVDD and the floating diffusion FD, and the gate thereof is given a reset signal RST that is a control signal through a reset control line LRST. - Accordingly, the
reset transistor 23 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD. - The gate of the amplifying
transistor 24 is connected to the floating diffusion FD. The amplifyingtransistor 24 is connected to anoutput signal line 6 through theselection transistor 25, and constitutes a source follower as a constant current source outside the pixel part. - The amplifying
transistor 24 and theselection transistor 25 form anamplifying circuit 7. - In addition, a selection signal SEL that is a control signal is given to the gate of the
selection transistor 25 through a selection control line LSEL according to an address signal to turn on theselection transistor 25. - If the
selection transistor 25 is turned on, the amplifyingtransistor 24 amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to theoutput signal line 6. -
FIG. 3 is a diagram showing an example of pixel sharing of a COMS image sensor. - In this configuration, four pixel cells 2-1 to 2-4 having each of photoelectric conversion elements 21-1 to 21-4 and transfer transistors 22-1 to 22-4 share the floating diffusion FD, the
reset transistor 23, and the amplifyingcircuit 7. - In the solid-state imaging element, the pixel cells of
FIG. 2 that have one amplifyingcircuit 7 for onephotoelectric conversion unit 21 formed on the first semiconductor layer 1-1, the pixel cells ofFIG. 3 that have one amplifyingcircuit 7 for a plurality ofphotoelectric conversion units 21, or the like is applied as shown inFIG. 1 . - In addition, the solid-state imaging element in Japanese Unexamined Patent Application Publication No. 2006-049361 has a structure in which stack-connecting terminals (micro-bumps or through holes VIA) 8 that propagate signals to a different stacked second semiconductor layer 1-2 are connected in the
pixel cells 2. - In other words, each of the stack-connecting
terminals 8 is connected to the amplifyingcircuit 7 that reads signals. - In the examples of
FIGS. 2 and 3 , a bias transistor (load MOS) 9 that functions as a constant current source of a source follower is formed on the second semiconductor layer 1-2. - When the size of a unit pixel is smaller than the size of the stack-connecting
terminal 8, it is difficult to arrange the stack-connectingterminals 8 for each of unit pixels in any event in the above-described related art. - For this reason, it is considered that the output of the amplifying circuits of a plurality of pixel cells shares an output signal line connected to the stack-connecting terminals as shown in
FIG. 4 . -
FIG. 5 is a diagram showing an example of principal circuits of the solid-state imaging element ofFIG. 4 . - In this example, output terminals of the amplifying
circuits 7 reading the plurality of pixel cells are connected to the sameoutput signal line 6, and the connection node thereof is connected to the second semiconductor layer 1-2 through the stack-connectingterminal 8. - The
pixel cells 2 include a plurality of photoelectric conversion units (PD) as shown inFIG. 2 , and it does not matter to share the amplifyingcircuit 7. - As described above, the amplifying
circuit 7 includes theselection transistor 25 in addition to the amplifyingtransistor 24, and is connected to theoutput signal line 6 through theselection transistor 25. - However, it is possible to omit the
selection transistor 25 by setting the voltage of the FD in a non-selected pixel to be low using thereset transistor 23 and by driving the amplifyingtransistor 24 to be in an OFF state. - In the configuration of
FIGS. 4 and 5 , when a pixel is selected by therow scanning circuit 3 and signals are output through the stack-connectingterminal 8, it is necessary to drive parasitic capacitance of the output terminal of the amplifyingcircuit 7 of other pixels connected to the same stack-connectingterminal 8. - In other words, parasitic capacitance of a source terminal of the amplifying
transistor 24, parasitic capacitance of a source terminal of theselection transistor 25, or parasitic capacitance of wiring is added as load capacity. - With an increase in the parasitic capacitance of the
output signal line 6 including the stack-connectingterminal 8, the time necessary for converging an output signal after the selection of a pixel on a target value is lengthened, thereby obstructing speed-up. - When it is necessary to perform a further speedy reading operation, elevating a current flowing into the amplifying
circuit 7 by changing, for example, a bias voltage Vb applied to the gate of thebias transistor 9 is considered, but an increase in power consumption results in proportion to increments of the current. - It is desirable for the technology to provide a solid-state imaging element and a camera system which enable the realization of speed increases in driving an output signal line of a pixel and low power consumption in a stacking structure.
- According to an embodiment of the present technology, there is provided a solid-state imaging element which includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, and in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line which is wired from the stack-connecting part, and the output signal line has a separation part which can separate each output signal line that is arbitrarily branched at all or some locations branched from the stack-connecting part.
- According to another embodiment of the technology, there is provided a camera system which includes a solid-state imaging element, an optical system which forms an image of a subject on the imaging element, and a signal processing circuit which processes an output image signal of the imaging element, and in which the solid-state imaging element includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that have a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals by the signal output part of the pixel cells are propagated, the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells is arrayed in a two-dimensional shape, a signal output part of a pixel group formed with the plurality of pixel cells shares the output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line that is arbitrarily branched at all or some locations branched from the stack-connecting parts.
- According to the technology, it is possible to realize speed-up in driving the output signal line in a pixel in a stacking structure and low power consumption.
-
FIG. 1 is a diagram showing a basic configuration of a solid-state imaging element disclosed in Japanese Unexamined Patent Application Publication No. 2006-049361; -
FIG. 2 is a diagram showing an example of a pixel of a CMOS image sensor including four transistors; -
FIG. 3 is a diagram showing an example of pixel sharing of a CMOS image sensor; -
FIG. 4 is a diagram showing a configuration example of a solid-state imaging element in which the output of amplifying circuits of a plurality of pixel cells shares an output signal line connected to stack-connecting terminals; -
FIG. 5 is a diagram showing an example of principal circuits of the solid-state imaging element ofFIG. 4 ; -
FIG. 6 is a diagram showing a configuration example of a CMOS image sensor (solid-state imaging element) according to an embodiment of the present technology; -
FIG. 7 is a diagram showing an example of a pixel of the CMOS image sensor including four transistors according to the embodiment; -
FIG. 8 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a first embodiment of the technology; -
FIG. 9 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) ofFIG. 8 ; -
FIG. 10 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according to a second embodiment of the technology; -
FIG. 11 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a third embodiment of the technology; -
FIG. 12 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according ofFIG. 11 ; -
FIG. 13 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fourth embodiment of the technology; -
FIGS. 14A to 14D-3 are diagrams illustrating an arrangement example of the pixels, the stack-connecting terminals, and the separation parts in detail according to the fourth embodiment; -
FIGS. 15A and 15B are diagrams showing examples in which the elements are arranged so that switches and dummy transistors of the separation parts at branch points hold periodicity; -
FIG. 16 is a diagram showing an example in which the elements are arranged so that switches and dummy transistors of the separations part at branch points hold periodicity, and the dummy transistors have a predetermined function; -
FIG. 17 is a diagram showing a layout example when a stack-connecting terminal is shared in 4×4 pixel cells; -
FIG. 18 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fifth embodiment of the technology; -
FIG. 19 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a sixth embodiment of the technology; -
FIG. 20 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a seventh embodiment of the technology; -
FIG. 21 is a diagram showing a stacking structure example of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a eighth embodiment of the technology; -
FIG. 22 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a ninth embodiment of the technology; and -
FIG. 23 is a diagram showing an example of a configuration of a camera system to which the solid-state imaging elements according to the embodiments of the technology are applied. - Hereinafter, embodiments of the technology will be described in relation to drawings.
- Description will be provided in the following order.
- 1. Example of Overall Configuration of Solid-state Imaging Element
- 2. Basic Concept of Characteristic Configuration for Adopting Stacking Structure
- 3. First Embodiment
- 4. Second Embodiment
- 5. Third Embodiment
- 6. Fourth Embodiment
- 7. Fifth Embodiment
- 8. Sixth Embodiment
- 9. Seventh Embodiment
- 10. Eighth Embodiment
- 11. Ninth Embodiment
- 12. Tenth Embodiment (Configuration Example of Camera System)
-
FIG. 6 is a diagram showing a configuration example of a CMOS image sensor (solid-state imaging element) according to an embodiment of the technology. - The
CMOS image sensor 100 includes apixel array part 110, a row selection circuit (Vdec) 120 as a pixel driving unit, and a readout circuit (AFE) 130. - In the present embodiment, the opposite side (=rear face) of a face on which transistors are arranged is set to a light-irradiated face as an example, and a plurality of semiconductor layers are stacked and formed so as to read output signals of pixels.
- A characteristic configuration corresponding to a stacking structure of the semiconductor layer will be described later.
- The
pixel array part 110 is arranged with a plurality ofpixel cells 110A in a two-dimensional shape (matrix shape) with M rows×N columns. -
FIG. 7 is a diagram showing an example of a pixel of the CMOS image sensor including four transistors according to the embodiment. - The
pixel cell 110A includes a photoelectric conversion unit (photoelectric conversion element) 111 including, for example, a photodiode (PD). - In addition, the
pixel cell 110A has four transistors including atransfer transistor 112, areset transistor 113, an amplifyingtransistor 114, and aselection transistor 115 as active elements for the onephotoelectric conversion unit 111. - The
photoelectric conversion unit 111 performs photoelectric conversion for incident light into charges (herein, electrons) in an amount corresponding to the quantity of the light. - The
transfer transistor 112 is connected between thephotoelectric conversion unit 111 and a floating diffusion FD as an output node, and the gate thereof (transfer gate) is given a transfer signal TRG that is a control signal through a transfer control line LTRG. - Accordingly, the
transfer transistor 112 transfers the electrons photoelectrically converted in thephotoelectric conversion unit 111 to the floating diffusion FD. - The
reset transistor 113 is connected between a power supply line LVREF and the floating diffusion FD, and the gate thereof is given a reset signal RST that is a control signal through a reset control line LRST. - Accordingly, the
reset transistor 113 resets the potential of the floating diffusion FD to the potential of the power supply line LVREF. - The floating diffusion FD is connected to the gate of the amplifying
transistor 114. The amplifyingtransistor 114 is connected to anoutput signal line 116 through theselection transistor 115, and constitutes a source follower as a constant current source outside the pixel part. - An amplifying
circuit 117 is formed with the amplifyingtransistor 114 and theselection transistor 115 as a signal output part. - In addition, a selection signal SEL that is a control signal corresponding to an address signal is given to the gate of the
selection transistor 115 through a selection control line LSEL to turn on theselection transistor 115. - If the
selection transistor 115 is turned on, the amplifyingtransistor 114 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to theoutput signal line 116. - The voltage output from each pixel is output to a readout circuit 130 through the
output signal line 116. - These operations are simultaneously performed for pixels of one row because, for example, the gates of the
transfer transistor 112, thereset transistor 113, and theselection transistor 115 are connected to one another in a row unit. - As described above, the amplifying
circuit 117 includes theselection transistor 115 in addition to the amplifyingtransistor 114, and is connected to theoutput signal line 116 via theselection transistor 115. - However, it is possible to omit the
selection transistor 115 by setting the voltage of the FD of a non-selected pixel to be low by thereset transistor 113 and driving the amplifyingtransistor 114 to be off. - The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL wired in the
pixel array part 110 are wired in a row unit of the pixel array. - The reset control line LRST, the transfer control line LTRG, and the selection control line LSEL are driven by the row selection circuit 120.
- The row selection circuit 120 controls an operation of a pixel arranged in an arbitrary row in the
pixel array part 110. The row selection circuit 120 functions as a pixel driving unit which controls the driving of a pixel through the control lines LSEL, LRST, and LTRG. - The readout circuit 130 performs a predetermined process for a signal VSL output through the
output signal line 116 from eachpixel cell 110A in a read row that is selected or pre-selected by driving of the row selection circuit 120, and temporarily retains a pixel signal that is, for example, subjected to a signal processing. - The readout circuit 130 is applicable to a configuration of a circuit including a sample-and-hold circuit that performs sampling and holding for a signal output through the
output signal line 116. - Alternatively, the readout circuit 130 includes a sample-and-hold circuit, and is applicable to a configuration of a circuit with a function of removing a reset noise and a fixed-pattern noise specified for a pixel such as unevenness in threshold values of the amplifying
transistor 114 by a CDS (Correlated Double Sampling) process. - In addition, the readout circuit 130 is equipped with an analog and digital (AD) converting function, and is applicable to a configuration in which a signal level is set to a digital signal.
- Hereinafter, a characteristic configuration corresponding to the stacking structure of a semiconductor layer in the
CMOS image sensor 100 according to the embodiment will be described in detail. - First, the basic concept of a characteristic configuration for adopting the stacking structure will be described.
- In the CMOS image sensor (solid-state imaging element) 100, basically, a plurality of stacked semiconductor layers is electrically connected to one another with a plurality of stack-connecting terminals (stack-connecting part).
- The
photoelectric conversion unit 111 andunit pixel cells 110A having signal output parts are two-dimensionally arrayed on a first semiconductor layer. - The signal output parts of a pixel group including a plurality of pixel cells share the
output signal line 116 wired from the stack-connecting terminal. - In addition, the
output signal line 116 has a separation part which can separate eachoutput signal line 116 that is arbitrarily branched in all or some of the locations branched from the stack-connecting terminal. - More specifically, an output of the amplifying
circuit 117 that includes a plurality of amplifying transistors is connected to the stack-connecting terminal, and some or all of branch points between stack-connecting terminals and the amplifyingcircuits 117 have a separation part which separates theoutput signal line 116. - The CMOS image sensor (solid-state imaging element) 100 has a light-irradiated face, for example, at the opposite side of the face where transistors and wires are arranged.
- In the
CMOS image sensor 100, when an output signal is propagated to the first semiconductor layer and a different semiconductor layer that are stacked through stack-connecting terminals, the degree of freedom for arranging the stack-connecting terminals rises, and transistors can be additionally arranged within a pixel array in small numbers without downscaling the photoelectric conversion unit. - By making use of the above advantage, it is possible to reduce the actual load capacity when reading signals of pixels through the amplifying
circuit 117, with a separation part such as a switch for separating each branch wiring at a node at which wiring from a stack-connecting terminal to each unit pixel is branched. - In the embodiment, a stack-connecting terminal is characteristic in that the terminal is arranged in the vicinity of the center of the pixel group connected thereto.
- Furthermore, the stack-connecting terminal can evenly divide parasitic capacitance of each wiring separated at a separation part by being arranged in the vicinity of the center of the pixel group connected thereto in the range of intervals in which stack-connecting terminals can be satisfactorily arranged.
- Accordingly, it is possible to minimize the actual load capacity when reading signals of each pixel through the amplifying
circuit 117. - In the embodiment, the branch point is characteristic in that the branch point is arranged in the vicinity of the center of the pixel group which is connected after the branch point.
- Furthermore, the branch point can evenly divide parasitic capacitance of each wiring separated at the separation part by arranging the branch point in the vicinity of the center of the pixel group which is connected after the branch point.
- Accordingly, it is possible to minimize the actual load capacity when reading signals of each pixel through the amplifying
circuit 117. - In the embodiment, the separation part arranged in the branch point is characteristic in that an element same as the separation part is dummy-arranged in an area where a separation part is not arranged so as to have periodicity in arrangement.
- Accordingly, it is possible to have periodicity of the layout of pixels and circuits, to have uniform imaging characteristics and operation characteristics of transistors, and to avoid image deterioration such as fixed-pattern noise, or the like.
- In the embodiment, the pixel group that is two-dimensionally arrayed is connected to the same stack-connecting terminal.
- By connecting the two-dimensionally arrayed pixel group to the same stack-connecting terminal, not only in the row or column direction, it is possible to minimize the distance from a stack-connecting terminal to the furthest pixel even when the number of pixels connected to the stack-connecting terminal is the same.
- Accordingly, in the embodiment, it is possible to make voltage drops uniform in readout voltages by parasitic resistance for each pixel.
- As a general readout circuit of output signals of pixels, the amplifying
transistor 114 in a pixel, and the source follower circuit including a constant current source by the bias transistor connected to theoutput signal line 116 can be exemplified. - Since the parasitic capacitance of the
output signal line 116 is discharged with a constant current, particularly, capacitance components are dominant at a convergence time of output, it is possible to attain speed-up or low power consumption in proportion to the separation of the capacitance. - On the other hand, since what is dominant is capacitive discharge, not a time constant of the wiring, it is characteristic that the convergence time does not dominantly deteriorate by resistance components, and there is almost no overhead incurred by the addition of a switch as a separation part.
- On the other hand, uniformity is regarded as important in the resistance components of the
output signal line 116. An input voltage of a source follower circuit is output to a source terminal of the amplifyingtransistor 114. - For this reason, the output voltage in the stack-connecting terminal is offset by a product of wiring resistance from the amplifying
transistor 114 to the stack-connecting terminal as an output terminal and a constant current generated in the load MOS (bias transistor) that is the current source. - The offset voltage can be easily cancelled by a CDS unit such as a correlated double sampling, but if the voltage differs for each pixel, a sufficient margin is necessary for a voltage range that can be input to an analog signal processing circuit such as an analog and digital conversion circuit after the output terminal.
- In the embodiment, since a switch as a separation means in the branch point is added to each separated
output signal line 116, it is characteristic that uniformity of resistance components of theoutput signal line 116 is not impaired. - Next, specific configuration examples will be described.
-
FIG. 8 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts in a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a first embodiment of the technology. -
FIG. 9 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) ofFIG. 8 . - In the
CMOS image sensor 100A of the first embodiment,pixel cells 110A are arranged on afirst semiconductor layer 200 in an array shape. Row scanning circuits 121-1 and 121-2 are arranged on the both sides of thepixel array part 110, and pixel driving circuits 122-1 and 122-2 are arranged corresponding to rows of thepixel cells 110A. - In the first embodiment, an amplifying
circuit 117 of thepixel cell 110A shares theoutput signal lines 116 in the column direction and is connected to a stack-connectingterminal 118. - A
separation part 140 of theoutput signal line 116 is provided on a location where theoutput signal line 116 branches between the stack-connectingterminal 118 and the amplifyingcircuit 117 of each pixel cell. - In the
pixel array part 110 ofFIG. 8 , pixel cells are arranged in a 6×6 matrix shape. - In the first embodiment, it is preferable that the stack-connecting
terminal 118 may be arranged at the center of a pixel group of a plurality ofpixel cells 110A connected thereto in the range of a minimum interval between stack-connecting terminals that can be produced. - In this case, ideally, it is preferable that the stack-connecting
terminals 118 are positioned in between the formation locations of the third and fourth pixel cells in columns CL0 to CL5, that is, at the center of each column, in the pixel array ofFIG. 8 . - When center arrangement is not possible, it is preferable to arrange the stack-connecting terminals in the vicinity of the center within the range where the terminals can be arranged as shown in
FIG. 8 . - In
FIG. 8 , the stack-connectingterminals 118 are arranged in between the formation locations of the fourth and the fifth pixel cells, that is, in the vicinity of the center within the range where the terminals can be arranged, in the even columns CL0, CL2, and CL4. - The stack-connecting
terminals 118 are arranged in between the formation locations of the second and the third pixel cells, that is, in the vicinity of the center within the range where the terminals can be arranged, in the odd columns CL1, CL3, and CL5. - In the example of
FIGS. 8 and 9 , theseparation part 140 is arranged so as to be separated in the stacking direction and to overlap the stack-connectingterminal 118. - Furthermore,
FIG. 9 includes fourpixel cells 110A-1 to 110A-4 for simplification, and shows an example where the stack-connectingterminal 118 and theseparation part 140 are arranged substantially at the center of the pixel group. - As shown in
FIG. 9 , theseparation part 140 at the branch point includes aswitch 141, and separates theoutput signal line 116 into two output signal line 116-1 and 116-2. - The output signal line 116-1 is connected to the amplifying
circuits 117 of thepixel cells 110A-1 and 110A-2 and the output signal line 116-2 is connected to the amplifyingcircuits 117 of thepixel cells 110A-3 and 110A-4. - The
switch 141 that constitutes theseparation part 140 includes a pair of terminals a and b and a pair of terminals c and d. - The terminal a is connected to the stack-connecting
terminal 118 and the terminal b is connected to the one output signal line 116-1. - The terminal c is connected to the stack-connecting
terminal 118 and the terminal d is connected to the other output signal line 116-2. - With the
switch 141 of the above configuration, the terminals a and b and the terminals c and d are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing. - The
switch 141 can be realized with a sample circuit in which either or both a NMOS transistor and a PMOS transistor are connected thereto in parallel, or the like. - In the example of
FIG. 9 , a bias transistor (load MOS) 119 which functions as a constant current source of the source follower is formed on thesecond semiconductor layer 210. - The
bias transistor 119 has a function of inputting a bias voltage Vb to a gate so that a constant current flows from theoutput signal line 116. - The
bias transistor 119 may be arranged in thefirst semiconductor layer 200. -
FIG. 10 is a diagram showing an example of principal circuits of a CMOS image sensor (solid-state imaging element) according to a second embodiment. - A point that the CMOS image sensor 100B according to the second embodiment differs from the
CMOS image sensor 100A according to the first embodiment is that the number of branches of theoutput signal line 116 by aseparation part 140B is not two but more than that (herein, three branches). - In the CMOS image sensor 100B, the
output signal line 116 is branched into three output signal lines 116-1, 116-2, and 116-3. - In addition, the amplifying
circuits 117 of thepixel cells 110A-5 and 110A-6 are connected to the output signal line 116-3. - A
switch 141B includes a pair of terminals e and f in addition to the configuration ofFIG. 9 . - In addition, the terminal e is connected to the stack-connecting
terminal 118 and the terminal f is connected to the output signal line 116-3. - With the
switch 141B of the above configuration, the terminals a and b, the terminals c and d, and the terminals e and f are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing. -
FIG. 11 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts on a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a third embodiment of the technology. -
FIG. 12 is a diagram showing an example of principal circuits of the CMOS image sensor (solid-state imaging element) ofFIG. 11 . - The
CMOS image sensor 100C according to the third embodiment is configured to have pixel groups sharing the stack-connectingterminals 118, including pixels arranged perpendicular (the horizontal direction inFIG. 11 ) to the readout scanning direction of pixels (the vertical direction inFIG. 11 ). - In the example of
FIG. 11 , each of two columns of the zeroth and the first columns, the second and the third columns, and the fourth and the fifth columns shares one stack-connectingterminal 118. - In addition, an output line L141 which extends from the output of the separation part 140-1 that is arranged in the middle of the even-numbered column and an output line L142 wired so as to return to the even-numbered column side from the output of the separation part 140-2 in the odd-numbered column side are connected to the separation part 140-3 arranged at a first branch point.
- The separation parts 140-0 and 140-1 form a second branch point, and basically have the same configuration as in the first embodiment.
- A switch 141-3 constituting the separation part 140-3 at the first branch point includes a pair of terminals g and h, and a pair of terminals i and j.
- The terminal g is connected to the stack-connecting
terminal 118 and the terminal h is connected to the one output line L141. - The terminal i is connected to the stack-connecting
terminal 118 and the terminal j is connected to the other output line L142. - With the switch 141-3 of the above configuration, the terminals g and h and the terminals i and j are switched to a connection or non-connection state according to a switching signal SSW by a control system that is not shown in the drawing.
- In the third embodiment, the first separation part 140-3 is positioned at the first branch point that branches first from the stack-connecting
terminal 118 and the second separation parts 140-1 and 140-2 are positioned at the second branch point that branches after that. - A plurality of pixels included in the same pixel group is simultaneously selected by readout scanning, but any one of the pixels that is simultaneously selected is connected to the stack-connecting
terminal 118 by the first or the second separation part. - In the example of
FIG. 12 , the number of pixel cells connected to the stack-connectingterminal 118 during reading of pixels is reduced to one fourth of a case where a separation part is not provided, whereby it is possible to speed-up and low power consumption by a decrease in parasitic capacitance. - In the example of
FIG. 12 , both the first and the second branch points have separation parts, but it does not matter that either of the branch points has a separation part. - For example, when only the first branch point is provided with a separation part, it is possible to reduce the total parasitic capacitance of the
output signal line 116 by half. - When a separation part is arranged only at the two second branch points, it is possible to reduce the number of connected pixel cells by one fourth by connecting any one of four switches arranged at the branch points.
- When parasitic capacitance of wiring from the first branch point to the second branch points is sufficiently smaller than the parasitic capacitance after the second branch points, substantially the same effect is obtained even when the separation part 140-3 at the first branch point is omitted.
- On the contrary, when parasitic capacitance of wiring from the first branch point to the second branch points is greater, it is preferable to have a separation part at the first branch point also.
-
FIG. 13 is a diagram showing an arrangement example of pixels, stack-connecting terminals, and separation parts on a first semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fourth embodiment of the technology. -
FIGS. 14A to 14D-3 are diagrams illustrating an arrangement example of the pixels, the stack-connecting terminals, and the separation parts in detail according to the fourth embodiment. - In a
pixel array part 110D ofFIG. 13 , pixel cells are arranged in a 6×6 matrix shape. - In addition,
FIG. 13 shows an arrangement example when a 4×4 pixel cell group GRP shares one stack-connectingterminal 11 as an example. - In order to minimize the length of wiring to the furthest pixel, it is preferable to arrange the stack-connecting
terminal 118 in the vicinity of the center of the 4×4 pixel cell group GRP. - Furthermore, it is preferable to arrange the first branch point at which the first separation part 140-3 is arranged in the vicinity of the center of the pixel cell group GRP, as shown in
FIG. 14A . - Furthermore, as shown in
FIG. 14B , the second separation parts 140-1 and 140-2 of the second branch point are arranged around of the center of each pixel cell group GRP separated by the first branch point. - In the same manner, as shown in
FIG. 14C , a third separation part 140-4 of a third branch point is arranged around the center of each pixel cell group GRP separated by the second branch points 140-1 and 140-2. - As a result, the configuration of the arrangement of the separation parts and the output
single lines 116 as shown inFIG. 14D is preferable to minimize wiring capacity or wiring resistance. - However, there is no strict limitation on the center arrangement due to the degree of complexity in the arrangement and wiring of transistors, but satisfactory effects are obtained if the separation parts are arranged in the vicinity of the center within a viable range.
- In addition, as shown in
FIG. 14D-2 , it is preferable to arrange a dummy transistor DMT as a dummy element at a location where separation means is not arranged in consideration of periodicity in the arrangement of the separation means. - By maintaining periodicity in the formation of transistors of each pixel cell, characteristics of light sensing elements and transistors are uniformed and the occurrence of fixed-pattern noise is suppressed.
- Furthermore, as shown in
FIG. 14D-3 , it does not matter that separation parts are omitted at some branch points, and replaced with the dummy transistor DMT. - In this example, the dummy transistors DMT are arranged instead of the second separation parts 140-1 and 140-2.
-
FIGS. 15A and 15B are diagrams showing an example in which elements are arranged so that switches of separation parts at branch points and dummy transistors hold periodicity. -
FIGS. 15A and 15B are circuit diagrams corresponding toFIG. 14D-3 , and the elements are arranged therein so that the switches of the separation parts at the branch points and the dummy transistors hold periodicity. - The dummy transistor DMT of
FIG. 15B is configured such that, as an example, the gates, the drains, and the sources of two NMOS transistors NT1 and NT2 which form the switch of the separation part and are cascade-connected to each other are grounded. -
FIG. 16 is a diagram showing an example in which the elements are arranged so that the switches of the separation parts at the branch points and the dummy transistors hold periodicity and the dummy transistors have a predetermined function. - As shown in
FIG. 16 , the dummy transistor DMT can be configured to have any function. - In the example of
FIG. 16 , the dummy transistor DMT is caused to function as a constant current source I1 of a source follower. - Specifically, the source of the NMOS transistor NT1 is grounded, the drain of the NMOS transistor NT2 is connected to the
output signal line 116, and the gates of both NMOS transistors NT1 and NT2 are connected to the power supply for the bias voltage Vb to constitute the constant current source I1. -
FIG. 17 is a diagram showing a layout example when a 4×4 pixel cells share the stack-connecting terminal. - When the 4×4 pixel cells share the stack-connecting
terminal 118, as shown inFIG. 17 , for example, it is possible to arrange theseparation part 140 in a gap between thepixel cells 110A. - Particularly, it is possible to arrange a separation part without reducing the area of a light sensing part in a rear surface irradiation type image sensor in which photoelectric conversion is performed by irradiating a surface opposite to a transistor-arranged surface with light, or an image sensor in which a photoelectric conversion film is formed upper than a wiring layer.
-
FIG. 18 is a diagram showing a stacking structure example of a first semiconductor layer and the second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a fifth embodiment of the technology. - In the
first semiconductor layer 200, awiring layer 202 is formed on a silicon (Si) substrate (p-well) 201. - An n-
type diffusion region 2011 is formed on theSi substrate 201 as a photoelectric conversion unit (PD) 111, and a p+type diffusion region 2012 is formed over the surface part of the photoelectric conversion unit 111 (the boundary between the wiring layer 202). -
n+ diffusion regions 2013 of FDs andn+ diffusion regions 2014 of the transistors for the switches of theseparation parts 140 are formed in plural over the surface part in theSi substrate 201. - In the
wiring layer 202, agate wiring 2021 and asignal propagation wiring 2022 of each transistor are formed in an insulating layer such as SiO2, and a micro-pad 2023 formed of Cu, or the like is formed over the surface part thereof. - In addition, a via (VIA) 2024 is formed in the
wiring layer 202 in order to connect an+ diffusion region 2014 of theseparation part 140 to themicro-pad 2023. - In the
second semiconductor layer 210, awiring layer 212 is formed on aSi substrate 211. -
Diffusion regions Si substrate 211. - In the
wiring layer 212, agate wiring 2121 and asignal propagation wiring 2122 of each transistor are formed in an insulating layer such as SiO2, and a micro-pad 2123 formed of Cu, or the like is formed over the surface part thereof. - In addition, a via (VIA) 2124 is formed in the
wiring layer 212 in order to connect adiffusion region 2111 and the like to amicro-pad 2123. - A CMOS image sensor (solid-state imaging element) 100E of
FIG. 18 is an image sensor in which thephotoelectric conversion unit 111 is formed on the semiconductor face opposite to the transistors and the wiring layers and the rear surface is irradiated with light, using a micro-bump BMP as the stack-connectingterminal 118. - In the
image sensor 100E, the surface part of thewiring layer 202 of thefirst semiconductor layer 200 and the surface part of thewiring layer 212 of thesecond semiconductor part 210 are opposed to each other to connect the micro-pad 2023 and the micro-pad 2123 with the micro-bump BMP. -
FIG. 19 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a sixth embodiment of the technology. - A point that an
image sensor 100F according to the sixth embodiment differs from theimage sensor 100E according to the fifth embodiment is that the micro-pad 2023 and the micro-pad 2123 as the uppermost wiring are connected to each other without using a micro-bump. -
FIG. 20 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a seventh embodiment of the technology. - Point that an
image sensor 100G according to the seventh embodiment differs from theimage sensor 100F according to the sixth embodiment are as follows. - In the
image sensor 100G, theSi substrate 211 of thesecond semiconductor layer 210 is arranged in the surface side of thewiring 202 of thefirst semiconductor layer 200. - In addition, the
micro-pad 2123 of thewiring layer 212 of thesecond semiconductor layer 210 is connected to themicro-pad 2023 of thewiring layer 202 of thefirst semiconductor layer 200 by a throughhole VIA electrode 213 that penetrates thesecond semiconductor layer 210. - Furthermore, the
wiring 2122 of thewiring layer 212 of thesecond semiconductor layer 210 is connected to thewiring 2022 of thewiring layer 202 of thefirst semiconductor layer 200 by a throughhole VIA electrode 214 that penetrates thesecond semiconductor layer 210. -
FIG. 21 is a diagram showing a stacking structure example of a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer of a CMOS image sensor (solid-state imaging element) according to an eighth embodiment of the technology. - The
CMOS image sensor 100H according to the eighth embodiment has a stacking structure of thefirst semiconductor layer 200, thesecond semiconductor layer 210, and a third semiconductor layer 230. - In the third semiconductor layer 230, a
wiring layer 222 is formed on aSi substrate 221. - On the
Si substrate 221,diffusion regions - In the
wiring layer 222, agate wiring 2221 and asignal propagation wiring 2222 of each transistor are formed in an insulating layer such as SiO2, and a micro-pad 2223 formed of Cu, or the like is formed over the surface part thereof. - In addition, a via (VIA) 2224 is formed in the
wiring layer 222 in order to connect thediffusion region 2211 and thewiring 2222 or thewiring 2222 and the micro-pad 2223. - In the
image sensor 100H, a photoelectric conversion film 240 is formed on thewiring layer 202 of thefirst semiconductor layer 200, and thewiring 2022 of thefirst semiconductor layer 200 and thewiring 2122 of thesecond semiconductor layer 210 are connected by a throughhole VIA 203 which penetrates thefirst semiconductor layer 200. - In addition, the
micro-pad 2123 of thewiring layer 212 of thesecond semiconductor layer 210 and themicro-pad 2223 of thewiring layer 222 of thethird semiconductor layer 220 are connected by a throughhole VIA electrode 213H which penetrates thesecond semiconductor layer 210. - Furthermore, as a photoelectric conversion film on the wiring layer, an organic photoelectric conversion film is well known. In addition, the semiconductor layer may be stacked with any number of layers.
- As such, if a photoelectric conversion layer is formed on a layer different from the transistors within the
first semiconductor layer 200, it is possible to arrange separation means and stack-connecting terminals with a high degree of freedom without reducing the area of light sensing elements. - In addition, it is possible to stack signal processing circuits or memory circuits as a semiconductor layer of the third semiconductor layer and to be connected by the stack-connecting
terminal 118. -
FIG. 22 is a diagram showing a stacking structure example of a first semiconductor layer and a second semiconductor layer of a CMOS image sensor (solid-state imaging element) according to a ninth embodiment of the technology. - In the
CMOS image sensor 100I according to the ninth embodiment, thefirst semiconductor layer 200 is formed in the same layout as inFIG. 13 , and thesecond semiconductor layer 210 is formed with anAD conversion unit 150 and asignal processing unit 160. - In the example of
FIG. 22 , onesignal processing unit 160 is arranged in the center part, and respective twoAD conversion units 150 are arranged in both sides of long edge parts. - In addition, in the
CMOS image sensor 100I,AD conversion circuits terminal 118. - Furthermore, if the pixel cells have amplifying circuits for signal output, a pixel sharing type in which a plurality of light sensing elements shares the amplifying circuits, a pixel configuration in which a charge holding region that realizes batch exposure is provided in a pixel, or the like is also acceptable.
- As described above, it is possible to obtain the following effects according to the technology.
- In an image sensor in which a connecting terminal that is connected to a stacked (three-dimensionally mounted) different semiconductor layer is shared in an amplifying circuit of a plurality of pixel cells, it is possible to reduce parasitic capacitance of an output signal line and realize speed-up and low power consumption of reading out of output signals from the pixels.
- In addition, since the above effect can be realized only with simple addition of switch circuits and wiring, almost no influence is given to the reduction of light sensing elements or deterioration in resolution in a rear surface irradiation image sensor or an image sensor using an organic photoelectric conversion film.
- By arranging a stack-connecting terminal and a separation part at a branch point in the vicinity of the center of a pixel group connected thereto, there are effects of speed-up and low power consumption by minimized parasitic capacitance and of reducing the range of an input voltage necessary for an analog signal processing circuit of the latter stage by uniform wiring resistance.
- A solid-state imaging element that brings the above effects can be applied as an imaging device of a digital camera or a video camera.
-
FIG. 23 is a diagram showing an example of a configuration of a camera system to which the solid-state imaging elements according to the embodiments of the technology are applied. - The
camera system 300 is provided with animaging device 310 to which one of the CMOS image sensors (solid-state imaging elements) 100 and 100A to 100I according to the embodiments is applicable, as shown inFIG. 23 . - Furthermore, the
camera system 300 includes an optical system that leads incident light to a pixel region of the imaging device 310 (forms the image of a subject), for example, alens 320 that forms an image on an imaging plane with the incident light (image light). - The
camera system 300 includes a driving circuit (DRV) 330 which drives theimaging device 310 and a signal processing circuit (PRC) 340 which processes output signals of theimaging device 310. - The driving
circuit 330 has a timing generator (not shown in the drawing) which generates various timing signals including start pulses and clock pulses that drive circuits in theimaging device 310 and drives theimaging device 310 with a predetermined time signal. - In addition, the
signal processing circuit 340 performs a predetermined signal process for output signals of theimaging device 310. - The image signals processed in the
signal processing circuit 340 are recorded on a recording medium, for example, a memory, or the like. Image information recorded on the recording medium is made into hard copy by a printer, or the like. In addition, the image signals processed in thesignal processing circuit 340 are displayed as moving images on a monitor including a liquid crystal display or the like. - As described above, it is possible to realize a camera with high precision and low power consumption by mounting the above-described
imaging elements imaging device 310. - The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-197734 filed in the Japan Patent Office on Sep. 3, 2010, the entire contents of which are hereby incorporated by reference.
- It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Claims (28)
1-22. (canceled)
23. An imaging device comprising:
a first substrate including:
a first plurality of pixels;
a first signal line coupled to the first plurality of pixels;
a second plurality of pixels;
a second signal line coupled to the second plurality of pixels;
a first wiring layer disposed at a side opposite to a light incident side of the first substrate;
a first transistor, wherein a first terminal of the first transistor is coupled to the first signal line and a second terminal of the first transistor is coupled to a ground;
a second transistor, wherein a first terminal of the second transistor is coupled to the second signal line and a second terminal of the second transistor is coupled to the ground; and
a first switch circuit coupled to the first signal line and the second signal line;
a second substrate including:
at least a portion of an A/D conversion unit; and
a second wiring layer; and
a via coupled to the first wiring layer and the second wiring layer, wherein
the first switch circuit is configured to selectively couple the first signal line and the second signal line to the via.
24. The imaging device according to claim 23 , wherein at least one pixel of the first plurality of pixels includes a plurality of photoelectric conversion elements, a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor.
25. The imaging device according to claim 23 , further comprising:
a second switch circuit coupled to a third signal line, wherein the second switch circuit is configured to selectively couple the third signal line to the via.
26. The imaging device according to claim 23 , wherein the first switch circuit includes a third switch circuit coupled to the first signal line and the via, and a fourth switch circuit coupled to the second signal line and the via.
27. The imaging device according to claim 23 , wherein the first wiring layer includes the first signal line and the second signal line.
28. An imaging device comprising:
a first substrate including:
a first plurality of pixels;
a first signal line coupled to the first plurality of pixels;
a second plurality of pixels;
a second signal line coupled to the second plurality of pixels;
a first wiring layer disposed at a side opposite to a light incident side of the first substrate; and
a first switch circuit coupled to the first signal line and the second signal line;
a second substrate including:
at least a portion of an A/D conversion unit; and
a second wiring layer; and
a via coupled to the first wiring layer and the second wiring layer, wherein
a first terminal of a first transistor is coupled to the first signal line and a second terminal of the first transistor is coupled to a ground, a first terminal of a second transistor is coupled to the second signal line and a second terminal of the second transistor is coupled to the ground, and the first switch circuit is configured to selectively couple the first signal line and the second signal line to the via.
29. The imaging device according to claim 28 , wherein at least one pixel of the first plurality of pixels includes a plurality of photoelectric conversion elements, a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor.
30. The imaging device according to claim 28 , further comprising:
a second switch circuit coupled to a third signal line, wherein the second switch circuit is configured to selectively couple the third signal line to the via.
31. The imaging device according to claim 28 , wherein the first switch circuit includes a third switch circuit coupled to the first signal line and the via, and a fourth switch circuit coupled to the second signal line and the via.
32. The imaging device according to claim 28 , wherein the first wiring layer includes the first signal line and the second signal line.
33. The imaging device according to claim 28 , wherein the first substrate includes the first transistor and the second transistor.
34. An imaging device comprising:
a first substrate including:
a first plurality of pixels;
a first signal line coupled to the first plurality of pixels;
a second plurality of pixels;
a second signal line coupled to the second plurality of pixels; and
a first switch circuit coupled to the first signal line and the second signal line;
a second substrate including:
at least a portion of an A/D conversion unit; and
a via configured to bond the first substrate to the second substrate, wherein
a first terminal of a first transistor is coupled to the first signal line and a second terminal of the first is transistor coupled to a ground, a first terminal of the second transistor is coupled to the second signal line and a second terminal of the second transistor is coupled to the ground, and the first switch circuit is configured to selectively couple the first signal line and the second signal line to the via.
35. The imaging device according to claim 34 , further comprising:
a second switch circuit coupled to a third signal line, wherein the second switch circuit is configured to selectively couple the third signal line to the via.
36. The imaging device according to claim 34 , wherein the first switch circuit includes a third switch circuit coupled to the first signal line and the via, and a fourth switch circuit coupled to the second signal line and the via.
37. The imaging device according to claim 34 , wherein the first substrate includes a first wiring layer, and the second substrate includes a second wiring layer.
38. The imaging device according to claim 37 , wherein the via is configured to bond the first wiring layer to the second wiring layer.
39. The imaging device according to claim 34 , wherein the first substrate includes the first transistor and the second transistor.
40. The imaging device according to claim 37 , wherein the first wiring layer includes the first signal line and the second signal line.
41. The imaging device according to claim 34 , wherein the first signal line is disposed adjacent to the second signal line.
42. An imaging device comprising:
a first substrate including:
a first plurality of pixels;
a first signal line coupled to the first plurality of pixels;
a second plurality of pixels;
a second signal line coupled to the second plurality of pixels;
a first switch circuit coupled to the first signal line and the second signal line;
a third plurality of pixels;
a third signal line coupled to the third plurality of pixels; and
a second switch circuit coupled to the third signal line;
a second substrate including:
at least a portion of an A/D conversion unit; and
a via configured to bond the first substrate to the second substrate, wherein
the first switch circuit is configured to selectively couple the first signal line and the second signal line to the via selectively, and wherein the second switch circuit is configured to selectively couple the third signal line to the via.
43. The imaging device according to claim 42 , wherein the first switch circuit includes a third switch circuit coupled to the first signal line and the via, and a fourth switch circuit coupled to the second signal line and the via.
44. The imaging device according to claim 42 , wherein the first substrate includes a first wiring layer, and the second substrate includes a second wiring layer.
45. The imaging device according to claim 44 , wherein the via is configured to bond the first wiring layer to the second wiring layer.
46. The imaging device according to claim 42 , wherein the first substrate includes the first transistor and the second transistor.
47. The imaging device according to claim 44 , wherein the first wiring layer includes the first signal line and the second signal line.
48. The imaging device according to claim 42 , wherein the first signal line is disposed adjacent to the second signal line.
49. The imaging device according to claim 48 , wherein the second signal line is disposed adjacent to the third signal line.
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Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5500007B2 (en) * | 2010-09-03 | 2014-05-21 | ソニー株式会社 | Solid-state imaging device and camera system |
US9257468B2 (en) | 2012-11-21 | 2016-02-09 | Olympus Corporation | Solid-state imaging device, imaging device, and signal reading medium that accumulates an amplified signal without digitization |
JP5820627B2 (en) | 2011-06-09 | 2015-11-24 | オリンパス株式会社 | Solid-state imaging device, imaging device, and signal readout method |
JP6083611B2 (en) * | 2011-08-30 | 2017-02-22 | パナソニックIpマネジメント株式会社 | Solid-state imaging device and imaging device |
JP5953028B2 (en) * | 2011-11-02 | 2016-07-13 | オリンパス株式会社 | Solid-state imaging device, imaging device, and signal readout method |
JP5973758B2 (en) * | 2012-03-22 | 2016-08-23 | オリンパス株式会社 | Solid-state imaging device |
CN109509761A (en) | 2012-03-30 | 2019-03-22 | 株式会社尼康 | Capturing element and focus detection device |
CN110177227B (en) | 2012-03-30 | 2022-04-05 | 株式会社尼康 | Imaging unit, imaging device, and imaging control program |
US9412725B2 (en) * | 2012-04-27 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
RU2018109081A (en) | 2012-05-02 | 2019-02-26 | Никон Корпорейшн | DEVICE FOR IMAGE FORMATION |
JP6119118B2 (en) * | 2012-06-07 | 2017-04-26 | 株式会社ニコン | Image sensor |
CN109089061B (en) | 2012-06-08 | 2022-01-21 | 株式会社尼康 | Imaging element and imaging device |
JP2014099582A (en) | 2012-10-18 | 2014-05-29 | Sony Corp | Solid-state imaging device |
JP6376245B2 (en) * | 2012-10-18 | 2018-08-22 | ソニー株式会社 | Solid-state imaging device and electronic device |
WO2014064837A1 (en) * | 2012-10-26 | 2014-05-01 | オリンパス株式会社 | Solid-state imaging device, imaging device, and signal reading method |
US8946784B2 (en) | 2013-02-18 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
JP5984018B2 (en) * | 2013-02-21 | 2016-09-06 | ソニー株式会社 | Solid-state imaging device and imaging apparatus |
JP6307791B2 (en) * | 2013-02-27 | 2018-04-11 | 株式会社ニコン | Semiconductor device |
CN111225161B (en) * | 2013-03-14 | 2023-04-18 | 株式会社尼康 | Image pickup element and image pickup apparatus |
US9318640B2 (en) | 2013-03-15 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
KR102075093B1 (en) * | 2013-08-14 | 2020-03-03 | 삼성전자주식회사 | Image sensor and analog to digital converter and analog to digital converting method tererof |
JP6141160B2 (en) * | 2013-09-25 | 2017-06-07 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging device and operation method thereof, electronic device and operation method thereof |
JP6547266B2 (en) * | 2013-10-01 | 2019-07-24 | 株式会社ニコン | Electronic device, control method of electronic device, and control program electronic device |
JP2015185823A (en) * | 2014-03-26 | 2015-10-22 | ソニー株式会社 | Solid state image sensor and imaging device |
JP2015186234A (en) * | 2014-03-26 | 2015-10-22 | ソニー株式会社 | Image sensor and electronic apparatus |
CN106664382B (en) * | 2014-07-15 | 2019-11-01 | 普里露尼库斯股份有限公司 | Solid-state image sensor, the manufacturing method of solid-state image sensor and e-machine |
WO2016120742A1 (en) | 2015-01-27 | 2016-08-04 | 株式会社半導体エネルギー研究所 | Occupant protection device |
CN107251545B (en) * | 2015-01-28 | 2020-03-03 | 松下知识产权经营株式会社 | Solid-state imaging device and camera |
US20160336370A1 (en) * | 2015-05-11 | 2016-11-17 | Sensors Unlimited, Inc. | Focal plane arrays with backside contacts |
JP6633850B2 (en) * | 2015-07-08 | 2020-01-22 | キヤノン株式会社 | Stacked solid-state imaging device |
JPWO2017038403A1 (en) * | 2015-09-01 | 2018-08-16 | ソニー株式会社 | Laminate |
EP3425902B1 (en) * | 2016-02-29 | 2023-10-25 | Nikon Corporation | Imaging element and imaging device |
US10998373B2 (en) * | 2016-07-11 | 2021-05-04 | Sony Semiconductor Solutions Corporation | Imaging element and imaging device |
CN111526267B (en) | 2016-08-03 | 2022-09-02 | 株式会社半导体能源研究所 | Image pickup device, image pickup module, electronic apparatus, and image pickup system |
JP2018037479A (en) * | 2016-08-30 | 2018-03-08 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging device and electronic apparatus |
US9955091B1 (en) * | 2016-12-20 | 2018-04-24 | Omnivision Technologies, Inc. | High dynamic range image sensor read out architecture using in-frame multi-bit exposure control |
US9961279B1 (en) | 2016-12-20 | 2018-05-01 | Omnivision Technologies, Inc. | Blooming free high dynamic range image sensor read out architecture using in-frame multi-bit exposure control |
WO2018193531A1 (en) * | 2017-04-19 | 2018-10-25 | オリンパス株式会社 | Endoscope, imaging module, and imaging module production method |
KR102552755B1 (en) * | 2017-06-02 | 2023-07-07 | 소니 세미컨덕터 솔루션즈 가부시키가이샤 | Solid-state imaging devices and electronic devices |
JP7038494B2 (en) | 2017-06-15 | 2022-03-18 | ルネサスエレクトロニクス株式会社 | Solid-state image sensor |
US10917589B2 (en) * | 2017-06-26 | 2021-02-09 | Facebook Technologies, Llc | Digital pixel with extended dynamic range |
US10686996B2 (en) | 2017-06-26 | 2020-06-16 | Facebook Technologies, Llc | Digital pixel with extended dynamic range |
US10825854B2 (en) * | 2017-08-16 | 2020-11-03 | Facebook Technologies, Llc | Stacked photo sensor assembly with pixel level interconnect |
US10598546B2 (en) | 2017-08-17 | 2020-03-24 | Facebook Technologies, Llc | Detecting high intensity light in photo sensor |
JP7102119B2 (en) | 2017-09-29 | 2022-07-19 | キヤノン株式会社 | Semiconductor devices and equipment |
JP6610648B2 (en) * | 2017-12-26 | 2019-11-27 | 株式会社ニコン | Imaging device |
WO2019130702A1 (en) * | 2017-12-27 | 2019-07-04 | ソニーセミコンダクタソリューションズ株式会社 | Image pickup device |
JP6602407B2 (en) * | 2018-01-11 | 2019-11-06 | キヤノン株式会社 | Solid-state imaging device and imaging system |
US11906353B2 (en) | 2018-06-11 | 2024-02-20 | Meta Platforms Technologies, Llc | Digital pixel with extended dynamic range |
US10897586B2 (en) | 2018-06-28 | 2021-01-19 | Facebook Technologies, Llc | Global shutter image sensor |
JP7178819B2 (en) * | 2018-07-18 | 2022-11-28 | 浜松ホトニクス株式会社 | Semiconductor photodetector |
JP7005459B2 (en) * | 2018-09-13 | 2022-01-21 | 株式会社東芝 | Solid-state image sensor |
TWI685199B (en) * | 2018-10-26 | 2020-02-11 | 瑞昱半導體股份有限公司 | Driving circuit |
JPWO2020090403A1 (en) * | 2018-10-30 | 2021-09-24 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state image sensor and image sensor |
US11037968B2 (en) * | 2019-04-05 | 2021-06-15 | Waymo Llc | Image sensor architecture |
US11943561B2 (en) | 2019-06-13 | 2024-03-26 | Meta Platforms Technologies, Llc | Non-linear quantization at pixel sensor |
CN113841244A (en) * | 2019-06-26 | 2021-12-24 | 索尼半导体解决方案公司 | Image pickup apparatus |
US11936998B1 (en) | 2019-10-17 | 2024-03-19 | Meta Platforms Technologies, Llc | Digital pixel sensor having extended dynamic range |
JPWO2021085025A1 (en) * | 2019-11-01 | 2021-05-06 | ||
JP2020074596A (en) * | 2020-01-23 | 2020-05-14 | 株式会社ニコン | Image pickup device |
US11902685B1 (en) | 2020-04-28 | 2024-02-13 | Meta Platforms Technologies, Llc | Pixel sensor having hierarchical memory |
JP7099560B2 (en) * | 2021-01-19 | 2022-07-12 | 株式会社ニコン | Image sensor and image sensor |
CN113363271B (en) * | 2021-05-31 | 2023-12-22 | 武汉新芯集成电路制造有限公司 | Photosensitive array and image forming apparatus |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4471228A (en) * | 1980-12-05 | 1984-09-11 | Fuji Photo Film Co., Ltd. | Solid-state image sensor with exposure controller |
US6822213B2 (en) * | 2000-11-27 | 2004-11-23 | Vision - Sciences Inc | Image sensors with improved signal to noise ratio |
US6989589B2 (en) * | 2003-07-21 | 2006-01-24 | Motorola, Inc. | Programmable sensor array |
US20060023109A1 (en) * | 2004-07-30 | 2006-02-02 | Sony Corporation | Semiconductor module, MOS type solid-state image pickup device, camera and manufacturing method of camera |
US20060243885A1 (en) * | 2005-04-05 | 2006-11-02 | Denso Corporation | Image sensor and control method of the image sensor |
US20080088014A1 (en) * | 2006-09-26 | 2008-04-17 | Adkisson James W | Stacked imager package |
US7394148B2 (en) * | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
US20090051801A1 (en) * | 2007-08-21 | 2009-02-26 | Sony Corporation | Image pickup apparatus |
US20090230287A1 (en) * | 2008-03-17 | 2009-09-17 | Anderson Todd J | Stacked image sensor with shared diffusion regions in respective dropped pixel positions of a pixel array |
US20100276572A1 (en) * | 2005-06-02 | 2010-11-04 | Sony Corporation | Semiconductor image sensor module and method of manufacturing the same |
US7859581B2 (en) * | 2003-07-15 | 2010-12-28 | Eastman Kodak Company | Image sensor with charge binning and dual channel readout |
US7868283B2 (en) * | 2006-08-21 | 2011-01-11 | Sony Corporation | Physical quantity detection device with pixel array column-aligned terminals and method of driving same |
US7964929B2 (en) * | 2007-08-23 | 2011-06-21 | Aptina Imaging Corporation | Method and apparatus providing imager pixels with shared pixel components |
US8274586B2 (en) * | 2008-06-17 | 2012-09-25 | Panasonic Corporation | Solid-state imaging device and method of manufacturing the same |
US20120307030A1 (en) * | 2011-05-12 | 2012-12-06 | Olive Medical Corporation | Image sensor for endoscopic use |
US8334491B2 (en) * | 2008-12-12 | 2012-12-18 | Cmosis Nv | Pixel array with shared readout circuitry |
US8344307B2 (en) * | 2009-04-27 | 2013-01-01 | Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg | Image sensor |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61120588A (en) * | 1984-11-16 | 1986-06-07 | Hitachi Ltd | Solid-state image pickup device |
JPH11164204A (en) * | 1997-11-25 | 1999-06-18 | Nikon Corp | Amplification type solid-state image pickup device |
JPH11252452A (en) * | 1998-02-26 | 1999-09-17 | Toshiba Tec Corp | Panoramic image-pickup device |
JP2000165747A (en) * | 1998-11-27 | 2000-06-16 | Sharp Corp | Radiographic equipment |
JP4303922B2 (en) * | 2002-07-29 | 2009-07-29 | 富士フイルム株式会社 | Solid-state imaging device and imaging apparatus |
WO2004019411A1 (en) * | 2002-08-09 | 2004-03-04 | Hamamatsu Photonics K.K. | Photodiode array, production method therefor, and radiation detector |
CN101228631A (en) * | 2005-06-02 | 2008-07-23 | 索尼株式会社 | Solid imaging element and manufacturing method thereof |
JP4887079B2 (en) * | 2006-06-06 | 2012-02-29 | 富士フイルム株式会社 | Photoelectric conversion film stack type solid-state imaging device |
US8049256B2 (en) * | 2006-10-05 | 2011-11-01 | Omnivision Technologies, Inc. | Active pixel sensor having a sensor wafer connected to a support circuit wafer |
JP2008177191A (en) * | 2007-01-16 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Solid imaging device and camera employing it |
JP4621270B2 (en) * | 2007-07-13 | 2011-01-26 | キヤノン株式会社 | Optical filter |
JP5223343B2 (en) * | 2008-01-10 | 2013-06-26 | 株式会社ニコン | Solid-state image sensor |
US7965329B2 (en) * | 2008-09-09 | 2011-06-21 | Omnivision Technologies, Inc. | High gain read circuit for 3D integrated pixel |
JP5262512B2 (en) * | 2008-09-25 | 2013-08-14 | ソニー株式会社 | Image sensor, control method therefor, and camera |
JP5500007B2 (en) * | 2010-09-03 | 2014-05-21 | ソニー株式会社 | Solid-state imaging device and camera system |
-
2010
- 2010-09-03 JP JP2010197734A patent/JP5500007B2/en active Active
-
2011
- 2011-07-19 TW TW100125523A patent/TWI469336B/en active
- 2011-08-03 CN CN201110220662.6A patent/CN102387324B/en active Active
- 2011-08-03 CN CN201610465465.3A patent/CN106129075B/en active Active
- 2011-08-03 KR KR1020110077205A patent/KR101872028B1/en active IP Right Grant
- 2011-08-26 US US13/218,979 patent/US9007503B2/en active Active
-
2015
- 2015-03-06 US US14/640,913 patent/US9197825B2/en active Active
- 2015-10-19 US US14/886,984 patent/US9615043B2/en active Active
-
2016
- 2016-10-27 US US15/335,778 patent/US9900482B2/en active Active
-
2017
- 2017-02-28 US US15/445,022 patent/US10129444B2/en active Active
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4471228A (en) * | 1980-12-05 | 1984-09-11 | Fuji Photo Film Co., Ltd. | Solid-state image sensor with exposure controller |
US6822213B2 (en) * | 2000-11-27 | 2004-11-23 | Vision - Sciences Inc | Image sensors with improved signal to noise ratio |
US7859581B2 (en) * | 2003-07-15 | 2010-12-28 | Eastman Kodak Company | Image sensor with charge binning and dual channel readout |
US6989589B2 (en) * | 2003-07-21 | 2006-01-24 | Motorola, Inc. | Programmable sensor array |
US20060023109A1 (en) * | 2004-07-30 | 2006-02-02 | Sony Corporation | Semiconductor module, MOS type solid-state image pickup device, camera and manufacturing method of camera |
US20060243885A1 (en) * | 2005-04-05 | 2006-11-02 | Denso Corporation | Image sensor and control method of the image sensor |
US20100276572A1 (en) * | 2005-06-02 | 2010-11-04 | Sony Corporation | Semiconductor image sensor module and method of manufacturing the same |
US7394148B2 (en) * | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
US7868283B2 (en) * | 2006-08-21 | 2011-01-11 | Sony Corporation | Physical quantity detection device with pixel array column-aligned terminals and method of driving same |
US20080088014A1 (en) * | 2006-09-26 | 2008-04-17 | Adkisson James W | Stacked imager package |
US20090051801A1 (en) * | 2007-08-21 | 2009-02-26 | Sony Corporation | Image pickup apparatus |
US7964929B2 (en) * | 2007-08-23 | 2011-06-21 | Aptina Imaging Corporation | Method and apparatus providing imager pixels with shared pixel components |
US20090230287A1 (en) * | 2008-03-17 | 2009-09-17 | Anderson Todd J | Stacked image sensor with shared diffusion regions in respective dropped pixel positions of a pixel array |
US8274586B2 (en) * | 2008-06-17 | 2012-09-25 | Panasonic Corporation | Solid-state imaging device and method of manufacturing the same |
US8334491B2 (en) * | 2008-12-12 | 2012-12-18 | Cmosis Nv | Pixel array with shared readout circuitry |
US8344307B2 (en) * | 2009-04-27 | 2013-01-01 | Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg | Image sensor |
US20120307030A1 (en) * | 2011-05-12 | 2012-12-06 | Olive Medical Corporation | Image sensor for endoscopic use |
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US20160044266A1 (en) | 2016-02-11 |
US20170171488A1 (en) | 2017-06-15 |
CN102387324B (en) | 2016-08-03 |
TW201220484A (en) | 2012-05-16 |
KR20120023547A (en) | 2012-03-13 |
JP5500007B2 (en) | 2014-05-21 |
JP2012054876A (en) | 2012-03-15 |
KR101872028B1 (en) | 2018-06-27 |
CN106129075B (en) | 2019-06-07 |
US20120057056A1 (en) | 2012-03-08 |
US10129444B2 (en) | 2018-11-13 |
US9197825B2 (en) | 2015-11-24 |
CN106129075A (en) | 2016-11-16 |
US20150181138A1 (en) | 2015-06-25 |
TWI469336B (en) | 2015-01-11 |
US9615043B2 (en) | 2017-04-04 |
CN102387324A (en) | 2012-03-21 |
US9900482B2 (en) | 2018-02-20 |
US9007503B2 (en) | 2015-04-14 |
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