US20170117214A1

US20170117214A1 - Semiconductor device with through-mold via

Info

Publication number: US20170117214A1
Application number: US15/390,568
Authority: US
Inventors: Dong Joo Park; Jin Seong Kim; Ki Wook Lee; Dae Byoung Kang; Ho Choi; Kwang Ho Kim; Jae Dong Kim; Yeon Soo JUNG; Sung Hwan Cho
Original assignee: Amkor Technology Inc
Current assignee: Amkor Technology Inc
Priority date: 2009-01-05
Filing date: 2016-12-26
Publication date: 2017-04-27
Also published as: US20180308788A1; US11869829B2; US20200343163A1; US10811341B2

Abstract

In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of co-pending U.S. patent application Ser. No. 12/348,813 filed on Jan. 5, 2009, which is expressly incorporated by reference herein.

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

Not Applicable

BACKGROUND

1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device having a thin profile and optimized electrical signal paths to provide enhanced electrical performance.
2. Description of the Related Art
The variety of electronic devices utilizing semiconductor devices or packages has grown dramatically in recent years. These electronic devices include cellular phones, portable computers, etc. Each of these electronic devices typically includes a printed circuit board on which a significant number of such semiconductor devices or packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. However, even though many semiconductor devices have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a continuing need to develop semiconductor device designs (e.g., semiconductor devices which are of increasingly reduced thickness) to maximize the number of semiconductor devices that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor devices. The need also exists for new semiconductor device designs to possess increased functionality, despite the smaller size of slimmer/thinner profiles thereof.
One method to minimize the space needed to accommodate semiconductor devices is to stack plural semiconductor dies in a single semiconductor device which is itself fabricated to be of a reduced size. However, semiconductor devices including stacked plural semiconductor dies are typically connected to an external circuit board through the use of solder balls or lands disposed solely on a lower external surface thereof. In this regard, when the size of the semiconductor device itself is reduced, the available space for input/output terminals (e.g., lands) is restricted. As a result, when the size of the semiconductor device is reduced, it is often difficult to realize various functions thereof due the insufficient availability of input/output terminals. Stated another way, when plural semiconductor dies are stacked in a single semiconductor device, the need arises for an increased number of input/output terminals for inputting/outputting electrical signals to each semiconductor die, though the smaller size of the semiconductor device creates limits in the available space for increasing the number of input/output terminals. Thus, the problem that arises is that is often difficult to form the input/output terminals when the size of the semiconductor device is reduced. When the input/output terminals are formed using solder balls, this particular problem becomes even more severe due to the volume of solder balls.
In an effort to address the aforementioned problems, there has been developed POP (package on package) technology to stack a semiconductor device on another semiconductor device, and PIP (package in package) technology to install a semiconductor device in another semiconductor device. A typical PIP semiconductor device comprises various combinations of electronic components including passive devices, semiconductor dies, semiconductor packages, and/or other elements which are arranged in a horizontal direction, or stacked in a vertical direction on an underlying substrate. In many PIP devices, the substrate and the electronic components are interconnected to one another through the use of conductive wires alone or in combination with conductive bumps, with such electronic components thereafter being encapsulated by a suitable encapsulant material which hardens into a package body of the PIP device. However, the drawbacks of both POP and PIP technology is that it is difficult to secure and stack the input/output terminals through the use of either technology as a result of the input/output terminals of the semiconductor device typically being formed only on one surface (e.g., the lower surface) thereof. The present invention addresses these and other shortcomings of prior art POP and PIP devices, as will be described in more detail below.

BRIEF SUMMARY

In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:

FIG. 1 is a cross-sectional view of a semiconductor device constructed in accordance with a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of a semiconductor device constructed in accordance with a second embodiment of the present invention;

FIG. 3 is a cross-sectional view of a semiconductor device constructed in accordance with a third embodiment of the present invention;

FIG. 4 is a cross-sectional view of a semiconductor device constructed in accordance with a fourth embodiment of the present invention;

FIG. 5 is a cross-sectional view of a semiconductor device constructed in accordance with a fifth embodiment of the present invention;

FIG. 6 is a cross-sectional view of a semiconductor device constructed in accordance with a sixth embodiment of the present invention;

FIG. 7 is a cross-sectional view of a semiconductor device constructed in accordance with a seventh embodiment of the present invention;

FIG. 8 is a cross-sectional view of a semiconductor device constructed in accordance with an eighth embodiment of the present invention;

FIG. 9 is a cross-sectional view of a semiconductor device constructed in accordance with a ninth embodiment of the present invention;

FIG. 10 is a flow chart illustrating an exemplary fabrication method for the semiconductor device shown in FIG. 1;

FIGS. 11A, 11B, 11C, 11D, 11E, 11F, 11G, and 11H are views illustrating an exemplary fabrication method for the semiconductor package shown in FIG. 1;

FIG. 12 is a flow chart illustrating an exemplary fabrication method for the semiconductor device shown in FIG. 6; and

FIGS. 13A, 13B, 13C, 13D, 13E, 13F, 13G, and 13H are views illustrating an exemplary fabrication method for the semiconductor package shown in FIG. 6.

Common reference numerals are used throughout the drawings and detailed description to indicate like elements.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now to the drawings wherein the showings are for purposes of illustrating various embodiments of the present invention and not for purposes of limiting the same, FIG. 1 depicts in cross-section a semiconductor device 100 constructed in accordance with a first embodiment of the present invention. The semiconductor device 100 comprises a substrate 110 which preferably has a generally quadrangular configuration. The substrate 110 can be selected from common circuit boards (e.g., rigid circuit boards and flexible circuit boards) and equivalents thereof. In this regard, the present invention is not intended to be limited to any particular type of substrate 110. By way of example and not by way of limitation, the substrate 110 may include an insulating layer 114 having opposed, generally planar top and bottom surfaces. Disposed on the top surface is an electrically conductive pattern 112, while disposed on the bottom surface are conductive lands 113. The conductive pattern 112 and lands 113 are electrically interconnected to each other in a prescribed pattern or arrangement through the use of conductive vias 111 which extend through the insulation layer 114 in a direction generally perpendicularly between the top and bottom surfaces thereof. A solder mask 115 is preferably coated on at least portions of the lands 113 and the bottom surface of the insulating layer 114. The solder mask 115 is used to protect portions of the lands 113 which would otherwise be exposed to the ambient environment.
The semiconductor device 100 further comprises a semiconductor die 120 which is electrically connected to the substrate 110, and in particular to the conductive pattern 112 thereof. The semiconductor die 120 defines opposed, generally planar top and bottom surfaces, and includes a plurality of terminals or bond pads 121 disposed on the top surface thereof. In FIG. 1, each of the bond pads 121 is depicted as projecting upwardly from the generally planar top surface of the semiconductor die 120. However, those of ordinary skill in the art will recognize that each of the bond pads 121 may be partially embedded within the semiconductor 120 so as to extend in substantially flush relation to the top surface thereof. The semiconductor die 120 further includes a plurality of through electrodes 122 formed therein and passing between the top and bottom surfaces thereof. As seen in FIG. 1, one end (the top end as viewed from the perspective shown in FIG. 1) of each electrode 122 is electrically coupled to a respective one of the bond pads 121, with the remaining end (the bottom end as viewed from the perspective shown in FIG. 1) extending to the bottom surface of the semiconductor die 120.
As further seen in FIG. 1, each of the electrodes 122 is electrically connected to the conductive pattern 112 of the substrate 110 through the use of respective ones of a plurality of conductive bumps 130. Examples of suitable material for the conductive bumps 130 include, but are not limited to, gold, silver, copper, soldering materials or equivalents thereto. As will be recognized by those of ordinary skill in the art, the conductive bumps 130, which are formed between the semiconductor die 120 and the substrate 110, effectively transmit electrical signals between the semiconductor die 120 and the substrate 110. Though not shown, it is contemplated that an underfill material may be disposed between the bottom surface of the semiconductor die 120 and the top surface of the insulating layer 114, the underfill material also covering portions of the conductive pattern 112 and the conductive bumps 130. The underfill material, if included, would serve to protect the semiconductor die 120 by absorbing stress according to differences between the thermal expansion coefficients of the substrate 110 and the semiconductor die 120. It is contemplated that the semiconductor die 120 may comprise a circuit that includes transistors, resistors and capacitors integrated on a silicon substrate.
The semiconductor device 100 further comprises a plurality of solder balls 160 which are electrically connected to the respective ones of the lands 113 of the substrate 110 in a prescribed pattern or arrangement. As seen in FIG. 1, the solder mask 115 extends into contact with the solder balls 160. Examples of suitable materials for the solder balls 160 include, but are not limited to, eutectic solders (e.g., Sn37Pb), high-lead solders (e.g., Sn95Pb) having a high melting point, lead-free solders (e.g., SnAg, SnCu, SnZn, SnZnBi, SnAgCu and SnAgBi), or equivalents thereto. As will be recognized, the solder balls 160 are used to electrically couple the substrate 110, and hence the semiconductor die 120, to an external circuit.
In the semiconductor device 100, at least portions of the semiconductor die 120, the conductive bumps 130, the top surface of the insulating layer 114, and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 140 of the semiconductor device 100. The present invention is not intended to be limited to any specific material which could be used to facilitate the fabrication of the package body 140. For example, and not by way of limitation, the package body 140 can be formed from epoxy molding compounds or equivalents thereto. The fully formed package body 140 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110.
In the semiconductor device 100, the package body 140 includes a plurality of through-mold vias 150 formed therein. Each through-mold via (TMV) 150 extends from the top surface of the package body 140 to a respective one of the bond pads 121 disposed on the top surface of the semiconductor die 120. Each TMV 150 is preferably formed by creating a hole in the package body 140 using a laser or an etching solution, and filling such hole with a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto. In this regard, it is contemplated that the fabrication of each TMV 150 may be facilitated by the completion of a reflow process subsequent to placing a ball fabricated from one of the aforementioned materials on top of the hole formed in the package body 140 through the use of one of the aforementioned processes.
As seen in FIG. 1, each TMV 150 has a generally conical configuration. More particularly, each TMV 150 is of a first diameter at a respective one of the bond pads 121, and a second diameter at the top surface of the package body 140, the second diameter exceeding the first diameter. As such, each TMV 150 defines a continuous side wall which is inclined at a predetermined angle relative to the top surface of the package body 140. As will be recognized by those of ordinary skill in the art, each TMV 150 creates an electrically conductive path from the semiconductor die 120 to the top surface of the package body 140, whereas the conductive bumps 130, substrate 110 and solder balls 160 collectively define an electrically conductive path which extends from the semiconductor die 120 in an opposite direction, such as toward an underlying substrate to which the semiconductor device 110 may ultimately be electrically connected through the use of the solder balls 160. Those of ordinary skill in the art will recognize that each TMV 150 may have a shape or configuration differing from that shown in FIG. 1 without departing from the spirit and scope of the present invention.
Due to the inclusion of the TMV's 150 therein, the semiconductor device 100 is particularly suited for having another semiconductor device stacked thereon and electrically connected thereto. In this regard, the lands or solder balls of a second semiconductor device can be electrically coupled to respective ones of the TMV's 150 exposed in the top surface of the package body 140. Along these lines, it is contemplated that the end of each TMV 150 extending to the top surface of the package body 140 have a generally concave configuration to partially accommodate the solder balls of a conventional BGA (Ball Grid Array) semiconductor device which may be stacked upon the semiconductor device 100, thus reducing the overall height or profile of the stack. Another semiconductor device suitable for stacking upon the semiconductor device 100 is an LGA (Land Grid Array) device, the stack comprising the semiconductor device 100 and the LGA device also being of comparatively reduced thickness due to the use of the TMV's 150 to facilitate the electrical interconnection therebetween.
Referring now to FIG. 10, there is provided a flow chart which sets forth an exemplary method for fabricating the semiconductor device 100 of the present invention shown in FIG. 1. The method comprises the steps of preparing the substrate (S1), preparing the semiconductor die (S2), forming conductive bumps on the semiconductor die (S3), attaching and electrically connecting the semiconductor die to the substrate (S4), encapsulation to form a package body (S5), forming TMV's in the package body (S6), and the connection of solder balls to the substrate (S7). FIGS. 11A-11H provide illustrations corresponding to these particular steps, as will be discussed in more detail below.
Referring now to FIG. 11A, in the initial step S1 of the fabrication process for the semiconductor device 100, the substrate 110 having the above-described structural attributes is provided. As indicated above, a solder mask 115 may be coated on at least portions of the lands 113 and the bottom surface of the insulating layer 114.
In the next step S2 of the fabrication process for the semiconductor device 100, the semiconductor die 120 is prepared. More particularly, as shown in FIG. 11B, the semiconductor die 120 is formed to include the aforementioned bond pads 121 on the top surface thereof, and the through-electrodes 122 which pass through the semiconductor die 120 between the top and bottom surfaces thereof, the electrodes 122 being electrically coupled to respective ones of the bond pads 121 as indicated above. Thereafter, as illustrated in FIG. 11C, step S3 is completed wherein the conductive bumps 130 are electrically connected to those ends of the through electrodes 122 opposite those ends electrically coupled to the bond pads 121. Thus, the electrodes 122 effectively electrically couple the bond pads 121 to respective ones of the conductive bumps 130.
Referring now to FIG. 11D, in the next step S4 of the fabrication process for the semiconductor device 100, the semiconductor die 120 is electrically connected to the substrate 110. More particularly, the conductive bumps 130 electrically connected to the semiconductor die 120 as described above in relation to step S3 are each electrically connected to the conductive pattern 112 of the substrate 110. As also indicated above, an underfill material may be interposed between the semiconductor die 120 and the substrate 110, such underfill material thus covering or encapsulating at least portions of the conductive bumps 130.
Referring now to FIG. 11E, in the next step S5 of the fabrication process for the semiconductor device 100, at least portions of the semiconductor die 120, the conductive bumps 130, the conductive pattern 112 and the top surface of the insulating layer 114 are each encapsulated or covered by an encapsulant material which ultimately hardens into the package body 140 of the semiconductor device 100. As indicated above, the fully formed package body 140 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110. The encapsulation step S5 can be carried out by transfer molding using a mold or dispensing molding using a dispenser.
In the next step S6 of the fabrication process for the semiconductor device 100, the TMV's 150 are formed in the package body 140. More particularly, the formation of the TMV's 150 comprises the initial step of forming vias or holes 140 a in the package body 140 as shown in FIG. 11F. Each of the holes 140 a extends from the top surface of the package body 140 to a respective one of the bond pads 121. As indicated above, the holes 140 a may be formed through the use of a laser drilling or chemical etching process. After being formed in the package body 140 in the aforementioned manner, each of the holes 140 a is filled with a conductive metal material as shown in FIG. 11G, thus completing the formation of the TMV's 150. As also indicated above, the filling of each hole 140 a with the metal material may be accomplished through the completion of a reflow process subsequent to the placement of a ball fabricated from a suitable conductive metal material upon that end of each hole 140 extending to the top surface of the package body 140.
Referring now to FIG. 11H, in the next step S7 of the fabrication process for the semiconductor device 100, the solder balls 160 are electrically connected to respective ones of the lands 113 of the substrate 110. As seen in FIG. 11H, the solder mask 115 may extend into contact with the solder balls 160. The solder balls 160 may be fabricated from the materials described above in relation thereto.
Referring now to FIG. 2, there is shown a semiconductor device 200 constructed in accordance with a second embodiment of the present invention. The semiconductor device 200 is substantially similar to the above-described semiconductor device 100, with only the differences between the semiconductor devices 200, 100 being described below.
The sole distinction between the semiconductor devices 100, 200 lies in the addition of through-mold vias (TMV's) 250 to the package body 140 of the semiconductor device 200. As seen in FIG. 2, each of the TMV's 250 extends from the top surface of the package body 140 to a corresponding portion of the conductive pattern 112 of the substrate 110. Each TMV 250 is preferably fabricated using the same process described above in relation to each TMV 150. Advantageously, in the semiconductor device 200, the inclusion of the TMV's 250 increases the available number of input/output terminals of the semiconductor device 200 in comparison to the semiconductor device 100.
Referring now to FIG. 3, there is shown a semiconductor device 300 constructed in accordance with a third embodiment of the present invention. The semiconductor device 300 comprises the above-described substrate 110. In addition to the substrate 110, the semiconductor device 300 comprises a first (upper) semiconductor die 320 which is attached to the top surface of the insulating layer 114 of the substrate 110 (as viewed from the perspective shown in FIG. 3) through the use of an adhesive layer 323. The first semiconductor die 320 defines opposed, generally planar top and bottom surfaces, and includes a plurality of terminals or bond pads 321 disposed on the top surface thereof. In this regard, the bottom surface of the first semiconductor die 320 is that surface which is attached to the substrate 110 through the use of the adhesive layer 323. In the semiconductor device 300, the bond pads 321 of the first semiconductor die 320 are electrically connected to the conductive pattern 112 of the substrate 110 through the use of a plurality of conductive wires 330. Each conductive wire 330 may be formed by the completion of a normal wire bonding method, that is, by forming a ball bond at the corresponding bond pad 321 of the first semiconductor die 320, and then forming a stitch bonding region at a prescribed portion of the conductive pattern 112 of the substrate 110. Alternatively, each conductive wire 330 may be formed by a reverse loop wire bonding method, that is, by forming a ball bond at the corresponding bond pad 321 and corresponding portion of the conductive pattern 112, and then connecting such ball bonds to each other.
In addition to the first semiconductor die 320, the semiconductor device 300 includes a second (lower) semiconductor die 325 which is also electrically connected to the substrate 110, and in particular the lands 113 thereof. Like the first semiconductor die 320, the second semiconductor die 325 defines opposed, generally planar top and bottom surfaces, and includes a plurality of bond pads 326 on that surface which defines the top surface as viewed from the perspective shown in FIG. 3. In this regard, each of the bond pads 326 of the second semiconductor die 325 is electrically connected to a respective one of the lands 113 through the use of respective ones of a plurality of conductive bumps 331. The conductive bumps 331 are each preferably fabricated from the same material described above in relation to the conductive bumps 130 of the semiconductor device 100.
In the semiconductor device 300, at least portions of the first and second semiconductor dies 320, 325, the conductive wires 330, the conductive bumps 331, the top and bottom surfaces of the insulating layer 114, the conductive pattern 112, and the lands 113 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 340 of the semiconductor device 300. The package body 340 may be fabricated from the same material described above in relation to the package body 140 of the semiconductor device 100. As seen in FIG. 3, the fully formed package body 340 preferably includes a generally planar top surface when viewed from the perspective shown in FIG. 3, a generally planar bottom surface when viewed from the same perspective, and generally planar side surfaces which extend generally perpendicularly between the top and bottom surfaces in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110.
In the semiconductor device 300, the package body 340 includes a plurality of through-mold vias (TMV's) 350 disposed therein. As seen in FIG. 3, certain ones of the TMV's 350 extend from the top surface of the package body 340 to a corresponding portion of the conductive pattern 112 of the substrate 110. The remaining TMV's 350 extend from the bottom surface of the package body 340 to respective ones of the lands 113 of the substrate 110. Each TMV 350 is identically configured to the above-described TMV's 250 of the semiconductor device 200, and is preferably fabricated using the same process described above in relation to each TMV 150 of the semiconductor device 100. Along these lines, it is contemplated that the end of each TMV 350 extending to the top surface and/or the bottom surface of the package body 340 may have a generally concave configuration to partially accommodate solder balls of a conventional BGA semiconductor device which may be stacked on the top surface and/or the bottom surface of the semiconductor device 300. In this regard, the inclusion of the TMV's 350 in the semiconductor device 300 makes the semiconductor device 300 particularly suited for having one or more additional semiconductor devices stacked on the top and/or bottom surfaces thereof.
Referring now to FIG. 4, there is shown a semiconductor device 400 constructed in accordance with a fourth embodiment of the present invention. The semiconductor device 400 comprises the above-described substrate 110. Additionally, in the semiconductor device 400, the above-described solder balls 160 are formed on and electrically connected to respective ones of the lands 113 of the substrate 110. Further, the above-described solder mask 115 is preferably applied to the bottom surface of the insulating layer 114 of the substrate 110, the solder mask 115 being coated on at least portions of the lands 113 and extending into contact with portions of each of the solder balls 160.
In addition to the substrate 110, the semiconductor device 400 comprises a first (lower) semiconductor die 320 which is electrically connected to the conductive pattern 112 of the substrate 110. More particularly, the first semiconductor die 420 defines opposed, generally planar top and bottom surfaces, and includes a plurality of terminals or bond pads 421 disposed on the bottom surface thereof. Each of the bond pads 421 is electrically connected to the conductive pattern 112 through the use of a respective one of a plurality of conductive bumps 430. The conductive bumps 430 are each preferably fabricated from the same material described above in relation to the conductive bumps 130 of the semiconductor device 100.
The semiconductor device 400 further comprises an interposer 423 which is attached to the top surface of the first semiconductor die 420 through the use of an adhesive layer 415. The interposer 423 includes an interposer body 424 having a first conductive pattern 423 a formed within the top surface thereof, a second conductive pattern 423 b formed therein, and a third conductive pattern 423 c which is also formed therein and electrically connects the first and second conductive patterns 423 a, 423 b to each other. That surface of the body 424 disposed furthest from the first conductive pattern 423 a is secured to the top surface of the first semiconductor die 420 through the use of the aforementioned adhesive layer 413. As seen in FIG. 4, the first and second conductive patterns 423 a, 423 b are formed within the body 424 of the interposer 423 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 423 c is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second patterns 423 a, 423 b extend.
The semiconductor device 400 further comprises a second (upper) semiconductor die 425 which is electrically connected to the interposer 423, and in particular to the first conductive pattern 423 a formed on the body 424 thereof. Like the first semiconductor die 420, the second semiconductor die 425 defines opposed, generally planar top and bottom surfaces. Disposed on the bottom surface of the first semiconductor die 425 is a plurality of conductive terminals or bond pads 426. The bond pads 426 are each electrically connected to the first conductive pattern 423 a through the use of respective ones of a plurality of conductive bumps 431 which are each preferably fabricated from the same material used in relation to the conductive bumps 430. As seen in FIG. 4, the second and third conductive patterns 423 b, 423 c of the interposer 423 are configured to effectively route signals between a portion of the first conductive pattern 423 a to which the second semiconductor die 425 is electrically connected to another portion of the first conductive pattern 423 a which is located outwardly beyond the lateral side surfaces of the second semiconductor die 425. In this regard, when the interposer 423 is captured between the first and second semiconductor dies 420, 425 in the manner shown in FIG. 4, a peripheral portion of the interposer 423 protrudes beyond the lateral side surfaces of each of the first and second semiconductor dies 420, 425. Additionally, a portion of the first conductive pattern 423 a is exposed in the body 424 of such peripheral portion of the interposer 423.
In the semiconductor device 400, the interposer 423 (and hence the second semiconductor die 425) is electrically connected to the conductive pattern 112 of the substrate 110 through the use of one or more electrically conductive wires 432. More particularly, one end of each conductive wire 432 extends and is electrically connected to a portion of the first conductive pattern 423 a which is exposed in the peripheral portion of the substrate 423, and in particular the body 424 thereof. The remaining, opposite end of the conductive wire 432 is electrically connected to a prescribed portion of the conductive pattern 112 of the substrate 110. Thus, the second semiconductor die 425 is capable of receiving electrical signals from and outputting electrical signals to an external circuit via the interposer 423, conductive wire(s) 432, and substrate 110.
In the semiconductor device 400, at least portions of the first and second semiconductor dies 420, 425, the conductive bumps 430, 431, the interposer 423, the conductive wires 432, the insulating layer 114 of the substrate 110, and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 440 of the semiconductor device 100. The package body 440 may be fabricated from the same materials described above in relation to the package body 140 of the semiconductor device 100. The fully formed package body 440 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110.
In the semiconductor device 400, the package body 440 preferably includes a plurality of through-mold vias (TMV's) 450 formed therein. As seen in FIG. 4, each of the TMV's 450 extends from the top surface of the package body 440 to a corresponding portion of the conductive pattern 112 of the substrate 110. Each TMV 450 is identically configured to the above-described TMV's 250, 350, and is preferably fabricated using the same process described above in relation to each TMV 150.
Referring now to FIG. 5, there is shown a semiconductor device 500 constructed in accordance with a fifth embodiment of the present invention. The semiconductor device 500 comprises the above-described substrate 110. Additionally, in the semiconductor device 500, the above-described solder balls 160 are formed on and electrically connected to respective ones of the lands 113 of the substrate 110. Further, the above-described solder mask 115 is preferably applied to the bottom surface of the insulating layer 114 of the substrate 110, the solder mask 115 being coated on at least portions of the lands 113 and extending into contact with portions of each of the solder balls 160. The semiconductor device 500 also includes a first semiconductor die 120 which is identical to the above-described semiconductor 120 of the semiconductor device 100, and is electrically connected to the conductive pattern 112 of the substrate 110 through the use of the conductive bumps 130 in the same manner described above in relation to the semiconductor device 100. In addition to the first semiconductor die 120, also electrically connected to the conductive pattern 112 of the substrate 110 is a plurality of conductive balls 551. As seen in FIG. 5, the conductive balls 551 are electrically connected to a peripheral portion of the conductive pattern 112. Each of the conductive balls 551 is preferably fabricated from a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto.
The semiconductor device 500 further comprises an interposer 523 which is disposed on the top surface of the first semiconductor die 420 and electrically connected to the first semiconductor die 120. The interposer 523 includes an interposer body 524 having a first conductive pattern 523 a formed within the top surface thereof, a second conductive pattern 523 b formed therein, and a third conductive pattern 523 c which is also formed therein and electrically connects the first and second conductive patterns 523 a, 523 b to each other. As seen in FIG. 5, the first and second conductive patterns 523 a, 523 b are formed within the body 524 of the interposer 523 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 523 c is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second conductive patterns 523 a, 523 b extend. In the semiconductor device 500, the second conductive pattern 523 b of the interposer 523 is electrically connected to the bond pads 121 of the first semiconductor die 121. As is also seen in FIG. 5, the interposer 523 is sized relative to the first semiconductor die 120 such that the side surfaces of the body 524 extend in substantially co-planar relation to respective side surfaces of the first semiconductor die 120.
The semiconductor device 500 further comprises the second (upper) semiconductor die 425 described above in relation to the semiconductor device 400. In this regard, the second semiconductor die 425 is electrically connected to the interposer 523, and in particular to the first conductive pattern 523 a formed on the body 524 thereof. The bond pads 426 of the second semiconductor die 425 are each electrically connected to the first conductive pattern 523 a through the use of respective ones of the aforementioned conductive bumps 431. As seen in FIG. 5, the side surfaces of the body 524 of the interposer 523 also extend in substantially co-planar to respective side surfaces of the second semiconductor die 425. Thus, when the interposer 523 is captured between the first and second semiconductor dies 120, 425 in the manner shown in FIG. 5, the side surfaces of the body 524 of the interposer 523 extend in generally co-planar relation to respective ones of the lateral side surfaces of each of the first and second semiconductor dies 120, 425.
In the semiconductor device 500, at least portions of the first and second semiconductor dies 120, 425, the conductive bumps 130, 431, the interposer 523, the conductive balls 551, the insulating layer 114 of the substrate 110, and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 540 of the semiconductor device 500. The package body 540 may be fabricated from the same materials described above in relation to the package body 140 of the semiconductor device 100. The fully formed package body 540 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110.
In the semiconductor device 500, the package body 140 preferably includes a plurality of through-mold vias (TMV's) 550 formed therein. Each TMV 550 includes a first region which is defined by a respective one of the conductive balls 551 electrically connected to the conductive pattern 112 of the substrate 110. In addition to the first region, each TMV 550 includes a second region 552 which extends from the top surface of the package body 140 to a respective one of the conductive balls 551. The second region 552 of each TMV 550 is identically configured to the above-described TMV's 250, 350, 450, and is preferably fabricated using the same process described above in relation to each TMV 150. In this regard, the second region 552 of each TMV 550 is defined by a metal-filled hole which is formed in the package body 540 to extend from the top surface thereof to a corresponding conductive ball 551 (i.e., the first region of the same TMV 550). Thus, each TMV 550 (comprising the second region 552 and the first region or conductive ball 551) extends from the top surface of the package body 540 to (and in electrical communication with) the conductive pattern 112. Since the second regions 552 of the TMV's 550 extend to respective ones of the conductive balls 551 rather than to the conductive pattern 112, each second region 552 is of a shorter height in comparison to the TMV's 450 included in the semiconductor device 400, though being fabricated in the same manner as indicated above. Due to the shortened height of height of the second regions 552 of the TMV's 550, including the holes used to form the same, potential adverse effects on the first and second semiconductor dies 120, 425 attributable to the formation of the holes is reduced, thus improving the reliability of the semiconductor device 500.
Referring now to FIG. 6, there is shown a semiconductor device 600 constructed in accordance with a sixth embodiment of the present invention. The semiconductor device 600 comprises the above-described substrate 110. Additionally, in the semiconductor device 600, the above-described solder balls 160 are formed on and electrically connected to respective ones of the lands 113 of the substrate 110. Further, the above-described solder mask 115 is preferably applied to the bottom surface of the insulating layer 114 of the substrate 110, the solder mask 115 being coated on at least portions of the lands 113 and extending into contact with portions of each of the solder balls 160. The semiconductor device 600 also includes a semiconductor die 420 which is identical to the above-described semiconductor 420 of the semiconductor device 400, and is electrically connected to the conductive pattern 112 of the substrate 110 through the use of the conductive bumps 430 in the same manner described above in relation to the semiconductor device 400.
In the semiconductor device 600, at least portions of the semiconductor die 420, the conductive bumps 430, the insulating layer 114 of the substrate 110, and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 640 of the semiconductor device 600. The package body 640 may be fabricated from the same materials described above in relation to the package body 140 of the semiconductor device 100. The fully formed package body 640 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110. The generally planar top surface of the semiconductor die 420 is preferably exposed in and substantially flush with the top surface of the package body 640.
In the semiconductor device 600, the package body 640 preferably includes a plurality of through-mold vias (TMV's) 650 formed therein. Each TMV 650 preferably comprises a conductive ball which is electrically connected to a peripheral portion of the conductive pattern 112. The conductive balls used to define the TMV's 650 are preferably fabricated from a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto. Importantly, in the semiconductor device 600, the package body 640 is formed in a manner wherein portions of the conductive balls used to form the TMV's 650 protrude from the top surface of the package body 640 in the manner shown in FIG. 6. Thus, the height of each TMV 650 slightly exceeds the height or thickness of the package body 640. It is also contemplated that the package body 640 may be fabricated by attaching a mold film to the substrate 110, such mold film partially covering the semiconductor die 420 and TMV's 650 in the aforementioned manner.
The semiconductor device 600 further comprises an interposer 623 which is disposed on and electrically connected to the TMV's 650. The interposer 623 includes an interposer body 624 having a first conductive pattern 623 a formed within the top surface thereof, a second conductive pattern 623 b formed therein, and a third conductive pattern 623 c which is also formed therein and electrically connects the first and second conductive patterns 623 a, 623 b to each other. As seen in FIG. 6, the first and second conductive patterns 623 a, 623 b are formed within the body 624 of the interposer 623 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 623 c is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second conductive patterns 623 a, 623 b extend. In the semiconductor device 600, the second conductive pattern 623 b of the interposer 623 is electrically connected to the exposed portions of the TMV's 650 in the manner shown in FIG. 6. Due to those portions of the TMV's 650 to which the interposer 623 is electrically connected protruding above the top surface of the package body 640, a narrow space or gap 615 is defined between the top surface of the package body 640 (as well as the top surface of the semiconductor die 420) and the interposer 623 (i.e., the bottom surface of the body 624). The formation of the gap 615 between the package body 640 and the interposer 623 enhances the ability of the semiconductor die 420 to dissipate heat outside of the semiconductor device 600.
Advantageously, the inclusion of the interposer 623 in the semiconductor device 600 allows a wiring pattern of the TMV's 650 to be selectively redistributed using the interposer 623. As is also seen in FIG. 6, the interposer 623 is sized relative to the package body 640 such that the side surfaces of the body 624 extend in substantially co-planar relation to respective side surfaces of the package body 640.
Referring now to FIG. 12, there is provided a flow chart which sets forth an exemplary method for fabricating the semiconductor device 600 of the present invention shown in FIG. 6. The method comprises the steps of preparing the substrate (S1), preparing the semiconductor die (S2), forming conductive bumps on the semiconductor die (S3), attaching and electrically connecting the semiconductor die to the substrate (S4), forming TMV's on the substrate (S5), encapsulation to form a package body (S6), attaching an interposer to the TMV's (S7), and the connection of solder balls to the substrate (S8). FIGS. 13A-13H provide illustrations corresponding to these particular steps, as will be discussed in more detail below.
Referring now to FIG. 13A, in the initial step S1 of the fabrication process for the semiconductor device 600, the substrate 110 having the above-described structural attributes is provided. As indicated above, a solder mask 115 may be coated on at least portions of the lands 113 and the bottom surface of the insulating layer 114.
In the next step S2 of the fabrication process for the semiconductor device 600, the semiconductor die 420 is prepared. More particularly, as shown in FIG. 13B, the semiconductor die 420 is formed to include the aforementioned bond pads 421 on the bottom surface thereof. As shown in FIG. 13B, the bond pads 421 are formed on the bottom surface of the semiconductor die 420 so as to protrude therefrom. In this regard, those of ordinary skill in the art will recognize that the bond pads 421 may alternatively be formed so as to be at least partially embedded in the semiconductor die 420 and to extend in substantially flush relation to the bottom surface thereof. Thereafter, as illustrated in FIG. 13C, step S3 is completed wherein the conductive bumps 430 are electrically connected to respective ones of the bond pads 121.
Referring now to FIG. 13D, in the next step S4 of the fabrication process for the semiconductor device 600, the semiconductor die 420 is electrically connected to the substrate 110. More particularly, the conductive bumps 430 electrically connected to the semiconductor die 420 as described above in relation to step S3 are each electrically connected to the conductive pattern 112 of the substrate 110, and hence to the lands 113.
Referring now to FIG. 13E, in the next step S5 of the fabrication process for the semiconductor device 600, the TMV's 650 are formed on the substrate 110. More particularly, as explained above, the formation of the TMV's 650 is facilitated by forming the aforementioned conductive balls on respective peripheral portions of the conductive pattern 112 of the substrate 110. Thus, the TMV's 650 extend at least partially about the periphery of the semiconductor die 420 in the manner shown in FIG. 13E.
Referring now to FIG. 13F, in the next step S6 of the fabrication process for the semiconductor device 600, at least portions of the semiconductor die 420, the conductive bumps 430, the TMV's 650, the conductive pattern 112 and the top surface of the insulating layer 114 are each encapsulated or covered by an encapsulant material which ultimately hardens into the package body 640 of the semiconductor device 600. As indicated above, the fully formed package body 640 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110. As also indicated above, the package body 640 is formed such that the top surface of the semiconductor die 420 extends in substantially flush relation to the top surface of the package body, with the TMV's 650 protruding slightly beyond the top surface of the package body 640. The encapsulation step S6 can be carried out by transfer molding using a mold, dispensing molding using a dispenser, or through the use of the aforementioned mold film.
In the next step S7 of the fabrication process for the semiconductor device 600 shown in FIG. 13G, the interposer 623 is electrically connected to the TMV's 650. More particularly, the second conductive pattern 623 b of the interposer 623 is electrically connected to the exposed portions of the TMV's 650 such that the aforementioned gap 615 is defined between the bottom surface of the body 624 of the interposer 623 and the top surface of the package body 640.
Referring now to FIG. 13H, in the next step S8 of the fabrication process for the semiconductor device 600, the solder balls 160 are electrically connected to respective ones of the lands 113 of the substrate 110. As seen in FIG. 13H, the solder mask 115 may extend into contact with the solder balls 160. The solder balls 160 may be fabricated from the materials described above in relation thereto.
Referring now to FIG. 7, there is shown a semiconductor device 700 constructed in accordance with a seventh embodiment of the present invention. The semiconductor device 700 comprises the above-described substrate 110. Additionally, in the semiconductor device 700, the above-described solder balls 160 are formed on and electrically connected to respective ones of the lands 113 of the substrate 110. Further, the above-described solder mask 115 is preferably applied to the bottom surface of the insulating layer 114 of the substrate 110, the solder mask 115 being coated on at least portions of the lands 113 and extending into contact with portions of each of the solder balls 160. The semiconductor device 700 also includes a first (lower) semiconductor die 420 which is identical to the above-described semiconductor 420 of the semiconductor device 400, and is electrically connected to the conductive pattern 112 of the substrate 110 through the use of the conductive bumps 430 in the same manner described above in relation to the semiconductor device 400.
In the semiconductor device 700, a plurality of conductive balls (which ultimately define lower through-mold vias or TMV's 650 as described below) are electrically connected to a peripheral portion of the first conductive pattern 112. The conductive balls used to define the TMV's 650 are preferably fabricated from a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto.
The semiconductor device 700 further comprises a first (lower) interposer 723 which is disposed on and electrically connected to the conductive balls ultimately defining the TMV's 650. The first interposer 723 includes an interposer body 724 having a first conductive pattern 723 a formed within the top surface thereof, a second conductive pattern 723 b formed therein, and a third conductive pattern 723 c which is also formed therein and electrically connects the first and second conductive patterns 723 a, 723 b to each other. As seen in FIG. 7, the first and second conductive patterns 723 a, 723 b are formed within the body 724 of the first interposer 723 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 723 c is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second conductive patterns 723 a, 723 b extend. In the semiconductor device 700, the second conductive pattern 723 b of the first interposer 723 is electrically connected to the conductive balls ultimately defining the TMV's 650 in the manner shown in FIG. 7. Additionally, the first interposer 723, and in particular a central portion of the bottom surface of the body 724 thereof, is attached to the top surface of the first semiconductor die through the use of an adhesive layer 415.
The semiconductor device 700 also includes a second (upper) semiconductor die 425 which is identical to the above-described semiconductor 425 of the semiconductor device 400, and is electrically connected to a central portion of the first conductive pattern 723 a of the first interposer 723 through the use of the conductive bumps 431 in the same manner described above in relation to electrical connection of the second semiconductor die 425 of the semiconductor device 400 to the first conductive pattern 423 a of the interposer 423 thereof. In the semiconductor device 700, a plurality of conductive balls (which ultimately define upper through-mold vias or TMV's 750 as described below) are electrically connected to a peripheral portion of the first conductive pattern 723 a of the first interposer 723. The conductive balls used to define the TMV's 750 are also preferably fabricated from a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto.
In the semiconductor device 700, at least portions of the first and second semiconductor dies 420, 425, the first interposer 723, the conductive bumps 430, the conductive balls ultimately defining the TMV's 650, 750, the insulating layer 114 of the substrate 110, and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 740 of the semiconductor device 700. The package body 740 may be fabricated from the same materials described above in relation to the package body 140 of the semiconductor device 100. The fully formed package body 740 preferably includes a generally planar top surface, and generally planar side surfaces which extend in generally flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110. The generally planar top surface of the second semiconductor die 425 is preferably exposed in and substantially flush with the top surface of the package body 740.
In the semiconductor device 700, the TMVs 650 are defined by the encapsulation of the conductive balls electrically connected to and extending between the conductive pattern 112 of the substrate 110 and the second conductive pattern 723 b of the interposer 723. Similarly, the upper TMVs 750 are defined by the partial encapsulation of the conductive balls electrically connected to the first conductive pattern 723 a of the interposer 723 with the package body 740. Importantly, in the semiconductor device 700, the package body 740 is formed in a manner wherein portions of the conductive balls used to form the TMV's 750 protrude from the top surface of the package body 740 in the manner shown in FIG. 7. Thus, the height of each TMV 750 slightly exceeds the height or thickness of the package body 740. As indicated above, each TMV 650, 750 preferably comprises a respective one of the aforementioned conductive balls which are each electrically connected to a peripheral portion of the first interposer 723.
The semiconductor device 700 further comprises a second (upper) interposer 770 which is disposed on and electrically connected to the TMV's 750. The second interposer 770 includes an interposer body 774 having a first conductive pattern 771 formed within the top surface thereof, a second conductive pattern 772 formed therein, and a third conductive pattern 773 which is also formed therein and electrically connects the first and second conductive patterns 771, 772 to each other. As seen in FIG. 7, the first and second conductive patterns 771, 772 are formed within the body 774 of the second interposer 770 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 773 is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second conductive patterns 771, 772 extend. In the semiconductor device 700, the second conductive pattern 772 of the second interposer 770 is electrically connected to the exposed portions of the TMV's 750 in the manner shown in FIG. 7. Due to those portions of the TMV's 750 to which the second interposer 770 is electrically connected protruding above the top surface of the package body 740, a narrow space or gap 715 is defined between the top surface of the package body 740 (as well as the top surface of the second semiconductor die 425) and the second interposer 770 (i.e., the bottom surface of the body 774). The formation of the gap 715 between the package body 740 and the second interposer 770 enhances the ability of the second semiconductor die 425 to dissipate heat outside of the semiconductor device 700. Advantageously, the inclusion of the second interposer 770 in the semiconductor device 700 allows a wiring pattern of the TMV's 750 to be selectively redistributed using the interposer 770.
Referring now to FIG. 8, there is shown a semiconductor device 800 constructed in accordance with an eighth embodiment of the present invention. The semiconductor device 800 is substantially similar to the above-described semiconductor device 700, with only the differences between the semiconductor devices 800, 700 being described below.
One of the differences between the semiconductor devices 800, 700 lies in the omission of the above-described second interposer 770 in the semiconductor device 800. Additionally, in the semiconductor device 800, the package body 740 described above in relation to the semiconductor device 700 is substituted with the package body 840 which is formed to completely cover the top surface of the second semiconductor die 425. This is in contrast to the semiconductor device 700 wherein the top surface of the second semiconductor die 425 is exposed in the top surface of the package body 740.
Another distinction between the semiconductor devices 800, 700 lies in the substitution of the above-described TMV's 750 of the semiconductor device 700 with the TMV's 850 included in the semiconductor device 800. In this regard, each of the TMV's 850 bears substantial structural similarity to the TMV's 550 described above in relation to the semiconductor device 500. More particularly, as seen in FIG. 8, each TMV 850 includes a first region which is defined by a respective one of a plurality of conductive balls 851 which are each electrically connected to a peripheral portion of the first conductive pattern 723 a of the interposer 723. In addition to the first region, each TMV 850 includes a second region 852 which extends from the top surface of the package body 840 to a respective one of the conductive balls 851. The second region 852 of each TMV 850 is identically configured to the above-described TMV's 250, 350, 450, 550, and is preferably fabricated using the same process described above in relation to each TMV 150. In this regard, the second region 852 of each TMV 850 is defined by a metal-filled hole which is formed in the package body 840 to extend from the top surface thereof to a corresponding conductive ball 851 (i.e., the first region of the same TMV 850). Thus, each TMV 850 (comprising the second region 852 and the first region or conductive ball 851) extends from the top surface of the package body 840 to (and in electrical communication with) the first conductive pattern 723 a of the interposer 723.
Referring now to FIG. 9, there is shown a semiconductor device 900 constructed in accordance with a ninth embodiment of the present invention. The semiconductor device 900 comprises the above-described substrate 110. Additionally, in the semiconductor device 900, the above-described solder balls 160 are formed on and electrically connected to respective ones of the lands 113 of the substrate 110. Further, the above-described solder mask 115 is preferably applied to the bottom surface of the insulating layer 114 of the substrate 110, the solder mask 115 being coated on at least portions of the lands 113 and extending into contact with portions of each of the solder balls 160. The semiconductor device 900 also includes a first (lower) semiconductor die 420 which is identical to the above-described semiconductor 420 of the semiconductor device 400, and is electrically connected to the conductive pattern 112 of the substrate 110 through the use of the conductive bumps 430 in the same manner described above in relation to the semiconductor device 400.
The semiconductor device 900 further comprises a second (upper) semiconductor die 925. The second semiconductor die 925 defines opposed, generally planar top and bottom surfaces, and includes a plurality of conductive terminals or bond pads 926 disposed on the top surface thereof when viewed from the perspective shown in FIG. 9. The bottom surface of the second semiconductor die 925 is attached to the top surface of the first semiconductor die 420 through the use of an intervening adhesive layer 415. The first and second semiconductor dies 420, 925 are preferably sized relative to each other such that the side surfaces thereof extend in substantially flush relation to each other when the first and second semiconductor dies 420, 925 are attached to each other through the use of the adhesive layer 415. Formed on and electrically connected to each of the bond pads 926 is a respective one of a plurality of conductive bumps 931, each of which is preferably fabricated from the same material used to facilitate the fabrication of conductive bumps 430 used to electrically connect the first semiconductor die 420 to the conductive pattern 112 of the substrate 110.
In the semiconductor device 900, at least portions of the first and second semiconductor dies 420, 925, the conductive bumps 430, 931, the insulating layer 114 of the substrate 110 and the conductive pattern 112 are each encapsulated or covered by an encapsulant material which ultimately hardens into a package body 940 of the semiconductor device 900. The package body 940 may be fabricated from the same materials described above in relation to the package body 140 of the semiconductor device 100. The fully formed package body 940 preferably includes a generally planar top surface, and generally planar side surfaces which extend in substantially flush or co-planar relation to respective side surfaces of the insulating layer 114 of the substrate 110. As seen in FIG. 9, portions of each of the conductive bumps 931 preferably protrude from the top surface of the package body 940.
In the semiconductor device 900, the package body 940 preferably includes a plurality of through-mold vias (TMV's) 950 formed therein. Each TMV 950 preferably comprises a conductive ball which is electrically connected to a peripheral portion of the conductive pattern 112. The conductive balls used to define the TMV's 950 are preferably fabricated from a conductive material selected from copper, aluminum, gold, silver, tin, lead, bismuth, soldering materials or equivalents thereto. Importantly, in the semiconductor device 900, the package body 940 is formed in a manner wherein portions of the conductive balls used to form the TMV's 950 protrude from the top surface of the package body 940 in the manner shown in FIG. 9. Thus, the height of each TMV 950 slightly exceeds the height or thickness of the package body 940.
The semiconductor device 900 further comprises an interposer 970 which is disposed on and electrically connected to the conductive bumps 931 and the TMV's 950. The interposer 970 includes an interposer body 974 having a first conductive pattern 971 formed within the top surface thereof, a second conductive pattern 972 formed therein, and a third conductive pattern 973 which is also formed therein and electrically connects the first and second conductive patterns 971, 972 to each other. As seen in FIG. 9, the first and second conductive patterns 971, 972 are formed within the body 974 of the interposer 623 so as to extend along respective ones of a spaced, generally parallel pair of planes. On the other hand, the third conductive pattern 973 is formed in a direction which extends generally perpendicularly between the planes along which respective ones of the first and second conductive patterns 971, 972 extend. In the semiconductor device 900, the second conductive pattern 972 of the interposer 970 is electrically connected to the exposed portions of the conductive bumps 931 and the TMV's 950 in the manner shown in FIG. 9. However, no space or gap such as the aforementioned gaps 615, 715 is defined between the interposer 970 and the top surface of the package body 940. Rather, the interposer 970, and in particular the bottom surface of the body 974 thereof, is in direct contact with the top surface of the package body 940. Advantageously, the inclusion of the interposer 970 in the semiconductor device 900 allows a wiring pattern of the conductive bumps 931 and the TMV's 950 to be selectively redistributed using the interposer 970. As is also seen in FIG. 9, the interposer 970 is sized relative to the package body 940 such that the side surfaces of the body 974 extend in substantially co-planar relation to respective side surfaces of the package body 940.
This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.

Claims

1. A packaged semiconductor device structure comprising:

a first redistribution structure comprising:

a first insulative structure including at least one insulating layer, the first insulative structure having a first major surface and an opposing second major surface;

a first conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure, wherein the first conductive pattern comprises a first portion disposed proximate to a perimeter part of the first redistribution structure and a second portion disposed proximate to a central part of the first redistribution structure; and

a second conductive pattern disposed proximate to the second major surface of the first insulative structure and electrically coupled to the first conductive pattern, wherein at least a portion of the second conductive pattern is exposed to the outside of the first insulative structure;

a first semiconductor device electrically coupled to the second portion of the first conductive pattern with conductive bumps;

first conductive structures projecting outward from and electrically coupled to the first portion of the first conductive pattern;

a package body encapsulating the first semiconductor device, at least portions of the first redistribution structure, and parts of the first conductive structures, wherein portions of the first conductive structures distal to the first redistribution structure are exposed to the outside of the package body, and wherein the portions of the first conductive structures distal to the first redistribution structure reside on a plane that is elevated above at least a portion of the package body; and

a second redistribution structure electrically coupled to the portions of the first conductive structures distal to the first redistribution structure.

2. The structure of claim 1, wherein the first conductive structures comprise conductive vias.

3. The structure of claim 1, wherein the first conductive structures comprise conductive balls.

4. The structure of claim 1, wherein the first conductive structures comprise a combination of conductive balls and conductive vias.

5. The structure of claim 1, wherein the portions of the first conductive structures distal to the first redistribution structure provide a gap between the package body and the second redistribution structure.

6. The structure of claim 5, wherein a major surface of the first semiconductor device is exposed to the outside of the package body in the gap.

7. The structure of claim 1, wherein the second redistribution structure is configured to selectively redistribute a wiring pattern of the first conductive structures.

8. The structure of claim 1 further comprising:

a third conductive pattern disposed within the first insulative structure and electrically coupling the first conductive pattern to the second conductive pattern; and

second conductive structures projecting outward from and electrically coupled to the portion of the second conductive layer exposed to the outside of the first insulative structure.

9. The structure of claim 8 further comprising:

a substrate comprising a substrate conductive pattern; and

a second semiconductor device electrically coupled to a first portion of the substrate conductive pattern, wherein:

the second conductive structures are further electrically coupled to a second portion of the substrate conductive pattern; and

the package body further encapsulates the second semiconductor device, the second conductive structures, and at least portions of the substrate conductive pattern.

10. The structure of claim 9 further comprising an adhesive layer interposed between the first redistribution structure and the first semiconductor device.

11. The structure of claim 1, wherein the second redistribution structure comprises:

a second insulative structure including at least one insulating layer, the second insulative structure having a first major surface and an opposing second major surface;

a third conductive pattern disposed proximate to the first major surface of the second insulative structure and exposed to the outside of the second insulative structure and configured for receiving an electronic component;

a fourth conductive pattern disposed proximate to the second major surface of the second insulative structure, wherein at least a portion of the fourth conductive pattern is exposed to the outside of the second insulative structure, and wherein the fourth conductive pattern is electrically coupled to the first conductive structures; and

a fifth conductive pattern disposed within the second insulative structure and electrically coupling the third conductive pattern to the fourth conductive pattern.

12. A packaged semiconductor device structure comprising:

a first redistribution structure comprising:

a first conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure;

a second conductive pattern disposed proximate to the second major surface of the first insulative structure, wherein at least a portion of the second conductive pattern is exposed to the outside of the first insulative structure; and

a third conductive pattern disposed within the first insulative structure and electrically coupling the first conductive pattern to the second conductive pattern;

a first semiconductor device electrically coupled to the first conductive pattern;

a substrate comprising a substrate conductive pattern, wherein the second conductive pattern is electrically coupled to the substrate conductive pattern;

first conductive structures projecting outward from and electrically coupled to the substrate conductive pattern and laterally spaced apart from the first semiconductor device; and

a package body encapsulating the first redistribution structure, the first semiconductor device, and the first conductive structures, wherein portions of the first conductive structures distal to the substrate conductive pattern are exposed to the outside of the package body.

13. The structure of claim 12, wherein the first conductive structures each comprise:

a first region attached to the substrate conductive pattern; and

a second region different than the first region coupled to the first region, wherein the portions of the first conductive structures exposed to the outside of the package body are part of the second region, and wherein:

the portions of the first conductive structures distal to the substrate conductive pattern reside on a plane that is elevated above the first semiconductor device.

14. The structure of claim 13, wherein:

the first region comprises a conductive ball; and

the second region comprises a conductive via.

15. The structure of claim 12 further comprising a second semiconductor device having a plurality of conductive vias disposed extending through the second semiconductor device, wherein the plurality of conductive vias electrically couple the second conductive pattern of the first redistribution structure to the substrate conductive pattern, and wherein the package body completely encapsulates the first redistribution structure.

16. A packaged semiconductor device structure comprising:

a first substrate structure having a first major surface and an opposing second major surface, the first substrate structure comprising:

a first conductive pattern disposed proximate to the first major surface of the first substrate structure; and

a second conductive pattern disposed proximate to the second major surface of the first substrate structure and electrically coupled to the first conductive pattern;

a second substrate structure comprising:

a third conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure; and

a fourth conductive pattern disposed proximate to the second major surface of the first insulative structure and electrically coupled to the third conductive pattern, wherein at least a portion of the fourth conductive pattern is exposed to the outside of the first insulative structure;

a second semiconductor device electrically coupled to the third conductive pattern;

an adhesive layer interposed between the first semiconductor device and the second major surface of the second substrate structure;

first conductive structures extending upright from and electrically coupled to the first conductive pattern and electrically coupled to the fourth conductive pattern;

and

a package body encapsulating at least portions of the first semiconductor device and the first conductive structures.

17. The structure of claim 16 further comprising:

second conductive structures extending upright and electrically coupled to the third conductive pattern, wherein:

at least portions of the second semiconductor device, at least portions of the second substrate structure, and first portions of the second conductive structures are encapsulated by the package body; and

second portions of the second conductive structures are exposed to the outside of the package body; and

a third substrate structure electrically coupled to the second portions of the second conductive.

18. The structure of claim 17, wherein:

distal ends of the second portions of the second conductive structures reside on a plane that is elevated above the package body to provide a gap between the package body and the third substrate structure.

19. The structure of claim 16, wherein the first semiconductor device is electrically coupled to the first conductive pattern with conductive bumps.

20. The structure of claim 17, wherein the second substrate structure is completely encapsulated by the package body.