US20170179262A1 - Thin film transistor array panel and method of manufacturing the same - Google Patents
Thin film transistor array panel and method of manufacturing the same Download PDFInfo
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- US20170179262A1 US20170179262A1 US15/446,858 US201715446858A US2017179262A1 US 20170179262 A1 US20170179262 A1 US 20170179262A1 US 201715446858 A US201715446858 A US 201715446858A US 2017179262 A1 US2017179262 A1 US 2017179262A1
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- metal oxide
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R11/00—Arrangements for holding or mounting articles, not otherwise provided for
- B60R2011/0042—Arrangements for holding or mounting articles, not otherwise provided for characterised by mounting means
- B60R2011/0049—Arrangements for holding or mounting articles, not otherwise provided for characterised by mounting means for non integrated articles
- B60R2011/005—Connection with the vehicle part
- B60R2011/0057—Connection with the vehicle part using magnetic means
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R11/00—Arrangements for holding or mounting articles, not otherwise provided for
- B60R2011/0042—Arrangements for holding or mounting articles, not otherwise provided for characterised by mounting means
- B60R2011/0049—Arrangements for holding or mounting articles, not otherwise provided for characterised by mounting means for non integrated articles
- B60R2011/005—Connection with the vehicle part
- B60R2011/0059—Connection with the vehicle part using clips, clamps, straps or the like
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F7/00—Signs, name or number plates, letters, numerals, or symbols; Panels or boards
- G09F7/18—Means for attaching signs, plates, panels, or boards to a supporting structure
- G09F2007/1856—Means for attaching signs, plates, panels, or boards to a supporting structure characterised by the supporting structure
- G09F2007/1865—Means for attaching signs, plates, panels, or boards to a supporting structure characterised by the supporting structure on vehicles
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- Thin Film Transistor (AREA)
Abstract
A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
Description
- This application claims priority to and the benefit of Korean Patent Application No. 10-2015-0000226 filed in the Korean Intellectual Property Office on Jan. 2, 2015, the entire contents of which are incorporated herein by reference, and this application is filed pursuant to 35 U.S.C. §121 as a Divisional application of Applicants' Patent Application Ser. No. 14/841,559 filed in the U.S. Patent & Trademark Office on 31 Aug. 2015, and assigned to the assignee of the present invention. All benefits accruing under 35 U.S.C. §120 from the aforesaid present application Ser. No. 14/841,559 are also claimed.
- The present invention generally relates to a thin film transistor array panel and a method of manufacturing the same.
- Generally, display devices such as a liquid crystal display and an organic light emitting diode display include a plural pairs of field generating electrodes and an electro-optical active layer interposed therebetween. The liquid crystal display includes a liquid crystal layer as the electro-optical active layer and the organic light emitting diode display includes an organic emission layer as the electro-optical active layer.
- One of the pair of field generating electrodes is generally connected to a switching element to receive an electrical signal and the electro-optical active layer converts the electrical signal into an optical signal, thereby displaying an image.
- The display device uses a thin film transistor (TFT) which is a three terminal element as the switching device and includes signal lines, such as a gate line which transfers a scanning signal for controlling the thin film transistor and a data line for transferring a signal to be applied to a pixel electrode.
- Meanwhile, as an area of the display device is increased, an oxide semiconductor technology for realizing high speed driving has been researched and a method for reducing resistance of the signal line has been researched. In particular, to reduce the resistance of the signal line, a main wiring layer may be made of materials such as copper or copper alloy. In this case, porous metal oxide is formed between the main wiring layer and a passivation layer covering the main wiring layer and thus reliability of a device may be reduced.
- The above information disclosed in this Related Art section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
- The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same having advantages of preventing porous metal oxide from being formed between a main wiring layer and a passivation layer.
- An exemplary embodiment of the present invention provides a thin film transistor array panel including: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
- The thin film transistor array panel may further include: a diffusion metal layer disposed between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer.
- The source electrode and the drain electrode may include copper or copper alloy.
- The second material may include at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe.
- The thin film transistor array panel may further include: barrier layers disposed under the source electrode and the drain electrode, the barrier layer including metal oxide.
- The barrier layer may include one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), and aluminum-zinc oxide (AZO).
- The metal oxide layer may cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively.
- The passivation layer may contact the upper surface and the lateral wall of the metal oxide layer.
- The thin film transistor array panel may further include: barrier layers disposed under the source electrode and the drain electrode; and capping layers disposed over the source electrode and the drain electrode, the barrier layer and the capping layer including metal oxide.
- Lateral walls of the source electrode and the drain electrode, respectively, which are adjacent to a channel region of the semiconductor layer may be exposed and the exposed lateral wall of the source electrode and the exposed lateral wall of the drain electrode may be covered with the metal oxide layer.
- The semiconductor layer may include oxide semiconductor.
- The lateral wall of the semiconductor layer may be aligned like the lateral walls of the source electrode and the drain electrode, except for the channel region.
- Another embodiment of the present invention provides a method for manufacturing a thin film transistor array panel including: forming a gate electrode on a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer between the gate electrode and the semiconductor layer; forming a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; annealing the source electrode and the drain electrode; forming a metal oxide layer covering the source electrode and the drain electrode; and forming a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the annealing includes diffusing an alloyed material to surfaces of the source electrode and the drain electrode.
- The forming of the metal oxide layer may include performing nitrogen oxide plasma treating.
- In the annealing, the diffusion metal layer may be formed between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer and the diffusion metal layer may include the alloyed material in the source electrode and the drain electrode.
- The method may further include: prior to the forming of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer, wherein the barrier layer is formed to include the metal oxide.
- The metal oxide layer may be formed to cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively.
- The method may further include: prior to the forming of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer; and forming capping layers on the source electrode and the drain electrode, wherein the barrier layer and the capping layer are formed to include the metal oxide.
- The semiconductor layer may be formed to include oxide semiconductor.
- The forming of the semiconductor layer and the forming of the source electrode and the drain electrode may be simultaneously performed using one mask.
- According to an exemplary embodiment of the present invention, it is possible to improve the reliability by suppressing the materials forming the main wiring layer from being oxidized by forming the metal oxide layer between the main wiring layer and the passivation layer. Further, according to an exemplary embodiment of the present invention, it is possible to reduce the process costs by removing the capping layer which is formed on the main wiring layer.
- A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein:
-
FIG. 1 is a plan view illustrating a thin film transistor array panel according to an exemplary embodiment of the present invention. -
FIG. 2 is a cross-sectional view taken along the line II-II ofFIG. 1 . -
FIGS. 3 to 13 are cross-sectional views illustrating a method of manufacturing of a thin film transistor array panel according to the exemplary embodiment of the present invention. -
FIG. 14 is a cross-sectional view illustrating a liquid display device according to an exemplary embodiment of the present invention. -
FIG. 15 is a cross-sectional view taken along the line II-II ofFIG. 1 to represent the thin film transistor array panel according to the exemplary embodiment of the present invention. -
FIGS. 16 to 25 are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to the exemplary embodiment of the present invention. - Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the exemplary embodiments set forth herein but may be modified in many different forms. On the contrary, exemplary embodiments introduced herein are provided to make disclosed contents thorough and complete and sufficiently transfer the spirit of the present invention to those skilled in the art.
- In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Further, it will be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening them may also be present. Like reference numerals designate like elements throughout the specification.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like or similar reference numerals refer to like or similar elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers, patterns and/or sections, these elements, components, regions, layers, patterns and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer pattern or section from another region, layer, pattern or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Example embodiments are described herein with reference to cross sectional illustrations that are schematic illustrations of illustratively idealized example embodiments (and intermediate structures) of the inventive concept. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the inventive concept.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIG. 1 is a plan view illustrating a thin film transistor array panel according to an exemplary embodiment of the present invention.FIG. 2 is a cross-sectional view taken along the line II-II ofFIG. 1 . - Referring to
FIGS. 1 and 2 , a thin filmtransistor array panel 100 according to an exemplary embodiment of the present invention includes a plurality ofgate lines 121 which are formed on an insulatingsubstrate 110 made of transparent glass, plastic, or the like. - The gate lines 121 transfers gate signals and mainly extend in a horizontal direction. Each
gate line 121 includes a plurality ofgate electrodes 124 which protrude from the gate lines 121. - The
gate line 121 and thegate electrode 124 may have a double layer structure which is configured offirst layers second layers first layers second layers first layers second layers - The
first layers second layers gate line 121 andgate electrode 124 are formed in the double layer but is not limited thereto, and therefore thegate line 121 andgate electrode 124 may be formed in a single layer form or a triple layer form. - A
gate insulating layer 140 which is made of insulating materials such as silicon oxide or silicon nitride is disposed on thegate line 121. Thegate insulating layer 140 may include a first insulatinglayer 140 a and a second insulatinglayer 140 b. The first insulatinglayer 140 a may be made of silicon nitride (SiNx) having a thickness of approximately 4000 Å and the second insulating layer may be made of silicon oxide (SiOx) having a thickness of approximately 500 Å. According to another exemplary embodiment of the present invention, the first insulatinglayer 140 a may be made of silicon oxinitride (SiON) and the second insulatinglayer 140 b may be made of silicon oxide (SiOx). The exemplary embodiment of the present invention describes that thegate insulating layers gate insulating layers - A
semiconductor layer 151 is formed on thegate insulating layer 140. Thesemiconductor layer 151 may be made of amorphous silicon, crystalline silicon, or oxide semiconductor. Thesemiconductor layer 151 mainly extends in a vertical direction and includes a plurality projections (154) which extend toward thegate electrode 124. - When the
semiconductor layer 151 is made of the oxide semiconductor, thesemiconductor layer 151 includes at least one of zinc (Zn), indium (In), tin (Sn), gallium (Ga), and hafnium (Hf). In particular, according to the exemplary embodiment of the present invention, thesemiconductor layer 151 may be made of indium-gallium-zinc oxide. - A data wiring layer which includes a plurality of
data lines 171 and a plurality ofsource electrodes 173 and a plurality ofdrain electrodes 175 which are connected to thedata lines 171 is formed on thesemiconductor layer 151 and thegate insulating layer 140. - The data lines 171 transfer the data signals and mainly extend in a vertical direction to intersect the gate lines 121. The
source electrode 173 extends from thedata line 171 to overlap thegate electrode 124 and may have substantially an U-letter shape. However, a structure of thesource electrode 173 and thedrain electrode 175 may be modified. - The
drain electrode 175 is separated from thedata line 171 and extends upward from a center of the U-letter shape of thesource electrode 173. - The
data line 171, thesource electrode 173, and thedrain electrode 175 have a double layer structure of barrier layers 171 p, 173 p, and 175 p and main wiring layers 171 q, 173 q, and 175 q. The barrier layers 171 p, 173 p, and 175 p are made of metal oxide. In detail, the barrier layers 171 p, 173 p, and 175 p may be made of one of indium-zinc oxide, gallium-zinc oxide, and aluminum-zinc oxide. The barrier layers 171 p, 173 p, and 175 p serve a diffusion preventing layer which prevents materials such as copper from being diffused to thesemiconductor layer 151. - The main wiring layers 171 q, 173 q, and 175 q include a first material and a second material added thereto. For example, the first material may be copper and the second material may include at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe. The main wiring layers 171 q, 173 q, and 175 q may be made of copper alloy. The second material added to the first material may be equal to or less than approximately 20 at % of the entire content.
- A
diffusion metal layer 170 c is disposed on surfaces of the main wiring layers 171 q, 173 q, and 175 q. According to the exemplary embodiment of the present invention, thediffusion metal layer 170 c may have a shape enclosing the main wiring layers 171 q, 173 q, and 175 q. An material (second material) alloyed to the main wiring layers 171 q, 173 q, and 175 q by annealing is diffused, so that thediffusion metal layer 170 c may be formed. - According to the exemplary embodiment of the present invention, a
metal oxide layer 177 is formed along an exposed surface of thediffusion metal layer 170 c. Themetal oxide layer 177 may be formed by being oxidized in a state in which thediffusion metal layer 170 c is exposed to the outside. Thediffusion metal layer 170 c may be oxidized by nitrogen oxide plasma treatment. - According to the exemplary embodiment of the present invention, the
metal oxide layer 177 covers thesource electrode 173 and thedrain electrode 175 while directly contacting the metal layers which are disposed on the surfaces of thesource electrode 173 and thedrain electrode 175, in particular, covers exposed lateral wall portions A and B of thesource electrode 173 and thedrain electrode 175 and exposed upper surfaces of thesource electrode 173 and thedrain electrode 175. In this case, themetal oxide layer 177 may not be formed on a portion of thegate insulating layer 140 which does not overlap thesource electrode 173 and thedrain electrode 175 and on a channel region of thesemiconductor layer 151. - Hereinafter, the exposed lateral wall portion A of the
source electrode 173 and thedrain electrode 175 which are adjacent to the channel region of thesemiconductor layer 151 will be described in detail. - Referring to
FIG. 2 , theprojection 154 of thesemiconductor layer 151 is provided with a portion which is not covered with thedata line 171 and thedrain electrode 175 and is exposed between thesource electrode 173 and thedrain electrode 175. Thesemiconductor layer 151 may have substantially the same plane pattern as thedata line 171 and thedrain electrode 175, except for the exposed portion of theprojection 154. In other words, a lateral wall of thesemiconductor layer 151 may be aligned like a lateral wall of thedata line 171, a lateral wall of thesource electrode 173, and a lateral wall of thedrain electrode 175, except for the exposed portion of theprojection 154. - One
gate electrode 124, onesource electrode 173, and onedrain electrode 175 form one thin film transistor (TFT) along with theprojection 154 of thesemiconductor layer 151 and the channel region of the thin film transistor is formed at theprojection 154 between thesource electrode 173 and thedrain electrode 175. - The lateral walls of the
source electrode 173 and thedrain electrode 175 which are adjacent to the channel region are exposed, the exposed side portions A of thesource electrode 173 and thedrain electrode 175 are provided with thediffusion metal layer 170 c, and the exposed side portions A of thesource electrode 173 and thedrain electrode 175 are covered with themetal oxide layer 177. - When a subsequent process forming the passivation layer including silicon oxide in the state in which the lateral wall portions A of the
source electrode 173 and thedrain electrode 175 without thediffusion metal layer 170 c and themetal oxide layer 177 are exposed is performed or theprojection 154 of the semiconductor layer is annealed to have channel characteristics, materials such as copper included in the main wiring layers 171 q, 173 q, and 175 q form porous oxide, and thus characteristics of the thin film transistor may be reduced. According to the exemplary embodiment of the present invention, themetal oxide layer 177 formed by the oxidization of thediffusion metal layer 170 c and thediffusion metal layer 170 c may prevent the materials such as copper from being oxidized. - A
passivation layer 180 is formed on thesource electrode 173, thedrain electrode 175, and themetal oxide layer 177. Thepassivation layer 180 is made of inorganic insulating materials such as silicon nitride and silicon oxide, organic insulating materials, insulating materials having a low dielectric constant, and the like. - According to the exemplary embodiment of the present invention, the
passivation layer 180 may include alower passivation layer 180 a and anupper passivation layer 180 b. Thelower passivation layer 180 a may be made of silicon oxide and theupper passivation layer 180 b may be made of silicon nitride. According to the exemplary embodiment of the present invention, since thesemiconductor layer 151 includes oxide semiconductor, thelower passivation layer 180 a which is adjacent to thesemiconductor layer 151 may be made of silicon oxide. Thelower passivation layer 180 a is made of silicon nitride, characteristics of the thin film transistor do not appear well. - The
passivation layer 180 may contact a portion which is not covered withsource electrode 173 anddrain electrode 175 and is exposed between thesource electrode 173 and thedrain electrode 175. - The
passivation layer 180 is formed with a plurality of contact holes 185 through which one end of thedrain electrode 175 is exposed. - A plurality of
pixel electrodes 191 are formed on thepassivation layer 180. Thepixel electrode 191 is physically and electrically connected to the drain electrode through thecontact hole 185 and is applied with a data voltage from thedrain electrode 175. - The
pixel electrode 191 may be made of transparent conductive materials such as ITO or IZO. -
FIGS. 3 to 13 are cross-sectional views illustrating a method of manufacturing of a thin film transistor array panel according to the exemplary embodiment of the present invention.FIGS. 3 to 13 sequentially illustrate cross-sectional views taken along the cut line II-II ofFIG. 1 . - Referring to
FIG. 3 , at least one of molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), chromium alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, manganese (Mn), manganese alloy is staked on the insulatingsubstrate 110 made of transparent glass, plastic, or the like and one selected from aluminum-based metals such as aluminum (Al) and aluminum alloy, silver-based metals such as silver (Ag) and silver alloy, and copper-based metals such as copper (Cu) and copper alloy is stacked thereon to form the double layer and then pattern the double layer, thereby forming thegate line 121 including thegate electrode 124. For example, thelower layers upper layers - In detail, after the double layer is formed, a photo resist (not shown) is stacked and patterned and then the patterned photo resist (not shown) is used as a mask to etch the
lower layers upper layers lower layers upper layers - Referring to
FIG. 4 , thegate insulating layer 140, theoxide layer 150, themetal oxide layer 170 p, and themetal layer 170 q are stacked on thegate line 121 and thegate electrode 124. The first insulatinglayer 140 a including silicon nitride is deposited on thegate insulating layer 140 and then the second insulatinglayer 140 b including silicon oxide including silicon oxide may be deposited thereon. - The
oxide layer 150 may be formed to include at least one of zinc (Zn), indium (In), tin (Sn), gallium (Ga), and hafnium (Hf), themetal oxide layer 170 p may be formed to include one of indium-zinc oxide, gallium-zinc oxide, and aluminum-zinc oxide, and themetal layer 170 q may be formed to include copper alloy. The material included in copper may include at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe. - The photo resist is formed thereon and then is patterned to form a first photo resist
pattern 50. The first photo resistpattern 50 has a thickfirst region 50 a and a relatively thinnersecond region 50 b. A difference in thickness of the first photo resistpattern 50 may be formed by controlling an irradiated amount of light using the mask or using a reflow method. In the case of controlling the amount of light, a slit pattern, a lattice pattern, or a translucent layer may be formed. Thesecond region 50 b having a thin thickness corresponds to a position at which the channel region of the thin film transistor is formed. - Referring to
FIG. 5 , the first photo resistpattern 50 is used as the mask and an etchant which may etch themetal oxide layer 170 p and themetal layer 170 q together is used to etch themetal oxide layer 170 p and themetal layer 170 q. The etchant used herein may be the same as the etchant used at the time of etching thelower layers upper layers gate line 121. - As illustrated in
FIG. 5 , when themetal oxide layer 170 p and the metal layer 1706 q are etched, the sides of themetal oxide layer 170 p and themetal layer 170 q which are covered with the first photo resistpattern 50 are etched with the etchant, and as a result, as illustrated inFIG. 5 , a boundary line between afirst metal layer 170 p and asecond metal layer 170 r is disposed in regions A, B, and C in which the first photo resistpattern 50 is formed. - In this case, the etchant which etches the
metal oxide layer 170 p and themetal layer 170 q does not etch thegate insulating layer 140 and theoxide layer 150. - In addition, the first photo resist
pattern 50 uses the mask to etch theoxide layer 150. - Referring to
FIG. 6 , thesecond portion 50 b having a thin thickness inFIG. 5 is removed with an etch back. In this case, thefirst portion 50 a is etched together and thus a width and a height thereof are reduced, and as a result, thefirst portion 50 a becomes a second photo resist 51 ofFIG. 6 . The second photo resist 51 is formed in narrower regions A′, B′, and C′ narrower than the regions A, B, and C in which the first photo resist inFIG. 5 is formed. - Referring to
FIG. 7 , the second photo resist 51 is used as the mask and the etchant is used to etch themetal oxide layer 170 p and themetal layer 170 q. - In this case, the
metal oxide layer 170 p and themetal layer 170 q are separated from each other to form thedata lines source electrodes drain electrodes semiconductor layer 151 including theprojection 154 which forms the channel of the thin film transistor while the upper surface of theoxide layer 150 is exposed is formed. - As such, when the photo resists having different thicknesses are used, the semiconductor layers 151 and 154 having substantially the same plane pattern as the barrier layers 171 p, 173 p, and 175 p and the main wiring layers 171 q, 173 q, and 175 q of the
data line 171, thesource electrode 173, and thedrain electrode 175 are formed. In detail, the lateral walls of the semiconductor layers 151 and 154 are aligned to be substantially same as the lateral wall of thedata line 171, the lateral wall of thesource electrode 173, and the lateral wall of thedrain electrode 175, except the exposed portion between thedrain electrode 175 and thesource electrode 173. - Next, referring to
FIG. 8 , ashing is performed to remove the photo resist and then annealing may be performed to form the diffusion metal layer on the surfaces of thesource electrode 173 and thedrain electrode 175. - Referring to
FIG. 9 , the second material (alloyed material) included in thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring layer are diffused to an edge during the annealing. In this case, copper is mainly distributed at the centers of thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring layer and thediffusion metal layer 170 c including the second material is formed along the surfaces of thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring layer. - Referring to
FIG. 10 , the surface of thediffusion metal layer 170 c may be subjected to N2O (nitrous oxide) plasma treatment to improve characteristics of the thin film transistor. - Referring to
FIG. 11 , a portion of thediffusion metal layer 170 c which is disposed on the surfaces of thesource part 173 q of the main wiring layer and the drain part 715 q of the main wiring layer is oxidized and thus themetal oxide layer 177 is formed along the surfaces thereof. Themetal oxide layer 177 may be formed on the upper surface and the lateral wall of thediffusion metal layer 170 c. - Referring to
FIGS. 12 and 13 , thepassivation layer 180 is formed on themetal oxide layer 177, thegate insulating layer 140, and theprojection 154 of the semiconductor layer exposed between thesource electrode 173 and thedrain electrode 175. Thepassivation layer 180 forms thelower passivation layer 180 a including silicon oxide (SiOx) and theupper passivation layer 180 b including silicon nitride (SiNx) may be formed on thelower passivation layer 180 a. - The thin film transistor array panel as illustrated in
FIG. 2 may be formed by forming thecontact hole 185 through which a portion of thedrain electrode 175 is exposed by patterning thepassivation layer 180 and forming thepixel electrode 191 on thepassivation layer 180. In this case, thepixel electrode 191 is formed to be physically connected to thedrain electrode 175 through thecontact hole 185. -
FIG. 14 is a cross-sectional view illustrating a liquid display device according to an exemplary embodiment of the present invention. - Referring to
FIG. 14 , the thin filmtransistor array panel 100 and thecounter display panel 200 face each other and the liquid crystal layer 3 is disposed therebetween. - The
second substrate 210 is disposed at a position facing thefirst substrate 110. Thesecond substrate 210 may be the insulating substrate made of transparent glass, plastic, or the like. Thelight blocking member 220 is formed on the second insulatingsubstrate 210. Thelight blocking member 220 is called a black matrix and prevents light leakage. - A plurality of
color filters 230 are formed on thesecond substrate 210 and thelight blocking member 220. Thecolor filter 230 is mainly present in the region which is enclosed with thelight blocking member 220 and may vertically extend along a column of thepixel electrode 191. Eachcolor filter 230 may display one of primary colors such as three primary colors of red, green, and blue. However, thecolor filters - Although the case in which the
light blocking member 220 and thecolor filter 230 are formed on thecounter display panel 200 is described above, but at least one of thelight blocking member 220 and thecolor filter 230 may also be formed on the thin filmtransistor array panel 100. - The
overcoat 250 is formed on thecolor filter 230 and thelight blocking member 220. Theovercoat 250 may be made of an insulating material and prevents thecolor filter 230 from being exposed and provides a flat surface. Theovercoat 250 may be omitted. - A
common electrode 270 is formed on theovercoat 250. - The
pixel electrode 191 to which the data voltage is applied generates an electric field along with thecommon electrode 270 to which a common voltage is applied to determine an alignment of liquid crystal molecules 31 of the liquid crystal layer 3 between the two electrodes. Thepixel electrode 191 and thecommon electrode 270 form a capacitor and thus maintain an applied voltage even after the thin film transistor is turned off. - The
pixel electrode 191 may overlap a storage electrode line (not illustrated) to form a storage capacitor, and thus voltage maintaining capability of a liquid crystal capacitor may be strengthened. - The content of the exemplary embodiment described with reference to
FIG. 2 may be applied to the description of the thin filmtransistor array panel 100. - Although the case in which the thin film transistor array panel according to the exemplary embodiment of the present invention is applied to the liquid crystal display is described, the exemplary embodiment of the present invention may be widely applied to display devices which perform a switching operation using the organic light emitting diode display and other thin film transistors.
-
FIG. 15 is a cross-sectional view taken along the line II-II ofFIG. 1 to represent the thin film transistor array panel according to the exemplary embodiment of the present invention. - The exemplary embodiment of the present invention described with reference to
FIG. 15 is substantially the same as the exemplary embodiment described with reference toFIG. 2 . Hereinafter, portions different from the exemplary embodiment of the present invention ofFIG. 2 will be described. - Referring to
FIG. 15 , thedata line 171, thesource electrode 173, and thedrain electrode 175 further include cappinglayers metal oxide layer 177 may be formed at the exposed lateral wall portions of the main wiring layers 171, 173 q, and 175 r between the barrier layers 171 p, 173 p, and 175 p and the capping layers 171 r, 173 r, and 175 r. - Except for the difference from the foregoing description, the content described with reference to
FIG. 2 may be applied to all of the exemplary embodiments of the present invention. -
FIGS. 16 to 25 are cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to the exemplary embodiment of the present invention.FIGS. 16 to 25 sequentially illustrate cross-sectional views taken along the cut line II-II ofFIG. 1 . - Referring to
FIGS. 16 to 21 , the method for manufacturing a thin film transistor array panel according to the exemplary embodiment of the present invention is substantially the same as the exemplary embodiment of the present invention described with reference toFIGS. 4 to 9 . However, the method for manufacturing a thin film transistor array panel according to the exemplary embodiment of the present invention may additionally form themetal oxide layer 170 r on themetal layer 170 q as illustrated inFIG. 16 . In the subsequent process, themetal oxide layer 170 r is subjected to a patterning process along with themetal layer 170 q and themetal oxide layer 170 p which are formed thereunder to form the capping layers 171 r, 173 r, and 175 r on the main wiring layers 171 q, 173 q, and 175 q as illustrated inFIG. 19 . - Referring to
FIG. 20 , the ashing is performed to remove the photo resist and then the annealing may be performed to form the diffusion metal layer on the surfaces of thesource electrode 173 and thedrain electrode 175. - Referring to
FIG. 21 , the second material (alloyed material) included in thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring layer are diffused to an edge during the annealing. In this case, copper is mainly distributed at the centers of thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring layer and thediffusion metal layer 170 c including the second material is formed along the surfaces of thesource part 173 q of the main wiring layer and thedrain part 175 q of the main wiring surface. - Referring to
FIG. 22 , the surface of thediffusion metal layer 170 c may be subjected to N2 O (nitrous oxide) plasma treatment to improve characteristics of the thin film transistor. - Referring to
FIG. 23 , a portion of thediffusion metal layer 170 c which is disposed on the surfaces of thesource part 173 q of the main wiring layer and the drain part 715 q of the main wiring layer is oxidized and thus themetal oxide layer 177 is formed along the surfaces thereof. Themetal oxide layer 177 may be formed on the lateral wall of thediffusion metal layer 170 c. - Referring to
FIGS. 24 and 25 , thepassivation layer 180 is formed on themetal oxide layer 177, thegate insulating layer 140, the capping layers 171 r, 173 r, and 175 r, and theprojection 154 of the semiconductor layer exposed between thesource electrode 173 and thedrain electrode 175. Thepassivation layer 180 forms thelower passivation layer 180 a including silicon oxide (SiOx) and theupper passivation layer 180 b including silicon nitride (SiNx) may be formed on thelower passivation layer 180 a. - The thin film transistor array panel as illustrated in
FIG. 15 may be formed by forming thecontact hole 185 through which a portion of thedrain electrode 175 is exposed by patterning thepassivation layer 180 and forming thepixel electrode 191 on thepassivation layer 180. In this case, thepixel electrode 191 is formed to be physically connected to thedrain electrode 175 through thecontact hole 185. - While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (20)
1. A method for manufacturing a thin film transistor array panel,
disposing a gate electrode on a substrate;
disposing a semiconductor layer on the substrate;
disposing a gate insulating layer between the gate electrode and the semiconductor layer;
disposing a source electrode on the semiconductor layer and a drain electrode facing the source electrode;
forming a metal oxide layer covering the source electrode and the drain electrode;
disposing a diffusion metal layer between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer; and
forming a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer,
wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and
wherein metal included in the metal oxide layer is the same as the second material.
2. The method of claim 1 , further comprised of forming the metal oxide layer to contact lateral walls of the diffusion metal layer.
3. The method of claim 2 , further comprised of including copper or a copper alloy in the formation of the source electrode and the drain electrode.
4. The method of claim 3 , further comprised of including at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe in the second material.
5. The method of claim 4 , further comprised of disposing barrier layers under the source electrode and the drain electrode, the barrier layer including metal oxide.
6. The method of claim 5 , further comprised of including one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), and aluminum-zinc oxide (AZO) in the barrier layer.
7. The method of claim 1 , further comprised of forming the metal oxide layer to cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively.
8. The method of claim 7 , further comprised of forming the passivation layer to contact the upper surface and the lateral wall of the metal oxide layer.
9. The method of claim 1 , further comprising:
disposing barrier layers under the source electrode and the drain electrode; and
disposing capping layers over the source electrode and the drain electrode, the barrier layer and the capping layer including metal oxide.
10. The method of claim 9 , further comprised of:
disposing lateral walls of the source electrode and the drain electrode, respectively, which are adjacent to a channel region of the semiconductor layer to be exposed and, covering the exposed lateral wall of the source electrode and the exposed lateral wall of the drain electrode with the metal oxide layer.
11. The method of claim 1 , further comprised of including an oxide semiconductor in the semiconductor layer.
12. The method of claim 1 , further comprised of aligning the lateral wall of the semiconductor layer like the lateral walls of the source electrode and the drain electrode, except for the channel region.
13. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode on a substrate;
forming a semiconductor layer on the substrate;
forming a gate insulating layer between the gate electrode and the semiconductor layer;
forming a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode;
annealing the source electrode and the drain electrode;
forming a metal oxide layer covering the source electrode and the drain electrode; and
forming a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer,
wherein the annealing includes diffusing an alloyed material to surfaces of the source electrode and the drain electrode.
14. The method of claim 13 , subjecting the metal oxide layer to a treatment by nitrogen oxide when forming the metal oxide layer.
15. The method of claim 14 , wherein:
in the annealing, the diffusion metal layer is formed between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer, and the diffusion metal layer includes the alloyed material in the source electrode and the drain electrode.
16. The method of claim 15 , further comprised of prior to the forming of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer, wherein the barrier layer is formed to include the metal oxide.
17. The method of claim 16 , wherein:
the metal oxide layer is formed to cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively.
18. The method of claim 17 , further comprising:
prior to the formation of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer; and
forming capping layers on the source electrode and the drain electrode,
wherein the barrier layer and the capping layer are formed to include the metal oxide.
19. The method of claim 13 , wherein:
the semiconductor layer is formed to include an oxide semiconductor.
20. The method of claim 13 , wherein:
the forming of the semiconductor layer and the forming of the source electrode and the drain electrode are simultaneously performed using one mask.
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KR1020150000226A KR102281846B1 (en) | 2015-01-02 | 2015-01-02 | Thin film transistor array panel and method of manufacturing the same |
US14/841,559 US9627548B2 (en) | 2015-01-02 | 2015-08-31 | Thin film transistor array panel and method of manufacturing the same |
US15/446,858 US20170179262A1 (en) | 2015-01-02 | 2017-03-01 | Thin film transistor array panel and method of manufacturing the same |
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US20170194500A1 (en) * | 2015-07-14 | 2017-07-06 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Thin-Film Transistor and Method for Forming the Same |
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CN102646632B (en) * | 2012-03-08 | 2014-04-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
WO2017085595A1 (en) * | 2015-11-20 | 2017-05-26 | 株式会社半導体エネルギー研究所 | Semiconductor device, method for manufacturing semiconductor device or display device having semiconductor device |
CN106887436B (en) * | 2015-12-16 | 2019-10-25 | 鸿富锦精密工业(深圳)有限公司 | Thin-film transistor array base-plate and preparation method thereof |
KR102424445B1 (en) * | 2016-05-03 | 2022-07-22 | 삼성디스플레이 주식회사 | Thin film transistor array panel and manufacturing method thereof |
US10916430B2 (en) | 2016-07-25 | 2021-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US11522059B2 (en) * | 2018-02-20 | 2022-12-06 | Intel Corporation | Metallic sealants in transistor arrangements |
JP2020136505A (en) * | 2019-02-20 | 2020-08-31 | 株式会社Joled | Semiconductor device and display device |
CN110112212A (en) * | 2019-04-25 | 2019-08-09 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and array substrate |
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US9627548B2 (en) | 2017-04-18 |
US20160197192A1 (en) | 2016-07-07 |
KR102281846B1 (en) | 2021-07-26 |
KR20160083995A (en) | 2016-07-13 |
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