US3651480A - Program controlled data processing system - Google Patents
Program controlled data processing system Download PDFInfo
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- US3651480A US3651480A US685636A US3651480DA US3651480A US 3651480 A US3651480 A US 3651480A US 685636 A US685636 A US 685636A US 3651480D A US3651480D A US 3651480DA US 3651480 A US3651480 A US 3651480A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1654—Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54575—Software application
- H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
Abstract
A program controlled data processor system which employs functionally equivalent first and second control units on a mutually exclusive basis to control an input-output system. The processor system comprises a plurality of independent memory units and communication between the control means and the independent memory units is by way of communication paths which may be selectively associated with any of the memory units and with either of the control means. The processor arrangement includes means for insuring that the two control means simultaneously carry out identical work functions.
Description
United States Patent Downing et al.
[ Mar. 21, 1972 [54] PROGRAM CONTROLLED DATA PROCESSING SYSTEM [72] Inventors: Randall W. Downing; John S. Nowak, both of Wheaton; Frank F. Taylor, West Chicago; Werner Ulrich, Glen Ellyn, all of Ill.
[73] Assignee: Bell Telephone Laboratories, Incorporated,
New York, NY.
[22] Filed: Nov. 24, 1967 [2]] Appl. No.: 685,636
Related US. Application Data [62] Division ot'Ser. No. 334,875, Dec. 31, I963.
[52] [1.8. CI. ..340/l72.5 [5 1] Int. Cl. A ...G06i /16 [58] Field ofSearch ..340/l72.5; 235/157 [56] References Cited UNITED STATES PATENTS 3,303,474 2/1967 Moore et al. ...34O/l 72 5 3,253,262 5/1966 Wilenitz et al ..340ll72.5 3,25 l ,040 5/l966 Burkholder et al. ..340/ l 72,5 3,263,2l9 7/l 966 Brun et al. ..340/l 72.5
Primary ExaminerGareth D. Shaw Attorney-R1. Guenther and R. B. Ardis [57] ABSTRACT 55 Claims, 89 Drawing Figures UNI VE 9514A l I r/ewvx FRAME 1 l m. I mun 1r 501w m ,5, UM ggggg 1m 510041 0/502 0/574 126 001- l NETWORK FRAME l l zgyfi gf E 136 0451.5 Rat 1a L la? 1 au/vcroe l 1 1 m8 saw/c5 123 FRAME 27 l '92. CC 73 {63 U/VE saw i uwvcr saw .1 1 l L WSCELLANEW l NETW 00/1/17? I26 SIGNAL 0150? l NET/1r. cowm- TWA/K FRAME CABLE RCl R T CABLE RCl R I CABLERCl R l 133 mu/vx sen/v L V 7 13 My l 129 1132 5101x 41 0 5051 011045 RCV/i. 111 40 137 J my] 104 1/0 104 104 104 111145091? SCANNER PAIENTED m 2 1 m2 SHEET 01UF86 PATENTEDHARZI I972 3.651 .480
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Bus 0' 81137 CONV ROUTE REG 650/ (BUS 0 a BUS w CAL L 5mm; Bus
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PROGRAM INPUT E N PATH T3 450 E LL A" gg gr o v I i @755 I CONTROL I 700 50m} 1 I EMERGENCY ACTION EQ CONVERTER DECODER TIMING ACCESS CIRCUIT MEMORY I PATH 772% l v 312150710 OPERATIONAL CAW' }IL 0/1755 1 CHECK 705 706 BUS 0 us! PATENTEUHARZI I972 3.651.480
sum as or as FIG. 6
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Claims (55)
1. A program controlled data handling system comprising: a processor arrangement comprising a control arrangement, a plurality of independent memories containing sequences of program order words and data and a transmission arrangement for selectively interconnecting said memories and said control arrangement; and an input-output system connected to the processor arrangement and responsive to command signals therefrom; said control arrangement comprises two functionally equivalent control means, said transmission arrangement comprises a plurality of independent transmission buses for selectively connecting said control means and said memories to form two processor combinations, each processor combination comprising a selected one of said control means, selected ones of said memories and selected ones of said transmission buses; and said system further comprises circuits for assuring the concurrent performance of identical work functions by said two control means and circuits for inhibiting the transmission of command signals from one of said control means to said inputoutput system.
2. A program controlled data handling system in accordance with claim 1, wherein each of said transmission buses comprises a plurality of parallel transmission paths transformer-coupled to said memories and to said control arrangement.
3. A program controlled data processing system comprising: a central processor having first and second independent central controls each having an active and a standby state; a clock oscillator in each of said central controls for generating oscillator output signals; bistable means in each of said central controls for defining the active and standby states of said central controls; means for controlling each of said bistable means, said controlling means concurrently sets the bistable means in the first central control to a first state and resets the bistable means in the second central control to a second state or concurrently resets the bistable means in the first central control to the second state and sets the bistable means in the second central control to the first state; clock means in each of said central controls responsive to clock oscillator output signals for generating clock signals defining central control machine cycles; and gating means responsive to the states of said bistable means for selectively connecting either of said oscillators to both of said clock means.
4. A system in accordance with claim 3 wherein each of said clock means generates clock phasing signals, and said gating means further comprises means for gating said clock phasing signal of the central control which has its bistable means in the first stable state to a phasing input terminal of the clock means in the central control which has its bistable means in the second state.
5. A system in accordance with claim 3 wherein said gating means is responsive to a first state signal from said bistable means of said first central control and to a second state signal of said bistable means of said second central control to connect said oscillator in said first central control to said clock means in both said first and said second central controls, and wherein said gating means is responsive to a first state signal from said bistable means of said second central control and a second state signal of said bistable means of said first central control to connect said oscillator means of said second central control to said clock means in both said first central control and said second central control.
6. A central processor of a program controlled data handling system comprising: first and second central controLs, means for placing said first and second central controls in an active unit state on a mutually exclusive basis; each of said central controls comprising an oscillator, and clock means responsive to oscillator output signals for generating clock timing signals and for generating clock phasing signals; and gating means for selectively gating output signals of the oscillator of the currently active central control to input terminals of said clock means in both of said central controls, and for connecting the clock phasing output signals of the clock circuit of the active central control to a phasing input terminal of the clock means of the standby central control. and gating means for connecting output signals of the oscillator of the currently active central control to input terminals of said clock means in both of said central controls, and for connecting the clock phasing output signals of the clock circuit of the active central control to a phasing input of the clock means of the standby central control.
7. In a data processing system, a central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently carry out identical system functions, means in each of said central processors for detecting faulty operation therein and for generating trouble signals upon detection of trouble, and means for transmitting said trouble signals from each of said central processors to the other of said central processors, and means in each of said central processors responsive to said trouble signals for carrying out identical central processor remedial actions.
8. In combination, a central processor system, said central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, means for selectively comparing data words concurrently generated in said active central processor and said standby central processor and for generating a trouble signal when said data words do not agree.
9. The combination in accordance with claim 8 wherein said means for comparing comprises an internal transmission bus within each of said central processors and gating means within each of said central processors for gating information from a plurality of locations within said central processor to said internal bus, a matching circuit in each of said central processors, transmission means for transmitting the information on each of said internal buses to the matching circuit of the other central control, and means within each of said central controls for gating information from said selected one of said plurality of locations within said central control to said match circuit within said central control, said match circuit comprising means for recording said information transmitted from said other central control, means for recording said information gated from said selected one of said plurality of locations within said central control, and means for comparing the contents of said recording means, said comparing means responsive to said contents for generating a trouble signal.
10. In combination, a central control system comprising first and second central controls, means in said central control system defining an active central control and a standby central control, a program store containing sequences of program order words, certain of said program sequences being normal data processing program sequences and others of said sequences being maintenance program order word sequences, each of said central controls comprising means for obtaining said sequences of order words from said program store and means for executinG said sequences, each of said central controls comprising registers for storing said program order words and a plurality of flip-flop registers, said active central control including means responsive to certain of said sequences of maintenance program order words for generating central control write command signals, said command signals comprising an order portion and a data portion, means for transmitting said central control write command signals to said standby central control, decoding means in said standby central control responsive to said order portion of said central control write command signals for storing in selected ones of said registers said data portion of said command signal.
11. In combination, a central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, a plurality of operational checking means within each of said central processors for detecting a plurality of classes of faulty responses of said central processors and for generating trouble signals discrete to the class of faulty response detected, means for transmitting said trouble signals from a central processor detecting a faulty response to the other central processor, means in each of said central processors for recording said trouble signals and means for selectively inhibiting the transmission of said trouble signals.
12. The combination in accordance with claim 11 wherein said means for inhibiting the transmission of trouble signals comprises a flip-flop in each of said central processors.
13. A central data processor system comprising an active central processor and a standby central processor each comprising a plurality of match points, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same sequences of system work functions, matching means for comparing match points in said active processor with corresponding match points in said standby processor, means for generating a trouble signal when compared match points do not agree, and match control circuitry defining the particular match points to be compared.
14. A central data processor system in accordance with claim 13 wherein said central processor system comprises means responsive to said trouble signals for momentarily interrupting the performance of said sequences of system work functions and other means for performing remedial work functions in each of said central processors, and means responsive to said trouble signal for inhibiting said matching means.
15. A central data processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, matching means comprising first and second match registers and a match circuit for comparing the contents of said registers and for generating a trouble signal when said compared contents do not agree, a plurality of corresponding data word sources in each of said central processors, a match control circuit for selectively gating information from corresponding data word sources of said active and said standby processor to said first and said second match registers respectively.
16. A program controlled central processor system for performing a plurality of classes of work functions comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same work functions, register means for recording the class of work funCtion currently being performed in said central processors, a plurality of corresponding data word sources in each of said central processors, matching means for comparing data words and for generating a trouble signal when compared data words do not agree, a match control circuit for selectively gating data words from corresponding data word sources of said active and said standby central processors to said matching means in accordance with the contents of said class of work register means.
17. A central processor system in accordance with claim 16 further comprising a plurality of control and supervisory circuits and wherein each of said central processors comprises a program store containing sequences of program order words, a data store containing pluralities of data words, and a central control for obtaining information from said stores, for writing information into said data store and for executing said programs obtained from said program store and wherein said classes of work comprise: a. execution of program order words for generating signals for controlling said control and supervisory circuits, b. execution of program order words for reading information from said data store, c. execution of transfer orders, d. execution of rereading of the program store or of the data store, and e. execution of work functions other than (a) thru (d) above.
18. A central processor system in accordance with claim 16 wherein said match control circuit comprises means responsive to certain states of said register means for cyclically obtaining from said active and said standby central processor data words from selected data word sources in each of said central processors.
19. A system in accordance with claim 18 wherein said means for cyclically obtaining comprises a binary counter, and said central processor system comprises clock means defining machine cycles and means for incrementing said binary counter by a count of 1 during each machine cycle in which said register means is in said certain states.
20. A central processor system for performing a plurality of work functions comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same work functions, a plurality of corresponding data word sources in each of said central processors, matching means comprising first and second match registers, a match circuit for comparing the contents of said registers for generating a trouble signal when said compared contents do not agree, a match control circuit, mode control register means for determining a plurality of modes of operation of said match control circuit, said modes including a routine matching mode and a plurality of maintenance modes, said match control circuit responsive to the contents of said mode control register for selectively gating information from said plurality of data word sources to said first and said second match registers.
21. A central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same sequences of system work functions, a plurality of corresponding data word sources in each of said central processors, matching means for comparing data words obtained from corresponding data word sources within each of said central processors, means for generating a trouble signal when said compared data words do not agree, operational checking means for detecting improper actions of said central processor system and for generating a fault signal upon occurrence of an improper action, means responsive to said fault signal for causing each of said central processors to concurrently carry out thE same remedial work functions, and means responsive to a fault signal occurring during a remedial work function to inhibit said matching means.
22. A data processing system comprising an active central processor and a standby central processor, each of said central processors comprising a program store containing sequences of program order words, a data store and a central control, means in each of said central controls for obtaining information from said program stores and from said data stores and for executing said sequences of program order words to perform system work functions, means in said data processing system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, operational checking means for checking the validity of information obtained from said program store and for generating first and second signals representative of a valid program store response and an invalid program store response respectively, remedial means responsive to said second signal for causing both of said central processors to generate reread commands to reread their respective program stores at the memory location from which the invalid response was obtained, said operational checking means being responsive to said information obtained by said reread command to generate said first and said second signals, means responsive to the enablement of said remedial means and said first signal of said operational checking means for comparing the information obtained by said active and said standby central processors from their respective program stores in response to said reread commands.
23. A data processing system in accordance with claim 22 wherein said central processor system comprises means responsive to said remedial means and to said second signal for recording a data word representative of the location in said program store from which the invalid response was obtained.
24. In a data processing system a central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same sequences of system work functions, matching means for comparing data words selectively obtained from a plurality of locations within each of said central processors, means for generating a trouble signal when said compared data words do not agree, a match control circuit comprising a point match register and a time match register, means in said central processor system for setting said point match register and said time match register to selected states, and means responsive to the states of said point match register and said time match register for selectively gating information to said matching means from the locations defined by the states of said point match register at a time defined by the states of said time match register.
25. A central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same work functions, means for comparing data words concurrently generated in said active central processor and said standby central processor and for generating a trouble signal when said data words do not agree, means in said central processor system for inhibiting said comparing means, and means for causing said active central processor and said standby central processor to operate independently of each other to concurrently perform the same or other system work functions.
26. In combination, an active central processor and a standby central processor, a first data register, means in said active central processor for writing a data constant in the saId first register, a second data register, means in the said standby central processor for gating data words from selected points within said standby central processor to said second data register, and means for comparing the contents of said first and said second data registers and for generating a match signal when said data constant and said gated data word agree.
27. A central processor system comprising a program store containing sequences of program order words, certain of said order words being transfer orders, a data store containing system data, a central control comprising means for generating code-addresses for obtaining information from said stores and for writing information into said data store, means for executing said sequences of program order words, and means responsive to the execution of said transfer orders for recording the code-address of an executed transfer word and the code-address of the order word to which transfer is made.
28. A system in accordance with claim 27 wherein said central control further comprises first and second register means, and wherein said means responsive to the execution of said transfer orders comprises means for writing said code-address of the executed transfer order into said first register means and for writing the code-address of the order transferred to in said second register means, and means for momentarily halting the obtaining of information from said program store and means for transmitting the contents of said first and said second register means to said data store.
29. A central processor system comprising a memory system wherein information is duplicated in independent units of said memory system, a central control, duplicate response transmission means interconnecting said memory system and said central control, means in said central control for generating code-addresses for obtaining information from said memory system, command transmission means interconnecting said central control and said memory system, means in said memory system responsive to said code-addresses for transmitting to said duplicate response bus systems duplicate information defined by said code-addresses, and means for comparing the data words concurrently occurring on said duplicate response transmission buses and for generating a trouble signal whenever said data words disagree.
30. A central processor system comprising an active central processor and a standby central processor each having a plurality of corresponding data word sources, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same sequences of system work functions, matching means for comparing data words gated thereto, means for generating a trouble signal when said compared data words do not agree, a match control circuit comprising a point match register and a timeout register, means in said central processor system for setting said point match register and said timeout register to selected states, a timeout counter, clock means defining a machine cycle and a plurality of phases within said machine cycle, means for incrementing said timeout counter once every machine cycle, means for comparing the states of said timeout register and said timeout counter for generating a match signal when the states of said counter and said timeout register agree, and means responsive to said match signal for selectively gating to said matching means data words obtained from corresponding data word sources of said processors and defined by the states of said point match register.
31. A central processor system in accordance with claim 30 wherein said match control circuit further comprises a phase match register and said central processor system comprises means for setting said phase match register to selected states and said means responsive to said match signal is also responsive to the state of said phase match register to gate said data words to said matching means during a phase of said machine cycle defined by the state of said phase match register.
32. A central processor system in accordance with claim 30 wherein said central processor system further comprises operational checking means for detecting faulty responses of said central processor system for generating trouble signals upon occurrence of a faulty response, remedial means responsive to said trouble signal for carrying out remedial system work functions and means responsive to said remedial means for inhibiting the incrementing of said timeout counter.
33. A central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, means for comparing data words concurrently generated in said active central processor and said standby central processor and for generating a trouble signal when said data words do not agree, and means in said central processor system responsive to said trouble signal for inhibiting said comparing means and for halting the operation of said standby central processor.
34. A central processor system comprising an active central processor and a standby central processor, means in said central processor system for causing said active central processor and said standby central processor to concurrently perform the same system work functions, independent matching means in each of said central processors comprising first and second match registers and a match circuit for comparing the contents of said registers and for generating a trouble signal when said compared contents do not agree, a plurality of corresponding data word sources in each of said central processors, and independent match control circuits in said active and said standby central processors for selectively gating information from said plurality of data word sources to both of said independent matching means.
35. A central processor system in accordance with claim 34 wherein said match control circuit in said active central processor selectively gates information from data word sources within said active central processor to said first match register within said active central processor and to said second match register within said standby central processor and wherein said match control circuit in said standby central processor selectively gates information from said plurality of data word sources within said standby central processor to said first match register within said standby central processor and to said second match register within said active central processor.
36. In combination, a central data processor comprising a central control system having first and second central controls, a semipermanent memory arrangement comprising a plurality of independent memory units, said central controls and said semipermanent memory units linked by duplicated input and output bus systems for transmitting commands from said central controls to said semipermanent memory units and for transmitting responses from said memory units to said central controls, and a temporary memory arrangement comprising a plurality of independent temporary memory units and duplicated input and output bus systems interconnecting said central controls and said temporary memory units for transmitting commands from said central controls to said temporary memory units and for transmitting responses from said temporary memory units to said central controls.
37. In combination, a memory system containing sequences of program order words and system data, and active and standby central controls; each of said central controls comprising means for obtaining information from said mEmory system, and means for executing said sequences of program order words; means in said active central control for generating stop and start signals, transmission means interconnecting said active central control and said standby central control for transmitting said stop and start signals, means in said standby central control responsive to said stop signal for halting the execution of said sequences of program order words by said standby central control, and means in said standby central control responsive to said start signals to initiate execution of said sequences of program order words by said standby central control.
38. The combination in accordance with claim 37 wherein said stop signals comprise fast stop signals and delayed stop signals and wherein said means in said standby-central control responsive to said stop signals comprises a stop sequencer, said sequencer responsive to said delayed stop signals to halt execution of said program order words by said standby-central control after said standby-central control has completed work operations defined by the order word being executed at the time said delayed stop signal was received, and said sequencer responsive to said fast stop signal to halt the execution of said sequences of order words without delay.
39. The combination system in accordance with claim 38 wherein each of said central controls comprises a plurality of flip-flop registers and said sequencer in said standby-central control in response to said fast stop signal generates reset signals for resetting certain of said plurality of flip-flop registers in said standby-central control.
40. In combination: a memory arrangement containing program order words, certain of said order words being control write order words, said memory arrangement comprising a plurality of storage locations dedicated to the storage of program order words, a plurality of control locations dedicated to the storage of memory control information, and means responsive to control write commands comprising address portions and data portions to gate the data portions of said commands to control locations defined by the address portions of said commands; and a central control comprising means for obtaining said program order words from said store system, means responsive to said control write program order words to generate said control write commands, and means for transmitting said control write commands to said program store system.
41. The combination in accordance with claim 40 wherein said program store system comprises a plurality of program stores and said program store control write command comprises two words, the first of said words comprises a. a multibit code portion defining the particular program store of said program store system that is to response to the command, and b. a mode portion defining the control write mode, said second word comprises a multibit data portion and wherein said transmission means comprises a plurality of individual transmission paths for parallel transmission of said first and said second words to said particular program store.
42. The combination in accordance with claim 41 wherein said means for executing said commands comprises decoding means and a data reading sequencer, said data reading sequencer responsive to output signals of said decoding means for generating said program store control write command signals and for momentarily inhibiting said decoding means.
43. In combination, a central control system comprising first and second central controls, means in said central control system defining said first and second central controls as an active central control and a standby central control, a program store containing sequences of program order words, certain of said program sequences being normal processing sequences and others of said sequences being maintenance program sequences, a data store containing system data EACH of said central controls comprising means for obtaining said sequences of order words from said program store and means for executing said sequences, each of said central controls comprising registers for storing said program order words and a plurality of flip-flop registers, said maintenance program sequences including standby-central control control write sequences, said active central control includes means responsive to said standby-central control control write sequences to generate control write command signals, said control write command signals comprising: a. a data store write command to place described data in a certain memory location in said data store, b. a standby-central control alerting command, c. a data store read command to read said data store at said certain memory location, response transmission means interconnecting said data store and said active and said standby-central controls, said standby-central control comprises decoding means responsive to said standby-central control alerting command for storing in selected ones of said flip-flop registers said information read from said data store.
44. The combination in accordance with claim 43 wherein said response transmission means comprises data store receiving means in said active and standby-central controls, terminating resistors, and a plurality of independent transmission paths serially connecting said data store receiving means in said active and said standby-central controls and said terminating resistors.
45. A system for automatically controlling the times at which operation of a data handling means is initiated, comprising timing means operable to different settings representing elapsed time, time entry storage means operable to a setting representing a time entry, means controlled by the data handling means during the carrying out of the program for controlling the time entry means to store a time entry representing the time at which the next program is to be initiated, start means in the data handling means for placing the data handling means in operation to carry out a program, and control means controlled by the timing means and the time entry storage means and connected to the start means for operating the start means when a predetermined relation exists between the settings of the timing means and the time entry means.
46. The system set forth in claim 45 in which the control means includes a plurality of data comparing gate means for comparing the settings of the timing means and the time entry storage means.
47. The system set forth in claim 45 in which the data handling means includes address means for supplying address signals and which includes, addressable means connected to the time entry storage means and the address means and controlled by the address signals for controlling the transfer of a time entry into the time entry storage means.
48. The system set forth in claim 47 including addressable reset means supplied with address signals from the data handling means and controlled by the receipt of a particular address to reset the time entry storage means.
49. A system for controlling the periods of operation of a data handling unit of the type capable of carrying out a sequence of programmed operations in response to actuation of a start means and capable of terminating its operation at the conclusion of the program, comprising a timing circuit operable to successive settings representing elapsed time, a time entry storing circuit adjustable to different settings under the control of the data handling unit representing future times, comparing means coupled to the timing circuit and the time entry storing circuit for comparing the settings thereof, means coupled to the start means and controlled by the comparing means for operating the start means to place the data handling unit in operation to carry out its program, means for clearing the time entry storing means, and means controlled by the data handling unit for adjusting the setting of the cleared time entry storing means to a new setting in dependence on the next time at which the data handling unit is to be started.
50. A data processor comprising: means for selectively performing data processing functions, storage means for storing data representing future time, means for entering data in said storage means, timing means for generating output signals representing present time, means for comparing said timing means output signals and said data representing future time to generate a timeout signal when a match occurs, means responsive to said timeout signal to effect a change in the performance of data processing functions by said processor.
51. A data processor in accordance with claim 50 wherein said change in the performance of data processing functions includes the initiation of data processing functions not being performed prior to the occurrence of said match.
52. In combination: a memory system comprising a plurality of independent memory units; a central processor system comprising a plurality of data processors; a transmission bus system for interconnecting said memory system and said central processor system and comprising a plurality of independent transmission paths, each of said independent transmission paths being selectively connectable to each of said data processors and each of said memory units; register means for storing information defining a plurality of subsystems, each subsystem comprising a selected one of said memory units, a selected one of said data processors, and a selected one of said independent transmission paths; and means for connecting said selected memory unit and said selected processor to said selected transmission path in accordance with information stored in said register means.
53. A data processing system comprising: an active central processor and a standby central processor each comprising a central control unit and an associated memory unit having a plurality of addressable locations, each central control unit comprising means for reading the addressable locations of the associated memory unit, means responsive to information read from said locations to perform prescribed data processing functions, and operational checking means for checking the validity of information read from said locations and for generating an invalidity signal upon the detection of invalid information; and means for causing said active and said standby central processors to concurrently perform identical data processing functions comprising a remedial means responsive to an invalidity signal generated by either of said operational checking means to cause both of said central control units to again read the location from which the invalid information was obtained.
54. A data processing system comprising: a pair of central processors each comprising indicator means and associated execution means, said indicator means each having two stable states and said execution means being responsive to one stable state of the associated indicator means to perform certain predetermined operations and responsive to the other stable state of the associated indicator means to perform other predetermined operations; and means for concurrently setting said indicator means to said stable states on a mutually exclusive basis, whereby the indicator means of a first central processor is set to one stable state while the indicator means of the other central processor is set to the other stable state.
55. A data processing system in accordance with claim 54 wherein said system further comprises a plurality of input-output units and transmission means for interconnecting said processors and said input-output units, and wherein each of said processors comprises command signal generating means for generating and transmitting input-output command signals, Said command signal generating means being responsive to the first state of said indicator means to generate and transmit said input-output command signals and responsive to the second state of said indicator means to inhibit the transmission of said input-output command signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US33487563A | 1963-12-31 | 1963-12-31 | |
| US68563667A | 1967-11-24 | 1967-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US3651480A true US3651480A (en) | 1972-03-21 |
Family
ID=26989438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US685636A Expired - Lifetime US3651480A (en) | 1963-12-31 | 1967-11-24 | Program controlled data processing system |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US3651480A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US3882455A (en) * | 1973-09-14 | 1975-05-06 | Gte Automatic Electric Lab Inc | Configuration control circuit for control and maintenance complex of digital communications system |
| US3931505A (en) * | 1974-03-13 | 1976-01-06 | Bell Telephone Laboratories, Incorporated | Program controlled data processor |
| US4040023A (en) * | 1975-12-22 | 1977-08-02 | Bell Telephone Laboratories, Incorporated | Recorder transfer arrangement maintaining billing data continuity |
| US5155678A (en) * | 1985-10-29 | 1992-10-13 | International Business Machines Corporation | Data availability in restartable data base system |
| US5204952A (en) * | 1988-07-18 | 1993-04-20 | Northern Telecom Limited | Duplex processor arrangement for a switching system |
| US5787156A (en) * | 1985-07-10 | 1998-07-28 | Ronald A. Katz Technology Licensing, Lp | Telephonic-interface lottery system |
| US5898762A (en) * | 1985-07-10 | 1999-04-27 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US5917893A (en) * | 1985-07-10 | 1999-06-29 | Ronald A. Katz Technology Licensing, L.P. | Multiple format telephonic interface control system |
| US6016344A (en) * | 1985-07-10 | 2000-01-18 | Katz; Ronald A. | Telephonic-interface statistical analysis system |
| US6044135A (en) * | 1985-07-10 | 2000-03-28 | Ronald A. Katz Technology Licensing, L.P. | Telephone-interface lottery system |
| US20020034283A1 (en) * | 1987-02-24 | 2002-03-21 | Ronald A. Katz Technology Licensing, L.P. | Voice-data telephonic interface control system |
| US6434223B2 (en) | 1985-07-10 | 2002-08-13 | Ronald A. Katz Technology Licensing, L.P. | Telephone interface call processing system with call selectivity |
| US6449346B1 (en) | 1985-07-10 | 2002-09-10 | Ronald A. Katz Technology Licensing, L.P. | Telephone-television interface statistical analysis system |
| US6512415B1 (en) | 1985-07-10 | 2003-01-28 | Ronald A. Katz Technology Licensing Lp. | Telephonic-interface game control system |
| US6570967B2 (en) | 1985-07-10 | 2003-05-27 | Ronald A. Katz Technology Licensing, L.P. | Voice-data telephonic interface control system |
| US6678360B1 (en) | 1985-07-10 | 2004-01-13 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US20040208299A1 (en) * | 1985-07-10 | 2004-10-21 | Katz Ronald A. | Voice-data telephonic interface control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3882455A (en) * | 1973-09-14 | 1975-05-06 | Gte Automatic Electric Lab Inc | Configuration control circuit for control and maintenance complex of digital communications system |
| US3931505A (en) * | 1974-03-13 | 1976-01-06 | Bell Telephone Laboratories, Incorporated | Program controlled data processor |
| US4040023A (en) * | 1975-12-22 | 1977-08-02 | Bell Telephone Laboratories, Incorporated | Recorder transfer arrangement maintaining billing data continuity |
| US20010021245A1 (en) * | 1985-07-10 | 2001-09-13 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US6349134B1 (en) | 1985-07-10 | 2002-02-19 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US5787156A (en) * | 1985-07-10 | 1998-07-28 | Ronald A. Katz Technology Licensing, Lp | Telephonic-interface lottery system |
| US5898762A (en) * | 1985-07-10 | 1999-04-27 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US5917893A (en) * | 1985-07-10 | 1999-06-29 | Ronald A. Katz Technology Licensing, L.P. | Multiple format telephonic interface control system |
| US6016344A (en) * | 1985-07-10 | 2000-01-18 | Katz; Ronald A. | Telephonic-interface statistical analysis system |
| US6035021A (en) * | 1985-07-10 | 2000-03-07 | Katz; Ronald A. | Telephonic-interface statistical analysis system |
| US6044135A (en) * | 1985-07-10 | 2000-03-28 | Ronald A. Katz Technology Licensing, L.P. | Telephone-interface lottery system |
| US6148065A (en) * | 1985-07-10 | 2000-11-14 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US20040208299A1 (en) * | 1985-07-10 | 2004-10-21 | Katz Ronald A. | Voice-data telephonic interface control system |
| US6292547B1 (en) | 1985-07-10 | 2001-09-18 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US6678360B1 (en) | 1985-07-10 | 2004-01-13 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface statistical analysis system |
| US20020025027A1 (en) * | 1985-07-10 | 2002-02-28 | Ronald A. Katz | Telephonic-interface statistical analysis system |
| US6570967B2 (en) | 1985-07-10 | 2003-05-27 | Ronald A. Katz Technology Licensing, L.P. | Voice-data telephonic interface control system |
| US20020033596A1 (en) * | 1985-07-10 | 2002-03-21 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface lottery system |
| US6424703B1 (en) | 1985-07-10 | 2002-07-23 | Ronald A. Katz Technology Licensing, L.P. | Telephonic-interface lottery system |
| US6434223B2 (en) | 1985-07-10 | 2002-08-13 | Ronald A. Katz Technology Licensing, L.P. | Telephone interface call processing system with call selectivity |
| US6449346B1 (en) | 1985-07-10 | 2002-09-10 | Ronald A. Katz Technology Licensing, L.P. | Telephone-television interface statistical analysis system |
| US6512415B1 (en) | 1985-07-10 | 2003-01-28 | Ronald A. Katz Technology Licensing Lp. | Telephonic-interface game control system |
| US5155678A (en) * | 1985-10-29 | 1992-10-13 | International Business Machines Corporation | Data availability in restartable data base system |
| US20020034283A1 (en) * | 1987-02-24 | 2002-03-21 | Ronald A. Katz Technology Licensing, L.P. | Voice-data telephonic interface control system |
| US5204952A (en) * | 1988-07-18 | 1993-04-20 | Northern Telecom Limited | Duplex processor arrangement for a switching system |
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