US3719767A

US3719767A - Signal-selecting system for a keyboard type electronic musical instrument

Info

Publication number: US3719767A
Application number: US00196894A
Authority: US
Inventors: K Matumoto; M Omura; M Tsunoo
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1970-11-29
Filing date: 1971-11-09
Publication date: 1973-03-06
Anticipated expiration: 1990-03-06
Also published as: CA931395A; NL174193B; DE2154409A1; NL7116160A; FR2115459B1; ZA717580B; FR2115459A1; IT945173B; GB1369656A; NL174193C; DE2154409B2; JPS5023982B1

Abstract

A SIGNAL-SELECTING SYSTEM FOR A KEYBOARD TYPE ELECTRONIC MUSICAL INSTRUMENT WHICH HAS A PLURALITY OF GENERATORS GENERATING TONE SIGNALS HAVING FREQUENCIES CORRESPONDING TO THE NOTES OF THE MUSICAL SCALE. THE SIGNALSELECTING SYSTEM HAS A PLURALITY OF KEYSWITCHES EACH HAVING A MOVABLE-CONTACT AND A MAKE-CONTACT, AND A PLURALITY OF MEMORY MEANS EACH HAVING A SET TERMINAL, A RESET TERMINAL, A COMMON RESET TERMINAL AND AN OUTPUT TERMINAL. THE SET TERMINAL IS COUPLED TO A CORRESPONDING ONE OF THE KEYSWITCHES. A PLURALITY OF GATE MEANS IS PROVIDED, ONE BEING COUPLED BETWEEN EACH MEMORY MEANS AND A CORRESPONDING TONE GENERATOR SO AS TO PRODUCE A SELECTED OUTPUT TONE SIGNAL. A RESET MEANS IS COUPLED BETWEEN THE OUTPUT TERMINALS AND THE COMMON RESET TERMINALS. AN ELECTRIC POWER SOURCE IS CONNECTED THROUGH A COMMON LINE TO THE KEYSWITCHES. A PLURALITY OF RESET ELEMENTS IS PROVIDED, ONE BEING CONNECTED BETWEEN EACH OF THE KEYSWITCHES AND THE RESET TERMINAL OF THE MEMORY MEANS NEXT ADJACENT TO THE MEMORY MEANS CORRESPONDING TO SAID EACH OF SAID KEYSWITCHES, AND A PLURALITY OF DIODES ARE PROVIDED WHICH ARE CONNECTED IN SERIES, AND EACH DIODE IS ALSO CONNECTED BETWEEN RESET TERMINALS OF TWO ADJACENT MEMORY MEANS.

Description

March 6, 1973 KENJI MATUMQTQ EI'AL 3,7l9,767

SIGNAL-SELECTING SYSTEM FOR A KEYBOARD TYPE LECTRON I C MUS I CAL INSTRUMENT 5 Sheets-Sheet 2 Filed Nov. 9, 1971 AMPLIFIER 0 INVENTORS KENJI MATUMOTO MASUO OMURA MASA HIKO TSUNOO v/wmwwaak ATTORNEYS Marh 6, 1973 KENJI MATUMQTO ETAL 3,719,767 w SIGNAL-SELECTING SYSTEM FOR A KEYBOARD TYPE ELECTRONIC MUS ICAL INSTRUMENT 5 Sheets-Sheet 3 Filed Nov. 9, 1971 AMPLIFIER FIG.4

\GATE MEMOR Y MEANS GATE MEMORY MEANS MEMORY 27 MEANS 5 Sheets-Sheet L AMPLIFIERH March 1973 KENJI MATUMOTO ETM SIGNAL'SELECTING SYSTEM FOR A KEYBOARD TYPE ELECTRONIC MUSICAL INSTRUMENT Filed Nov. 9. 1971 5ATE FIGS GATE 1 3 33 (J5GATE 58 MEMoRY 28 MEANS MEANS RESET MEMORY MEANS KENJI MATUMOTO ETAL 3,719,757 SIGNAL-SELECTING SYSTEM FOR A KEYBOARD TYPE ELECTRONI C MUS I CAL INSTRUMENT 5 Sheets-Sheet 5 AMPLIFIER IO! \-GATE MEMORY 29 MEANS FIG.6

MEMORY MEANS RESET MEANS m mm M March 6, 1973 Filed Nov. 9, 1971 United States Patent 3,719,767 SIGNAL-SELECTING SYSTEM FOR A KEYBOARD TYPE ELECTRONIC MUSICAL INSTRUMENT Kenji Matumoto, Nara, Masuo ()mura, Hirakata, and

Masahiko Tsunoo, Suita, Japan, assignors to Matsushita Electric Industrial Co., Ltd., Osaka, Japan Filed Nov. 9, 1971, Ser. No. 196,894 Claims priority, application Japan, Nov. 29, 1970, 45/105,349 Int. Cl. Gh 1/00 US. Cl. 84--1.01 11 Claims ABSTRACT OF THE DISCLOSURE A signal-selecting system for a keyboard type electronic musical instrument which has a plurality of generators generating tone signals having frequencies corresponding to the notes of the musical scale. The signalselecting system has a plurality of keyswitches each having a movable-contact and a make-contact, and a plurality of memory means each having a set terminal, a reset terminal, a common reset terminal and an output terminal. The set terminal is coupled to a corresponding one of the keyswitches. A plurality of gate means is provided, one being coupled between each memory means and a corresponding tone generator so as to produce a selected output tone signal. A reset means is coupled between the output terminals and the common reset terminals. An electric power source is connected through a common line to the keyswitches. A plurality of reset elements is provided, one being connected between each of the keyswitches and the reset terminal of the memory means next adjacent to the memory means corresponding to said each of said keyswitches, and a plurality of diodes are provided which are connected in series, and each diode is also connected between reset terminals of two adjacent memory means.

FIELD OF THE INVENTION This invention relates to a keyboard type electronic musical instrument and more particularly to a novel signal selecting system capable of selecting a tone signal having the lowest or the highest frequency from among the tone signals produced by the instrument when a plurality of keyswitches are simultaneously closed. Upon simultaneous closing of more than two keyswitches, a voltage (or current) from an electric power source resets memory means corresponding to keyswitches aligned in one direction beyond the extreme one of the keyswitches which are simultaneously closed. Then said voltage (or current) sets only one memory means corresponding to the extreme one of keyswitches which are closed simultaneously. Said one memory means is-maintained in the set state after opening of said extreme one of keyswitches until any of the other keyswitches is closed.

DESCRIPTION 'OF THE PRIOR ART A conventional keyboard type electronic musical instrument is provided with a conventional signal-selecting system comprising many transfer type keyswitches, each of which has a break-contact, a make-contact, and a movable-contact. Transfer type keyswitches are connected in such a way that the make-contacts of the transfer type keyswitches are connected to set terminals of corresponding memory means, respectively, and are connected in series in such a way that the movable-contact of one transfer type keyswitch is connected to the break-contact of another transfer type keyswitch and the movable-contact of said another transfer type keyswitch is connected to the break-contact of a further transfer type keyswitch and so on. In addition, the movable-contact of the last 3,719,767 Patented Mar. 6, 1973 transfer type keyswitch is connected to an electric power source. Said memory means control switching on and off of corresponding gate means which control tone signals from corresponding generators. The outputs of said memory means are coupled to a reset means which generates a reset pulse to reset memory means each time any of the movable-contacts of said transfer type keyswitches is closed against a make-contact or when more than two of the memory means are set simultaneously. Therefore, of course, upon simultaneous closing of more than two of said transfer type keyswitches, the conventional signalselecting system sets only one memory means corresponding to the extreme one of the keyswitches which is closed simultaneously. Thus, such a conventional signal-selecting system is able to select the lowest frequency tone signal corresponding to the lowest note keyswitches from among keyswitches closed simultaneously and is also able to maintain the set state of only one memory means after opening of the extreme one of keyswitches until any of the other keyswitches is closed.

Said conventional signal-selecting system, however, is apt to have frequent break-downs due to poor contacts in the transfer type keyswitches. The reason is that the set terminal of any given memory means is coupled to the electric power source through a series connection consisting of many transfer type keyswitches having many contact points comprised of a make-contact and a movable-contact and of a break-contact and a movable-contact, respectively.

Therefore, only a small number of transfer type keyswitches can successfully be connected in series in a conventional signal-selecting system, if the system is to be reliable. In a conventional signal-selecting system, the use of many transfer type keyswitches results in lower reliability.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide an improved and reliable signal-selecting system for a keyboard type electronic musical instrument.

Another object of the present invention is to provide a reliable signal-selecting system which employs a plurality of keyswitches which are easily available.

A further object of the present invention is to provide a signal-selecting system comprising a plurality of keyswitches of the make-contact type.

A further object of the present invention is to provide a signal-selecting system comprising a plurality of keyswitches of the bus-bar type.

A further object of the present invention is to provide a signal-selecting system capable of selecting a tone signal having the lowest or the highest frequency from among the tone signals produced by the keyswitches which are simultaneously closed.

These objectives are achieved by employing a signalselecting system according to the present invention for selecting a tone signal from among a plurality of tone signals generated by a plurality of generators generating tone signals having frequencies corresponding to the notes of the musical scale. The system comprises a plurality of keyswitches each corresponding to one of said frequencies corresponding to the notes of the musical scale, and each having a movable-contact and a make-contact, a plurality of memory means, one corresponding to each of said plurality of generators and each having a set terminal,

said set terminal being coupled to a corresponding keysource connected through a common line to said plurality of keyswitches, a plurality of reset elements, one being connected between each of said plurality of keyswitches and a reset terminal of an adjacent memory means next to the memory means corresponding to said each of sa1d plurality of keyswitches, and diodes connected in series, and each of which is connected between two reset terminals of adjacent memory means.

Upon closing of one of said keyswitches, voltage (or current) from said electric power source sets the memory means corresponding to said one of said keyswitches and resets the memory means corresponding to the keyswitches aligned in one direction beyond said one of keyswitches. Upon simultaneous closing of not less than two of said keyswitches, voltage (or current) from said electric power source resets the memory means corresponding to the keyswitches aligned in one direction beyond the extreme one of keyswitches closed simultaneously. This voltage (or current), therefore, sets only one memory means corresponding to the extreme one of keyswitches closed simultaneously. The reset means generates a reset pulse for resetting the memory means set previ ously in the set state.

Therefore, this signal-selecting system can select the tone signal having the highest or the lowest frequency from among the tone signals produced by the plurality of keyswitches closed simultaneously, by the arrangement of diodes, reset elements, keyswitches and memory means.

Other objects and features of the invention will be made clear from the following detailed description of the invention, with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram of an embodiment of the signal-selecting system of the present invention;

FIG. 2 is a schematic circuit diagram of another embodiment of the signal-selecting system of the present invention employing flip-flop circuits as memory means;

FIG. 3 is a schematic circuit diagram of an embodiment of a memory means with corresponding generator and gate means; and

FIGS. 4, 5 and 6 are further examples of the signal selecting system of FIG. 1.

PREFERRED EMBODIMENTS Referring to FIG. 1 showing an embodiment of a signal selecting system,

generators

1, 2, 3 and 4 are provided which generate tone signals having frequencies corresponding to the notes of the musical scale. Keyswitches 11, 12, 13 and 14 correspond to the

respective generators

1, 2, 3 and 4, respectively, and have movable-

contacts

6, 7, 8 and 9 and make-

contacts

16, 17, 18 and 19, respectively. Memory means 21, 22, 23 and 24 correspond to the

respective generators

1, 2, 3 and 4 and have set

terminals

26, 27, 28 and 29,

reset terminals

36, 37, 38 and 39,

common reset terminals

46, 47, 48 and 49, and

output terminals

56, 57, 58 and 59, each respectively. Said set

terminals

26, 27, 28 and 29 are connected to said

movable contacts

6, 7, 8 and 9, respectively.

In each of said memory means 21, 22, 23 and 24, voltage (or current) applied to the reset terminal resets the memory means notwithstanding whether voltage (or current) is applied to the set terminal or not.

Gate means 31, 32, 33 and 34 are coupled to said

output terminals

56, 57, 58 and 59, respectively, and are controlled by the output of the corresponding memory means 21, 22, 23 and 24. Said gate means 31, 32, 33 and 34 control output of the tone signals from said

generators

1, 2, 3 and 4, respectively, so as to produce an output tone signal selected. A reset means 101 is coupled between said

output terminals

56, 57, 58 and 59 and said

common reset terminals

46, 47, 48 and 49. An electric power source 102 is connected through a common line 103 to said make-

contacts

16, 17, 18 and 19.

Reset elements

41, 42 and 43 are connected between

movablecontacts

6, 7 and 8 and the

reset terminals

37, 38 and 39 of memory means 22, 23 and 24 next adjacent to the memory means 21, 22 and 23 corresponding to said

movable contacts

6, 7 and 8, respectively.

Diodes

51, 52 and 53 are connected in series. Each of said diodes 51, S2 and 53 is connected between the reset terminals of two adjacent memory means, i.e. the diode 51 is connected betwen

adjacent reset terminals

36 and 37, the diode 52 is connected between

adjacent reset terminals

37 and 38, and the diode 53 is connected between

adjacent reset terminals

38 and 39. Outputs of the

gates

31, 32, 33 and 34 are fed to a sign-a1 amplifier 104 amplifying the selected tone signal.

When only the keyswitch 11 is closed, the voltage (or current) from said electric power source 102 is applied, through the common line 103 and said keyswitch 11, to the set terminal 26 so as to set only the memory means 21. Said voltage (or current) also resets memory means 22, 23 and 24 through the reset element 41 and the reset terminal 37, the reset element 41, the diode 52 and the reset terminal 38, and the reset element 41, the

diodes

52 and 53 and the reset terminal 39, each respectively. The memory means 21 is maintained in the set state, even after the keyswitch 11 is opened again, and the gate 31 is maintained in the switched on state so as to produce an output tone signal from tone generator 1. Then when another keyswitch is closed, for example, keyswitch 12, the voltage (or current) from said electric power source 102 is applied to the set terminal 27 so as to set the memory means 22 and to reset memory means 23 and 24 in a manner similar to that in which keyswitch 11 resets memory means 22, 23 and 24. In this case, however, two memory means 21 and 22 might be in the set states simultaneously because said memory means 21 has been set previously. When this occurs, said reset means 101 detects through the

output terminals

56 and 57 that two memory means 21 and 22 are set, and resets the memory means 21 which has been set previously. As a result, only the memory means 22 is set and maintained in the set state. When either of the other keyswitches 8 or 9 is closed, the voltage (or current) from said electric power source 102 is applied to the corresponding set terminal 28 or 29 so as to set only one corresponding memory means 23 or 24, respectively, in the same manner as that described in relation to the

keyswitches

11 and 12.

Upon the simultaneous closing of two keyswitches, for example 11 and 12, the voltage (or current) from said electric power source 102 resets all the memory means 22, 23 and 24 corresponding to keyswitches 12, 13 and 14 aligned in one direction beyond the extreme one 11 of the keyswitches among

keyswitches

11 and 12 closed simultaneously by means of the reset element 41 and the

diodes

52 and 53. As a result, said voltage (or current) sets only one memory means 21 corresponding to the keyswitch 11, which is the extreme one of the keyswitches among

keyswitches

11 and 12 closed simultaneously.

In summary, upon closing of one of the keyswitches, the voltage (or current) from said electric power source 102 sets one memory means corresponding to said one of the keyswitches. Said voltage (or current) also resets the memory means corresponding to the keyswitches aligned in one direction beyond said one of keyswitches by means of the reset element corresponding to said one of said keyswitches and through the diodes connected to said reset element. Said reset means 101 detects when two or more memory means are set and generates a reset pulse so as to reset the memory means which has been set previously. Upon simultaneous closing of not less than two keyswitches, the voltage (or current) from said electric power source resets the memory means corresponding to the keyswitches aligned in one direction beyond the extreme one of the keyswitches closed simultaneously by means of the reset element corresponding to said extreme one of the keyswitches and through the diodes connected to said reset element. Said reset means 101 detects when two or more memory means are set and generates a reset pulse so as to reset the memory means which has been set previously. As a result, said voltage (or current) sets only one memory means corresponding to the extreme one of the kcyswitches closed simultaneously. Then even after opening of the keyswitch, the corresponding memory means is maintained in the set state, and the corresponding gate is maintained in the switched-on state so as to produce an output tone signal.

The

diodes

51, 52 and 53 prevent inverse currents. The diode, for example I52, obstructs an inverse current which otherwise might flow into the reset terminal 37 from the reset terminal 38 of the next memory means 23 when the keyswitch 12 is closed.

Each of the

reset elements

41, 42' and 43 can be composed of an electric conductor as shown in FIG. 4. The reset elements 41", 42" and 43" can also be composed of isolating resistors, as shown in FIG. 5 or diodes 41", 42" and 43", the anodes of which are connected to the

movable contacts

6, 7 and 8, and the cathodes of which are connected to the

reset terminals

37, 38 and 39, respectively, as shown in FIG. 6.

In the latter case, the reset elements 41", 42" and 43" attenuate or obstruct the flows of inverse currents. Each reset element, for example element 42", attenuates or obstructs an inverse current which otherwise might flow into a set terminal, such as terminal 27, from the reset terminal, such as terminal 38, of the next memory means, such as means 23, therethrough when the keyswitch, such as keyswitch 11, is closed. The diode 51 can be removed when no reset element is connected to the reset terminal 36.

FIG. 2 shows another embodiment of the signa1-selecting system of the present invention, in which memory means 21, 22, 23 and 24 are composed of flip-flop circuits, and gate means 31,32, 33 and 34 are composed of respec tive input and output resistors and output impedances located at the

output terminals

56, 57, 58 and 59 of the memory means 21, 22, 23 and 24, respectively.

The memory means 21 comprises a first transistor 201, a second transistor 206, a base resistor 211 connected between the base of said first transistor 201 and a reference potential, such as ground, a common reset resistor 216 connected between the base of said second transistor 206 and the common reset terminal 46, a first feedback resistor 221 connected between the collector of said first transistor 201 and the base of said second transistor 206, a second feedback resistor 226 connected between the collector of said second transistor 206 and the base of said first transistor 201, a first collector resistor 231 connected between the collector of said one transistor 201 and a collector power source 106, a second collector resistor 236 connected between the collector of said second transistor 206 and said collector power source 106, a set resistor 241 connected between the set terminal 26 and the base of said first transistor 201, and a reset resistor 246 connected between the reset terminal 36 and the base of said second transistor 206, the emitters of said first transistor 201 and said second transistor 206 being connected through an emitter bias line 107 to an emitter bias source 105.

The voltage (or current) applied to the set terminal 26 is fed, through the set resistor 241, to the base of the transistor 201 so as to saturate the transistor 201. Then a voltage drop is caused at the collector of the transistor 201. Said voltage drop is fed back to the base of the transistor 206 through the feed back resistor 221 so as to make the transistor 206 cut off. Then a voltage jump is caused at the collector of the transistor 206. Said voltage jump is also fed back to the base of the transistor 201 through the feedback resistor 226 so as to saturate the transistor 201 deeply. As a result, the memory means 21 is set in the set state.

The voltage (or current) applied to the reset terminal 36 or to the common reset terminal 46 is fed through the reset resistor 246 or the common reset resistor 216, respectively, to the base of the transistor 206 so as to saturate the transistor 206. Then a voltage drop is caused at the collector of the transistor 206. Said voltage drop is fed back to the base of the transistor 201 so as to make the transistor 201 cut 011. Then a voltage jump is caused at the collector of the transistor 201. Said voltage jump is also fed back to the base of the transistor 206 through the feed back resistor 221 so as to saturate the transistor 206 deeply. As a result, the memory means 21 is reset.

The other memory means 22, 23 and 24 have the same configuration and operation as memory means 21. The detailed description of those memory means 22, 23 and 24, therefore, is unnecessary.

The gate means 31 comprises an input resistor 251 connected between the generator 1 and the output terminal 56 of the memory means 21, an output resistor 256 connected between the output terminal 56 and the signal amplifier 104, and is affected by the impedance at the output terminal 56 of the memory means. The output impedance of the output terminal 56 is high or low, corresponding to whether the memory means 21 is set or reset, respectively. The output terminal 56 acts as a shunt type gate means in association with the input resistor 251 and the output resistor 256.

Application of voltage (or current) to the set terminal 26 saturates the transistor 201 and makes the transistor 206 cut 011 so as to give the output terminal 56 a high impedance. As the shunt impedance of the shunt type gate means 31 is high, the tone signal from the generator 1 is derived through the input and output resistors 2'51 and 256. As a result, the gate means 31 is switched on.

On the other hand, application of voltage (or current) to the reset terminal 36 or the common reset terminal 46 saturates the transistor 206 and makes the transistor 201 out 01f so as to give the output terminal 56 a low impedance. As the shunt impedance of the shunt type gate means 31 is low, the tone signal from the generator 1 is bypassed to the reference potential through the low impedance exit between the collector and emitter of the transistor 206 and the emitter bias source having low impedance. Therefore, no output tone signal is derived from the gate means 31.

As a result, the gate means 31 is switched off. The other gate means 32, 33 and 34 have the same configuration and operation as gate means 31 so that detailed description of them is unnecessary.

The reset 101 is further connected through the emitter bias line 107 to the emitter bias source 105. Said reset means 101 compares the DC. potential at the output terminals of the memory means or the gate means 31, 32, 33 and 34 with the DC. potential at the emitter bias line 107 connected to said emitter bias source 105 and connected to the emitters of the

transistors

201, 202, 203, 204, 206, 207, 208 and 209. Then, said reset means 101 produces a reset pulse so as to reset the memory means set previously through the

common reset terminals

46, 47, 48 and 49 when two or more memory means are set in the set state.

The reset means 101 operates and generates a reset pulse in the following manner. When only one memory I means is set, then the output voltage therefrom rises. In this case, however, the reset means 101 neither operates nor generates a reset pulse, because the voltage rise is below the threshold voltage of the reset means 101. When the keyswitch 14 is closed, after closing keyswitch 11 so as to set memory means 21 and then opening it, the two memory means 21 and 24 are set. When two memory means are set in the above mentioned manner, the output voltage therefrom rises beyond the threshold voltage of the reset means 101. Therefore, the reset means operates and generates an output voltage which quickly resets the memory means 21 and 24 through the

reset terminals

46 and 49. After the reset operation is performed, only one memory means 24 will be set, if the keyswitch 14 remains closed. The output voltage of the reset means 101 then decreases quickly to zero again. The operation as explained heretofore is performed very rapidly. As a result, therefore, the reset means 101 generates a reset pulse having a very narrow pulse width so as to reset the memory means which has previously been set. The particular circuit arrangement required for the reset means 101 is not critical, as long as the circuit is capable of generating an output pulse when a given input voltage is reached. Such circuits are generally referred to in the art as Schmitt triggers, see for example, Watson, J. Semiconductor Circuit Design, N.J., D. Van Norstrand, 1966, p. 192.

The Schmitt trigger is a regenerative circuit which changes states abruptly when the input signal rises beyond a specific threshold voltage. These circuits are therefore readily adaptable for use as reset means 101. However, as would be obvious to one skilled in the art, the reset means 101 may also be composed of a conventional combination of a DC. comparator and a switching circuit or a conventional combination of a DC. comparator and a one-shot multivibrator.

In the embodiments of FIGS. 1 and 2, the

movablecontacts \

6, 7, 8, and 9 can be replaced by the make-

contacts

16, 17, 18 and 19, respectively, a shown in FIG. 5.

FIG. 3 shows another embodiment of the memory means with corresponding generator and gate means, in which memory means, designated generally as 25, has a set terminal 30, a reset terminal 40, a common reset terminal 50 and an output terminal 60, and comprises a first transistor 330, the emitter of which is connected to the reference potential, such as ground, a second transistor 329, the emitter of which is connected to the collector of said first transistor 330, a set resistor 326 connected between said set terminal 30 and the base of said second transistor 329, a reset resistor 336 connected between said reset terminal 40 and the base of said first transistor 330, a common reset resistor 346 connected between said common reset terminal 50 and the base of said first transistor 330, a shunt resistor 327 connected between the base of said second transistor 329 and the reference potential, a collector resistor 328 connected between a collector power source 306 and the collector of said second transistor 329, and a memory capacitor 331 connected between said output terminal 60 and the reference potential. Said ouput terminal 60 is connected to the junction of the collector of said first transistor 330 and the emitter of said second transistor 329. Positive voltage applied to the set terminal 30 is fed through the set resistor 326 to the base of said second transistor 329. Said positive voltage switches said second transistor 329 on so as to charge the memory capacitor 331 through the collector resistor 328 and said second transistor 329 from the collector source 306. Thus, the memory means 25 is set in the set state. In this case, the reset terminal 40 and the common reset terminal 50 are not supplied with any voltage. On the other hand, positive voltage applied to the reset terminal 40' or the common reset terminal 50 is fed through the reset resistor 336 or the common reset resistor 346, respectively, to the base of said first transistor 330. Said positive voltage switches said one transistor 330 on so as to discharge the memory capacitor 331 through said first transistor 330. Thus, the memory means 25 is reset. The output of the memory means 25 controls a gate means 35 so as to switch the tone signal from a generator 5 on and off. In the memory means 25, voltage (or current) applied to the reset terminal 40 or the common reset terminal 50 resets the memory means 25 notwithstanding whether voltage (or current) is applied to the set terminal 30 or not. The memory means 25, therefore, can also be used in the signal selecting system in place of the memory means 21, 22, 23 and 24.

The signal selecting system of the invention can be used for a manual keyboard, as well as a pedal keyboard. While particular embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that numerous modifications and variations can be made in the form and construction thereof without departing from the fundamental principles of the invention. It is, therefore, desired by the following claims, to include within the scope of the present invention all similar and modified forms of the apparatus disclosed, and by which the results of the invention can be obtained.

What is claimed is:

1. A signal-selecting system for a keyboard type electronic musical instrument having a plurality of generators generating tone signals having frequencies corresponding to the notes of the musical scale; said system comprising:

a plurality of keyswitches one corresponding to each of said plurality of generators and each having a movable-contact and a make-contact;

a plurality of memory means, one corresponding to each of said plurality of generators and each having a set terminal, a reset terminal, a common reset terminal and an output terminal, said set terminal being coupled to the corresponding one of said plurality of keyswitches;

a plurality of gate means, one being coupled between the corresponding one of said plurality of memory means and the corresponding tone generator so as to produce a selected output tone signal from said corresponding generator;

a reset means coupled between said output terminals and said common reset terminals;

an electric power source connected in parallel to said plurality of keyswitches;

a plurality of reset elements one being connected between each of said plurality of keyswitches and the reset terminal of the memory means next adjacent to the memory means corresponding to said one of said plurality of keyswitches; and

a plurality of diodes connected in series and each of which is connected between two reset terminals of adjacent memory means;

whereby upon closing of one of said keyswitches, said electric power source sets the memory means corresponding to said one of keyswitches and resets the memory means corresponding to keyswitches aligned in one direction beyond said one of keyswitches, said reset means generating a reset pulse for resetting a memory means set previously in the set state, or upon simultaneous closing of not less than two of said keyswitches, said electric power source sets only one memory means corresponding to the extreme one of the keyswitches closed simultaneously and resets the memory means corresponding to keyswitches aligned in one direction beyond said extreme one of the keyswitches closed simultaneously, said reset means generating a reset pulse for resetting a memory means set previously in the set state. i

2. A signal-selecting system as claimed in claim 1 wherein the movable-contact of each keyswitch is connected to said electric power source and the make-contact of each keyswitch is connected to the set terminal of said corresponding memory means.

3. A signal-selecting system as claimed in claim 1 wherein the make-contact of each keyswitch is connected to said electric power source and the movable-contact of each keyswitch is connected to the set terminal of said corresponding memory means.

4. A signal-selecting system as claimed in claim 3 wherein a common line is provided connecting said keyswitches to said power source, and said common line is a bus-bar and is the make-contact of said plurality of keyswitches.

5. A signal-selecting system as claimed in claim 1 wherein each of said plurality of reset elements is composed of an electric conductor.

6. A signal-selecting system as claimed in claim 1 wherein each of said plurality of reset elements is composed of a resistor.

7. A signal-selecting system as claimed in claim 1 wherein each of said plurality of reset elements is composed of a diode.

8. A signal-selecting system as claimed in claim 1 wherein said gate means each comprises an input resistor connected to the corresponding generator and an output resistor connected in series with the input resistor, the output from which is the selected signal, output terminal of the corresponding memory means being connected to the junction of said resistors, said output terminal having a high output impedance or a low output impedance when the memory means is set or reset and acting as a shunt type gate means.

9. A signal-selecting system as claimed in claim 1 wherein each of said memory means is composed of a flip-flop circuit.

10. A signal-selecting system as claimed in claim 1 wherein each of said memory means comprises a first transistor having an emitter connected to a reference potential, a second transistor having an emitter connected to the collector of said one transistor, a set resistor connected between said set terminal and the base of said second transistor, a reset resistor connected between said reset terminal and the base of said first transistor, a common reset resistor connected between said common reset terminal and the base of said first transistor, a shunt resistor connected between the base of said second transistor and said reference potential, a collector resistor connected between a collector power source and the collector of said second transistor, and a memory capacitor connected between said reference potential and said output terminal, said output terminal being connected to the junction of the collector of said first transistor and the emitter of said second transistor.

11. A signal-selecing system as claimed in claim 1 further comprising a common bias source connected to said memory means and to said reset means, said reset means having means for comparing the DC. potential of the common bias source with the DC. potential at the output terminals of said memory means and producing a reset pulse which resets all said memory means through said common reset terminal of each of said memory means when not less than two memory means are being set.

References Cited UNITED STATES PATENTS 1/1970 Hiyoshi 84-l.0l X 8/1971 Yamashita 84-1.01

U.S. Cl. X.R.

84DIG. 8