US4257825A - Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers - Google Patents

Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers Download PDF

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US4257825A
US4257825A US06/063,314 US6331479A US4257825A US 4257825 A US4257825 A US 4257825A US 6331479 A US6331479 A US 6331479A US 4257825 A US4257825 A US 4257825A
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test
wafers
thermal treatment
radiation
semiconductor
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US06/063,314
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Hanno Schaumburg
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US Philips Corp
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US Philips Corp
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Priority claimed from DE19782837776 external-priority patent/DE2837776A1/en
Priority claimed from DE19782848331 external-priority patent/DE2848331A1/en
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Assigned to U.S. PHILIPS CORPORATION, A CORP. OF DE. reassignment U.S. PHILIPS CORPORATION, A CORP. OF DE. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SCHAUMBURG HANNO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

A method of manufacturing semiconductor devices in which at least one zone is formed in a number of semiconductor wafers by implantation of doping ions and by a subsequent thermal treatment. In order to reduce the costs for the thermal treatment (individual test wafers) and to reduce the spread, at least one test figure is formed in each semiconductor wafer by the implantation and is subjected to a thermal treatment after the implantation of the doping ions by means of an intensive radiation directed thereon. The electrical properties of the test figure are then measured and further thermal treatment of the whole semiconductor wafer is determined in accordance with the result of this measurement.

Description

The invention relates to a method of manufacturing semiconductor devices in which at least one zone of a given conductivity type is provided in a number of semiconductor wafers by implantation of doping ions and by a subsequent thermal treatment of the whole semiconductor wafer.
In such a method in which stringent tolerance requirements are imposed upon the doping, (for example, in high-frequency transistors and capacitance diodes), the process control is important. It is endeavoured to obtain as early as possible control parameters with which the thermal treatment (to eliminate the lattice defects resulting from the implantation and to diffuse the implanted doping ions) can be influenced as efficaciously as possible.
It has so far been usual to implant semiconductor wafers of a batch (for example 30 plates) simultaneously with one wafer comprising exclusively test figures. This test wafer is then treated thermally at a comparatively low temperature of, for example, 900° C. From the sheet resistance then measured at the test figures, data are derived for the control of the thermal treatment of the batch (usually at temperatures far above 900° C.).
However, this method used so far is rather unreliable while in addition a wafer comprising only test figures is necessary for each batch, which wafers cannot be used further.
One of the objects of the invention is to carry out the method of the kind described in such manner that control parameters for the thermal treatment of the semiconductor wafers which enable a directed thermal treatment can be determined in a simple manner and without separate test wafers.
According to the invention this is achieved in that at least one test figure is formed in each semiconductor wafer by the implantation; that after the implantation of the doping ions only the test figure is subjected to a thermal treatment by means of an intensive radiation directed selectively thereon; that the electrical properties of the test figure are then measured and that the further thermal treatment of the whole semiconductor wafer is determined on the basis of the result of this measurement.
The radiation used may be both of an electromagnetic and of a corpuscular nature. According to a first preferred embodiment optical radiation originating from a laser is used. According to a further preferred embodiment an electron beam is used.
For completeness' sake it is to be noted that it is known (Appl. Phys. Letters, 32 (1978), 3, pp. 139-141) to eliminate the lattice defects in silicon doped by ion implantation by irradiation with a laser. However, the use of this process in a method of the kind described is not suggested in this article.
It is achieved inter alia by means of the method according to the invention that no separate test wafers need be used. Furthermore, the control parameters can be determined for each individual wafer so that for thermal treatment new batches each with substantially equal control parameters can be composed. As a result of this, the variation in properties between the manufactured semiconductor wafers can be considerably reduced. This is of particular importance in implantations in epitaxial layers the thickness and also the doping of which may vary rather considerably between individual wafers.
The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing, in which:
FIG. 1 is a diagrammatic plan view of a semiconductor wafer, and
FIG. 2 is a diagrammatic cross-sectional view of the wafer shown in FIG. 1 during the performance of the method according to the invention.
FIG. 1 is a plan view of a semiconductor wafer 1 on the major surface of which several (in this case four) test FIG. 3 for measuring the sheet resistance of the semiconductor body are provided in addition to the actual semiconductor devices 2 to be manufactured (which are shown diagrammatically only).
For a given critical doping process, the whole semiconductor wafer including the test figures is subjected to doping by ion implantation.
As is shown diagrammatically in FIG. 2, the surface of the semiconductor wafer is then covered with a mask 4 which exposes only the test FIG. 3. The test figure(s) is (are) then heated (continuously or pulsatingly) by means of a laser radiation 5 directed thereon. The energy transferred to the test figures by the laser radiation is controlled so that partial or complete annealing of the lattice defects caused by the preceding ion implantation takes place.
After removing the mask, a sheet resistance may be measured at the test figures which resistance is determined by the preceding implantation process and the starting doping of the semiconductor wafer 1. This sheet resistance value is then used to control the thermal treatment to which the actual semiconductor devices 2 in the plate 1 are then subjected. This may be thermal treatment of the whole wafer in a furnace or a thermal treatment by means of an intensive electromagnetic or corpuscular radiation.
When treating the wafers 1 in a furnace it is efficacious to compose the individual wafers to form new batches on the basis of the measured results at the test figures.
According to a modified embodiment of the method only the test figures of the wafers 1 after the ion implantation are heated by means of an electron beam 5 directed only on the test figures by a suitable deflection system. In this case the mask 4 is superfluous. The further measurement and processing is carried out in the same manner as in the preceding example.

Claims (8)

What is claimed is:
1. A method of manufacturing semiconductor devices in which at least one zone of a given conductivity type is provided in a number of semiconductor wafers comprising the steps of implanting doping ions into each semiconductor wafer to form at least one test figure, subjecting only said test figure to a thermal treatment by selectively directing an intensive radiation thereon, measuring electrical properties of said test figure, and carrying-out further thermal treatment of the entire semiconductor wafer as a result of said measuring step.
2. A method as claimed in claim 1, wherein said intensive radiation is optical radiation originating from a laser.
3. A method as claimed in claim 1, wherein said intensive radiation is radiation from an electron beam.
4. A method as claimed in one of claims 1, 2 or 3, wherein said intensive radiation is directed selectively on said test figure by using a mask.
5. A method as claimed in one of claims 1, 2 or 3, wherein said intensive radiation is directed as a direct beam only on said test figure in the absence of a mask.
6. A method as claimed in one of claims 1, 2, or 3, wherein after said steps of subjecting said test figure to intensive radiation and measuring said electrical properties, the semiconductor wafers are divided into groups, and each group of said wafers are subjected to the same further thermal treatment.
7. A method as claimed in claim 4, wherein after said steps of subjecting said test figure to intensive radiation and measuring said electrical properties, the semiconductor wafers are divided into groups and each group of said wafers are subjected to the same further thermal treatment.
8. A method as claimed in claim 5, wherein after said steps of subjecting said test figure to intensive radiation and measuring said electrical properties, the semiconductor wafers are divided into groups and each group of said wafers are subjected to the same further thermal treatment.
US06/063,314 1978-08-30 1979-08-02 Method of manufacturing semiconductor devices having improvements in device reliability by thermally treating selectively implanted test figures in wafers Expired - Lifetime US4257825A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE19782837776 DE2837776A1 (en) 1978-08-30 1978-08-30 Semiconductor module mfr. - by ion implantation basing heat treatment on laser radiation of test figures
DE2837776 1978-08-30
DE19782848331 DE2848331A1 (en) 1978-11-08 1978-11-08 Mfg. semiconductor devices without using separate test wafers - determining optimum heating conditions by measuring sheet resistance of selected doped zones
DE2848331 1978-11-08

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386459A (en) * 1980-07-11 1983-06-07 Bell Telephone Laboratories, Incorporated Electrical measurement of level-to-level misalignment in integrated circuits
US4668330A (en) * 1985-12-05 1987-05-26 Monsanto Company Furnace contamination
US4776917A (en) * 1984-12-24 1988-10-11 Shin-Etsu Chemical Co., Ltd. Single crystal wafer of lithium tantalate
US5403753A (en) * 1993-07-15 1995-04-04 Texas Instruments Incorporated Method of forming implant indicators for implant verification
US5434089A (en) * 1992-07-30 1995-07-18 Sgs-Thomson Microelectronics S.A. Method for testing the sheet resistivity of diffused layers
US5451529A (en) * 1994-07-05 1995-09-19 Taiwan Semiconductor Manufacturing Company Method of making a real time ion implantation metal silicide monitor
US5677041A (en) * 1993-03-25 1997-10-14 Texas Instruments Incorporated Integrated circuits formed in radiation sensitive material and method of forming same
US5834364A (en) * 1995-12-20 1998-11-10 Sgs-Thomson Microelectronics, S.A. Method of implementing of a reference sample for use in a device for characterizing implanted doses
FR2776831A1 (en) * 1998-03-27 1999-10-01 Mitsubishi Electric Corp DEVICE INCLUDING A MOS TRANSISTOR AND METHOD FOR DEVELOPING SUCH A DEVICE ON A SELF SUBSTRATE
US5970313A (en) * 1997-12-19 1999-10-19 Advanced Micro Devices, Inc. Monitoring wafer temperature during thermal processing of wafers by measuring sheet resistance of a test wafer
US6246102B1 (en) 1990-09-28 2001-06-12 Texas Instruments Incorporated Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture
US6417515B1 (en) 2000-03-17 2002-07-09 International Business Machines Corporation In-situ ion implant activation and measurement apparatus
CN101393906B (en) * 2007-09-17 2011-07-06 中芯国际集成电路制造(上海)有限公司 Ion injection test body, ion injection region mask board and ion injection test method
US10429747B2 (en) * 2016-11-11 2019-10-01 Applied Materials, Inc. Hybrid laser and implant treatment for overlay error correction

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2078441A (en) * 1980-06-17 1982-01-06 Westinghouse Electric Corp Forming impurity regions in semiconductor bodies by high energy ion irradiation
TW248612B (en) * 1993-03-31 1995-06-01 Siemens Ag

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB993388A (en) * 1964-02-05 1965-05-26 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices
GB1153282A (en) * 1965-05-25 1969-05-29 Philips Electronic Associated Improvements in or relating to Methods Of and Devices For The Thermal Processing of Material By Means Of Laser Beams
US3723873A (en) * 1971-01-21 1973-03-27 Singer Co Radiation method for determining semiconductor stability and reliability
US3725148A (en) * 1970-08-31 1973-04-03 D Kendall Individual device tuning using localized solid-state reactions
US4151008A (en) * 1974-11-15 1979-04-24 Spire Corporation Method involving pulsed light processing of semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB993388A (en) * 1964-02-05 1965-05-26 Standard Telephones Cables Ltd Improvements in or relating to semiconductor devices
GB1153282A (en) * 1965-05-25 1969-05-29 Philips Electronic Associated Improvements in or relating to Methods Of and Devices For The Thermal Processing of Material By Means Of Laser Beams
US3725148A (en) * 1970-08-31 1973-04-03 D Kendall Individual device tuning using localized solid-state reactions
US3723873A (en) * 1971-01-21 1973-03-27 Singer Co Radiation method for determining semiconductor stability and reliability
US4151008A (en) * 1974-11-15 1979-04-24 Spire Corporation Method involving pulsed light processing of semiconductor devices

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Calhoun et al., "Product Simulators", IBM-TDB, 12, (1970), 1214. *
Dhaka et al., "Measurement . . . Sheet Resistivity", IBM-TDB, 13, (1970), 14. *
Greenwald et al., "J. Appl. Phys.", 50, (Feb. 1979), 783. *
Narayan et al., J. Appl. Phys., 49, (1978), 3912. *
Shtyrkov et al., Sov. Phys. Semicond., 9, (1976), 1309. *
Young et al., Appl. Phys. Letts. 33, (1978), 14. *
Young et al., Appl. Phys. Letts., 32, (1978), 139. *

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386459A (en) * 1980-07-11 1983-06-07 Bell Telephone Laboratories, Incorporated Electrical measurement of level-to-level misalignment in integrated circuits
US4776917A (en) * 1984-12-24 1988-10-11 Shin-Etsu Chemical Co., Ltd. Single crystal wafer of lithium tantalate
US4898641A (en) * 1984-12-24 1990-02-06 Shin-Etsu Chemical Co., Ltd. Single crystal wafer of lithium tantalate
US4668330A (en) * 1985-12-05 1987-05-26 Monsanto Company Furnace contamination
US6246102B1 (en) 1990-09-28 2001-06-12 Texas Instruments Incorporated Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture
US5434089A (en) * 1992-07-30 1995-07-18 Sgs-Thomson Microelectronics S.A. Method for testing the sheet resistivity of diffused layers
US5691089A (en) * 1993-03-25 1997-11-25 Texas Instruments Incorporated Integrated circuits formed in radiation sensitive material and method of forming same
US5942374A (en) * 1993-03-25 1999-08-24 Texas Instruments Incorporated Integrated circuits formed in radiation sensitive material and method of forming same
US5677041A (en) * 1993-03-25 1997-10-14 Texas Instruments Incorporated Integrated circuits formed in radiation sensitive material and method of forming same
US5403753A (en) * 1993-07-15 1995-04-04 Texas Instruments Incorporated Method of forming implant indicators for implant verification
US5594258A (en) * 1993-07-15 1997-01-14 Texas Instruments Incorporated Semiconductor device with reticle specific implant verification indicator
US5451529A (en) * 1994-07-05 1995-09-19 Taiwan Semiconductor Manufacturing Company Method of making a real time ion implantation metal silicide monitor
US5834364A (en) * 1995-12-20 1998-11-10 Sgs-Thomson Microelectronics, S.A. Method of implementing of a reference sample for use in a device for characterizing implanted doses
US5970313A (en) * 1997-12-19 1999-10-19 Advanced Micro Devices, Inc. Monitoring wafer temperature during thermal processing of wafers by measuring sheet resistance of a test wafer
US6033922A (en) * 1997-12-19 2000-03-07 Advanced Micro Devices, Inc. Monitoring wafer temperature during thermal processing of wafers by measuring sheet resistance of a test wafer
FR2776831A1 (en) * 1998-03-27 1999-10-01 Mitsubishi Electric Corp DEVICE INCLUDING A MOS TRANSISTOR AND METHOD FOR DEVELOPING SUCH A DEVICE ON A SELF SUBSTRATE
US7129543B1 (en) 1998-03-27 2006-10-31 Renesas Technology Corp. Method of designing semiconductor device, semiconductor device and recording medium
US20060267096A1 (en) * 1998-03-27 2006-11-30 Renesas Technology Corp. Method of designing semiconductor device, semiconductor device and recording medium
US6417515B1 (en) 2000-03-17 2002-07-09 International Business Machines Corporation In-situ ion implant activation and measurement apparatus
CN101393906B (en) * 2007-09-17 2011-07-06 中芯国际集成电路制造(上海)有限公司 Ion injection test body, ion injection region mask board and ion injection test method
US10429747B2 (en) * 2016-11-11 2019-10-01 Applied Materials, Inc. Hybrid laser and implant treatment for overlay error correction

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GB2030361A (en) 1980-04-02
FR2435125A1 (en) 1980-03-28

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