US4593453A - Two-level transistor structures and method utilizing minimal area therefor - Google Patents
Two-level transistor structures and method utilizing minimal area therefor Download PDFInfo
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- US4593453A US4593453A US06/621,773 US62177384A US4593453A US 4593453 A US4593453 A US 4593453A US 62177384 A US62177384 A US 62177384A US 4593453 A US4593453 A US 4593453A
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- oxide
- pmos
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- active area
- polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Definitions
- the invention relates to a novel structure and method for forming stacked transistors and, in particular, CMOS structures for latch-up free operations.
- CMOS devices and enhancement-depletion devices utilizing either NMOS or PMOS technology. Since isolation wells are not used to isolate the NMOS from PMOS, all common PNPN paths are eliminated so that the CMOS bulk devices are latch-up free--all with an increased density advantage over existing techniques because of the elimination of space taken up by isolation wells.
- the invention is a two-layer multi-transistor device minimizing chip area required per transistor.
- One device is built on bulk silicon and the second device is built on the field oxide from a laser recrystallized polysilicon layer of which only one is required in the multi-transistor structure, thereby simplifying the process.
- the active area of the bulk silicon device is surrounded by field oxide and covered by a thin layer of gate oxide.
- Undoped polysilicon is deposited over the field oxide and recrystallized by laser beam or other appropriate technique.
- a second mask provides for defining a gate for the bulk silicon device and an active area on the field oxide for the second level device.
- the poly is lightly doped everywhere with the appropriate species (N-) and a third mask is used to define, e.g., the NMOS areas.
- the drain source, and gate may be implanted N+, followed by cross-over oxide (N+).
- mask 4 is used to etch the cross-over oxide to define the P-channel active area.
- Nitride is deposited and mask 5 defines the P-channel gate.
- P+ is used to dope the drain and source of the PMOS device followed by oxidation over the P+ drain and source area.
- the nitride is removed to bare poly to rent the growing of the P-channel gate oxide.
- Contact mask 6 is used to etch the oxide followed by metal deposition and mask 7 serves to etch the metal followed sintering.
- the principles permit the production of matched transistors, enhancement-depletion devices, either NMOS or PMOS, and other conventional FET structures.
- FIG. 1 is a view of a common known well-type prior art device
- FIG. 2 is a prior art well-less type stacked arrangement of transistors
- FIG. 3 shows a device of the present invention during processing
- FIG. 3A shows a preferred manufactured product
- FIG. 4 shows the first step in the preferred process of the present invention
- FIG. 5 shows the gate oxide covering the active region of the left-hand bulk silicon transistor device being formed surrounded by field oxide
- FIG. 6 shows the structure of FIG. 5 covered by undoped, recrystallized polysilicon
- FIG. 7 shows masks 1, 2, 6, and 7
- FIG. 7A shows masks 3, 4, and 5;
- FIG. 8 shows the structure in a succeeding step in the process forming the gate for the left-hand region and the active area on the field oxide for the right-hand transistor region;
- FIG. 9 shows doping of the source and drain for the left-hand transistor and doping for the right-hand transistor being developed on the field oxide
- FIG. 10 depicts doping of the PMOS drain and source
- FIG. 11 shows the growing of the P+ gate oxide
- FIG. 12 illustrates the opening of contact regions.
- this Stacked Transistor approach has been documented in the Background of the Invention section.
- this prior art involves two layers of polysilicon, i.e., the gate poly 21 and the poly layer 23.
- Poly 21 comprises the gate for the first transistor and poly level 23 comprises the second transistor stacked thereabove. Since the NMOS and PMOS have poly gates the PMOS device is not self-aligned, i.e., it will require device size to density and speed compromises, however, there is no latch-up because of the elimination of the PNPN paths. Laser recrystallization of the second poly is required.
- FIGS. 3 through 12 show a preferred present device and process for manufacturing the same.
- FIG. 3 shows a CMOS device in process of manufacture wherein a single layer of polysilicon has been employed to form the NMOS gate 31 and the body portion 33 of the PMOS device deposited on the field oxide 35 nitride 37 being used to maintain or preserve the N-channel between the source and drain 39 and 41 (FIG. 3A) formed between the steps of FIGS. 3 and 3A.
- FIG. 3A it may be seen that the NMOS device is formed to the left on the bulk silicon substrate 43 employing the portion 31 of the single poly layer as the gate for this device which is isolated in the cross-over oxide 45.
- the PMOS device utilizes another portion of the single poly layer as the source 39, drain 41, and channel 47, all situated on top of the field oxide 35.
- the present invention offers the only single poly layer process, which of course simplified the process and renders greater yields.
- the obvious advantage of density improvement over the ubiquitous well approach provides scalability to submicron dimensions.
- both PMOS and NMOS are self-aligning and can be separately optimized. This improves speed and performance in general.
- By utilizing the silicon field oxide for the PMOS device there can be no latch-up because there is no PNPN path.
- the devices can be reversed in position and manufactured similarly where other devices may be built in the processing according to the principles herein taught, i.e., either N-channel or P-channel can be built on the bulk silicon and two-layer enhancement depletion devices with either FET built on the bulk silicon may be accommodated.
- the silicon wafer comprises the bulk silicon 43 which is oxidized to form a first oxide layer 51 covered by a nitride layer 53 and mask 1 of FIG. 6 is used to define the active area of the left-hand transistor device, shown herein as an NMOS device.
- the resist 55 protects the underlying deposited nitride layer 53 and silicon oxide layer 51 during removal of the uncovered nitride and oxide layers.
- field oxide 57 is conventionally grown in the regions not covered by the resist 55.
- an underlying nitride layer 53 and oxide layer 51 to expose the bare surface of silicon in the active region.
- the next step is to grow gate oxide in the active region as is illustrated at 61 in FIG. 5.
- Step 1- Grow oxide and deposit nitride
- FIG. 6 the structure of FIG. 5 has been covered by undoped polysilicon shown as the layer 63 which is subsequently recrystallized.
- the listing of the preferred process may be updated as follows:
- Mask 1 is shown at 65 as comprising the rectangular opaque outline which reserved the resist portion 55 after exposure of the resist layer to light and development thereof. Reference will be made further to these two figures as the individual masks are employed in the processing to be described hereinafter.
- the polysilicon layer 63 of FIG. 6 has been doped N- everywhere and mask 2 of FIG. 7 consisting of the left-hand vertical rectangular opaque region 71 and the right-hand horizontal opaque region 72 has been utilized with conventional masking and etching techniques to outline the N gate 73 of the left-hand NMOS device being formed and the active area 75 for the right-hand PMOS device being formed on the field oxide 57.
- steps 5 through 8 of FIGS. 6 and 7 has:
- Step 5 deposit undoped polysilicon followed by recrystalliation
- Step 6 dope the polysilicon N- everywere
- Step 7 use mask 2 for laying down a resist and etching regions of the poly not covered by the resist which are;
- Step 8 the N gate region for the NMOS device on the left and the active area on the field oxide for the device for the PMOS device on the right;
- mask 3 of FIG. 7a is incorporated to define the NMOS region of the left-hand device for the purpose of doping the source 81 and drain 83 N+.
- Mask 3 is in reality an opening rather than being opaque, and accordingly the deposition or implanting of the N+ doping is ineffective in the field oxide 57 and merely changes the doping of the gate poly 73 from N- to N+. However, it is effective on the bare silicon to dope the source 81 and drain 83.
- the cross-over oxide or Silox 85 is deposited over the entire region. Accordingly, the steps of the process now added are:
- Step 11 Deposit cross-over oxide.
- mask 4 of FIG. 7A is utilized to etch the cross-over oxide 57 from the PMOS active area 75.
- Mask 4 is an open mask for the entire active area 75.
- the oxide 91 is grown and a layer of nitride 93 is deposited thereover.
- mask 5 of FIG. 7A is employed, being an opaque mask to define the PMOS gate region and to provide hardened resist thereover such that the nitride layer 93 and oxide layer 91 which are uncovered are removed.
- the PMOS source 95 and drain 97 are then doped P+ by ion implantation whereas the channel region 99 is protected by the nitride 93.
- the nitride 93 and the oxide 91 are removed to permit the subsequent step of oxidation over the PMOS drain-source region as shown in FIG. 11 at 101.
- Step 12 use open mask 4 for etching the cross-over oxide from the P active area.
- Step 13 grow oxide over region 75 and deposit nitride thereover
- Step 14 use mask 5 to define the PMOS gate and remove the oxide and nitride layers except under mask 5.
- the next step is illustrated by oxidation of the exposed field oxide 57 and the poly region 75 with the oxidation shown at 101.
- the nitride 93 and the oxide 91 are removed, followed thereafter by growing the thin field oxide 103 over the gate region of the N- poly body 75.
- Step 15 dope the drain and source 95 and 97 P+ (FIG. 10).
- Step 16 oxidize over the P+ drain and source areas.
- Step 17 remove the nitride and oxide to bare poly and grow the thin gate oxide for the PMOS device.
- the chip being processed has been prepared for metal deposition by employing contact mask 6 of FIG. 7 to open the source 81 by opening 111, gate 73 by opening 112, and drain 83 by opening 113 through the cross-over oxide 85 for the NMOS device.
- contact mask 6 of FIG. 7 to open the source 81 by opening 111, gate 73 by opening 112, and drain 83 by opening 113 through the cross-over oxide 85 for the NMOS device.
- the PMOS device it is only necessary to provide openings 114 and 116 to the source 95 and drain 97 because the gate 103 is already open to receive the metal deposits, which results in a metal-gate PMOS device.
- the metallization mask 7 is also pictured in FIG. 7 and shows the outline of the metal conductive film preserved to connect in FIG. 3 to the metal contacts 111', 112', 113', 114' and 116'.
- the gate contact 115' is automatically provided by the metal at the location 115 of FIG. 7.
- two NMOS devices may be produced utilizing the process outlined for the left-hand NMOS device or similarly two PMOS devices may be produced utilizing the process outlined for the right-hand PMOS device.
- the concept of stacking simply permits greater density of whichever devices are selected for processing and this includes self-aligned devices due to the use of mask 2.
- CMOS devices depletion and/or enhancement FETS or unitary assemblies.
- the gate of the first transistor is self-aligned to its drain and source by use of the poly mask 2.
- the gate of the second transistor is self-aligned to its own drain and source by virtue of mask 5.
- the single layer of polysilicon provides the first transistor gate 73 and the active body portion 75 for the second transistor.
- Use of the mask 2 defines the active body portion of the second transistor while defining the gate of the first transistor.
- mask 5 defines the drain, source and gate of the second transistor by virtue of the active polysilicon portion 75. Consequently, inherent alignment is manifested between the two transistors. It should further be noted that all elements of each transistor are in linear alignment, thus, again improving the yield and conserving the space otherwise required.
Abstract
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US06/621,773 US4593453A (en) | 1982-06-01 | 1984-06-18 | Two-level transistor structures and method utilizing minimal area therefor |
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US38339582A | 1982-06-01 | 1982-06-01 | |
US06/621,773 US4593453A (en) | 1982-06-01 | 1984-06-18 | Two-level transistor structures and method utilizing minimal area therefor |
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Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4740478A (en) * | 1987-01-30 | 1988-04-26 | Motorola Inc. | Integrated circuit method using double implant doping |
US4799097A (en) * | 1987-07-29 | 1989-01-17 | Ncr Corporation | CMOS integrated devices in seeded islands |
US4837176A (en) * | 1987-01-30 | 1989-06-06 | Motorola Inc. | Integrated circuit structures having polycrystalline electrode contacts and process |
DE4038114A1 (en) * | 1989-11-29 | 1991-06-13 | Toshiba Kawasaki Kk | SEMICONDUCTOR STORAGE AND METHOD FOR THE PRODUCTION THEREOF |
US5028976A (en) * | 1986-10-17 | 1991-07-02 | Canon Kabushiki Kaisha | Complementary MOS integrated circuit device |
US5067002A (en) * | 1987-01-30 | 1991-11-19 | Motorola, Inc. | Integrated circuit structures having polycrystalline electrode contacts |
US5072277A (en) * | 1989-07-10 | 1991-12-10 | Nippondenso Co., Ltd. | Semiconductor device with gradually varying doping levels to compensate for thickness variations |
US5493139A (en) * | 1993-05-27 | 1996-02-20 | Sharp Kabushiki Kaisha | Electrically erasable PROM (E2 PROM) with thin film peripheral transistor |
US5770892A (en) * | 1989-01-18 | 1998-06-23 | Sgs-Thomson Microelectronics, Inc. | Field effect device with polycrystalline silicon channel |
US5811865A (en) * | 1993-12-22 | 1998-09-22 | Stmicroelectronics, Inc. | Dielectric in an integrated circuit |
US5927992A (en) * | 1993-12-22 | 1999-07-27 | Stmicroelectronics, Inc. | Method of forming a dielectric in an integrated circuit |
US6140684A (en) * | 1997-06-24 | 2000-10-31 | Stmicroelectronic, Inc. | SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers |
US6638824B2 (en) | 1998-12-28 | 2003-10-28 | Fairchild Semiconductor Corporation | Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage |
US7078296B2 (en) | 2002-01-16 | 2006-07-18 | Fairchild Semiconductor Corporation | Self-aligned trench MOSFETs and methods for making the same |
EP1751794A2 (en) * | 2004-05-28 | 2007-02-14 | Fairchild Semiconductor Corporation | Method for enhancing field oxide and integrated circuit with enhanced field oxide |
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Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5028976A (en) * | 1986-10-17 | 1991-07-02 | Canon Kabushiki Kaisha | Complementary MOS integrated circuit device |
US5067002A (en) * | 1987-01-30 | 1991-11-19 | Motorola, Inc. | Integrated circuit structures having polycrystalline electrode contacts |
US4837176A (en) * | 1987-01-30 | 1989-06-06 | Motorola Inc. | Integrated circuit structures having polycrystalline electrode contacts and process |
US4740478A (en) * | 1987-01-30 | 1988-04-26 | Motorola Inc. | Integrated circuit method using double implant doping |
US4799097A (en) * | 1987-07-29 | 1989-01-17 | Ncr Corporation | CMOS integrated devices in seeded islands |
US5770892A (en) * | 1989-01-18 | 1998-06-23 | Sgs-Thomson Microelectronics, Inc. | Field effect device with polycrystalline silicon channel |
US5072277A (en) * | 1989-07-10 | 1991-12-10 | Nippondenso Co., Ltd. | Semiconductor device with gradually varying doping levels to compensate for thickness variations |
DE4038114A1 (en) * | 1989-11-29 | 1991-06-13 | Toshiba Kawasaki Kk | SEMICONDUCTOR STORAGE AND METHOD FOR THE PRODUCTION THEREOF |
DE4038114C2 (en) * | 1989-11-29 | 1999-03-18 | Toshiba Kawasaki Kk | Method of manufacturing a semiconductor memory |
US5493139A (en) * | 1993-05-27 | 1996-02-20 | Sharp Kabushiki Kaisha | Electrically erasable PROM (E2 PROM) with thin film peripheral transistor |
US5811865A (en) * | 1993-12-22 | 1998-09-22 | Stmicroelectronics, Inc. | Dielectric in an integrated circuit |
US5927992A (en) * | 1993-12-22 | 1999-07-27 | Stmicroelectronics, Inc. | Method of forming a dielectric in an integrated circuit |
US6140684A (en) * | 1997-06-24 | 2000-10-31 | Stmicroelectronic, Inc. | SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers |
US6638824B2 (en) | 1998-12-28 | 2003-10-28 | Fairchild Semiconductor Corporation | Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage |
US7078296B2 (en) | 2002-01-16 | 2006-07-18 | Fairchild Semiconductor Corporation | Self-aligned trench MOSFETs and methods for making the same |
EP1751794A2 (en) * | 2004-05-28 | 2007-02-14 | Fairchild Semiconductor Corporation | Method for enhancing field oxide and integrated circuit with enhanced field oxide |
EP1751794A4 (en) * | 2004-05-28 | 2007-10-03 | Fairchild Semiconductor | Method for enhancing field oxide and integrated circuit with enhanced field oxide |
US20080113482A1 (en) * | 2004-05-28 | 2008-05-15 | Leibiger Steven M | Method for enhancing field oxide |
US7824999B2 (en) | 2004-05-28 | 2010-11-02 | Fairchild Semiconductor Corporation | Method for enhancing field oxide |
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