US4745463A - Generalized chrominance signal demodulator for a sampled data television signal processing system - Google Patents
Generalized chrominance signal demodulator for a sampled data television signal processing system Download PDFInfo
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- US4745463A US4745463A US06/911,424 US91142486A US4745463A US 4745463 A US4745463 A US 4745463A US 91142486 A US91142486 A US 91142486A US 4745463 A US4745463 A US 4745463A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
Definitions
- the present invention relates to a chrominance signal demodulator for video signals which have been sampled at a rate substantially equal to N/D times the frequency of the color subcarrier signal, where N and D are integers.
- Digital and other sampled data circuitry are becoming commonplace in video signal processing apparatus.
- Comb filters, digital signal processing circuitry and field of frame store memories are found in equipment ranging from business teleconferencing systems to consumer television receivers.
- the frequency at which the samples are developed i.e. the sampling clock frequency
- sampling clock frequency In any of these signal processing systems, several factors act to limit the frequency of the sampling clock signal.
- Third, to simplify the demodulation of the chrominance signal components of the video signal it is desirable for the sampling clock signal to be locked in phase to the color synchronizing burst signal component of the video signal.
- the composite video signal consists of a luminance signal component and a chrominance signal component.
- the chrominance signal component is a combination of two color difference signals which modulate quadrature phase related, suppressed subcarrier signals.
- the chrominance samples obtained may be represented as a function of the instantaneous amplitudes of the two baseband color difference signals and the phase angle of the sampling points with respect to a predetermined reference phase.
- a chrominance sample, C s may be represented by the equation (1).
- ⁇ is the phase angle between the sampling point and the (B-Y) phase of the color subcarrier signal.
- FIGS. 1 and 2 show a portion of the color reference burst signal component of an NTSC composite video signal, which is at the -(B-Y) phase, sampled using clock signals that are phase-locked to the negative peaks of the burst signal and having frequencies of 4f c and (32/13) f c respectively.
- the samples taken with the 4f c clock signal occur at 90° phase intervals with respect to the (B-Y) phase of the color subcarrier signal.
- the sequence of chrominance samples may be represented as (B-Y), (R-Y), -(B-Y), -(R-Y), etc.
- This sequence of samples may be demodulated into sequences of samples representing the (R-Y) and (B-Y) color difference signals by separating the (R-Y) samples from the (B-Y) samples and inverting alternate samples in each of the separated sequences.
- any sequence of 32 consecutive samples there is one (B-Y) sample, one (R-Y) sample, one -(B-Y) sample and one -(R-Y) sample.
- the other 28 samples in the sequence are mixtures of the (B-Y) and (R-Y) color difference signals. Consequently, it is more difficult to recover the baseband (B-Y) and (R-Y) color difference signals than it would be if the signal were samples at 4f c .
- the present invention is embodied in circuitry for processing the chrominance signal component of a composite video signal which also includes a horizontal line synchronizing signal component.
- the chrominance signal includes a color information signal modulating a carrier signal.
- the processing circuitry which embodies the invention demodulates the chrominance signal to recover the baseband color information signal.
- the chrominance signal applied to the processing circuitry is sampled in synchronism with a clock signal having a frequency substantially equal to N/D times the frequency of the carrier signal, where N and D are integers.
- the sampled data chrominance signal is applied to a programmable sampled data filter which includes a plurality of delay stages and a plurality of programmable sample scaling circuits.
- the scale factors used by the programmable sample scaling circuits are changed in N steps by circuitry which is responsive to the clock signal and to a phase alignment signal.
- the filter provides output samples representing the baseband color information signal.
- FIGS. 1 and 2 illustrate waveforms useful in explaining the operation of the invention.
- FIG. 3 is a block diagram of video signal processing apparatus including an embodiment of the present invention.
- FIG. 4 is a block diagram of a clock signal generator suitable for use with the embodiment of the invention shown in FIG. 3.
- FIG. 5 is a block diagram of a chrominance signal demodulator embodying the present invention.
- NTSC digital television receiver The embodiment of the invention described below is in the context of a NTSC digital television receiver. However, it is contemplated that the invention may be practiced in analog sampled data systems which use, for example, charge transfer devices and that it may also be implemented in receivers which use other signal standards, or in teleconferencing equipment or studio video signal processing equipment.
- broad arrows represent busses for multiple-bit parallel digital signals and line arrows represent connections conveying analog signals or single bit digital signals.
- compensating delays may be required in certain of the signal paths.
- One skilled in the art of digital signal processing circuit design would know where such delays would be needed in a particular system.
- radio frequency (RF) television signals are received by an antenna 310 and applied to a tuner 312.
- the tuner 312 which may be of conventional design, selects an RF signal having a predetermined carrier frequency and heterodynes it with an oscillatory signal generated by a local oscillator (not shown) to develop an intermediate frequency (IF) signal.
- the IF signal is applied to the IF amplifier and detector circuitry 314.
- This baseband television signal includes a video portion, which may, for example, contain luminance and chrominance signal components, occupying a band of frequencies from 0 to 4.2 MHz, and an audio portion which may, for example, consist of an audio signal modulating a 4.5 MHz carrier signal.
- the baseband television signals provided by the circuitry 314 are applied to band-pass filter and 4.5 MHz trap circuitry 316.
- the circuitry 316 processes the baseband television signals to provide the modulated audio signal component to the substantial exclusion of the video signal, at a first output terminal and the video signal component, CV, to the substantial exclusion of the modulated audio signal, at a second output terminal.
- the first output terminal of the circuitry 316 couples the modulated audio signal to the audio circuitry 318.
- the circuitry 318 may, for example, demodulate the signal applied to its input port and amplify the resultant audio signal for application to a speaker 320.
- the video signal, CV which has a bandwidth of 4.2 MHz, is applied to an analog to digital converter (ADC) 322.
- the ADC 322 is responsive to a sampling clock signal CK, having a frequency of approximately 8.8 MHz to generate a sampled data signal representing the video signal CV. This clock frequency is 32/13 times the frequency, f c .
- the clock signal CK is developed by a clock signal generator 326 described below.
- the sampled data video signal provided by ADC 322 is applied to a burst gate detector 324.
- the detector 324 generates a burst gate signal, BG, which has pulses that coincide with the color reference burst signal in the horizontal line intervals of the video signal.
- the video signal, CV, provided by the band-pass filter and trap circuitry 316 is applied to a band-pass filter 325 which may, for example, remove any direct current (DC) bias from the burst signal.
- the filtered signal provided by the band-pass filter 325 and the burst gate signal BG are applied to the clock signal generator 326.
- FIG. 4 is a block diagram showing circuitry which may be used for the clock signal generator 326.
- the clock signal generator shown in FIG. 4 includes a phase-locked-loop (PLL) which comprises a gated phase comparator 410, a low-pass filter 412, a voltage controlled oscillator (VCO) 414 and a frequency divider 416.
- the phase comparator 410 compares an oscillatory signal provided by the frequency divider 416 to the video signal CV during the burst interval defined by the gating signal BG.
- a phase difference signal, generated by the phase comparator 410 is applied to the low-pass filter 412 which may, for example, integrate the phase difference signal to develop a frequency control signal for the VCO 414.
- the VCO 414 which has a free running frequency of approximately 32 f c , produces an oscillatory signal that is applied to the frequency divider circuitry 416.
- the circuitry 416 divides the frequency of the signal provided by the VCO 414 by 32 to produce a signal having a frequency of f c , the same frequency as the color synchronizing burst signal, for application to the phase comparator 410.
- the gain factors of the individual elements of the PLL are chosen, for example, to achieve a loop time constant of from 12 line periods to one field period.
- the signal provided by the VCO 414 which has a nominal frequency of 32 f c is applied to frequency dividing circuitry 418.
- the circuitry 418 divides the frequency of this signal by 13 to produce the signal CK having a frequency of (32/13) f c .
- the clock signal CK, the video signal CV and the burst gate signal BG are applied to circuitry which generates a phase alignment signal PA. This signal is used by the chrominance demodulator circuitry as explained below in reference to FIG. 5.
- the signal CV is applied to a first inverter, 422, which, during the burst interval, provides, for example, a square-wave output signal having pulses that have a predetermined phase relationship relative to the (B-Y) phase of the chrominance signal.
- This signal is inverted by a second inverter 424 and delayed by the signal propogation delay through the inverter 424.
- the burst gate signal, BG, and the output signals of the inverters 422 and 424 are applied to an AND gate 426.
- the AND gate 426 produces a signal which has short-duration pulses. This signal is delayed by a delay element 427 to provide a signal having pulses that correspond to the (B-Y) sampling phase.
- the signal provided by the delay element 427 is applied to the D input terminal of a flip-flop 420.
- the clock signal CK is applied to the clock input terminal of the flip-flop 420 and, through an inverter, 428, to the reset terminal, R, of the flip-flop.
- the output signal, PA, of the flip-flop 420 is a logic one for one-half of one period of the signal CK. This signal indicates that a sampling clock pulse at the (B-Y) phase of the chrominance signal has occurred.
- the digitized video signal provided by the ADC 322 and the clock signal CK are applied to a comb filter 328.
- the filter 328 which may be of conventional design, separates the video signal into a luminance signal, Y, and a chrominance signal, C.
- the signal Y is applied to a luminance signal processor 330 which may, for example, include circuitry for peaking the high frequency components of the luminance signal and for converting the digital luminance signal into an analog signal Y'.
- the signal Y' is applied to a conventional matrix circuit 332 which combines the signal Y' with color difference signals (R-Y)' and (B-Y)' to produce red, green and blue primary color signals (R, G and B respectively) for application to a display device 338.
- the (R-Y)' and (B-Y)' color difference signals are generated from the chrominance signal C by the chrominance signal demodulator 334 and the chrominance signal processor 336.
- FIG. 5 is a block diagram showing exemplary circuitry for the chrominance signal demodulator 334.
- the chrominance signal C is applied to the input port of a delay element 510, the output port of which is coupled to the input port of a delay element 512.
- Each of the delay elements 510 and 512 delays the samples applied to its input port by one period of the signal CK.
- the sample available at the output port of the delay element 510 is multiplied by the scale factors ⁇ and ⁇ in the respective sample scaling circuits 522 and 516.
- the sample applied to the input port of the delay element 510 is subtracted from the sample available at the output port of the delay element 512 by the subtracter 514.
- the difference sample generated by the subtracter 514 is multiplied by the scale factors ⁇ and ⁇ in the respective sample scaling circuits 524 and 518.
- the samples provided by the scaling circuits 516 and 518 are summed by an adder 520 to generate samples representing the (R-Y) color difference signal and the samples provided by the scaling circuits 522 and 524 are summed by the adder 526 to generate samples representing the baseband (B-Y) color difference signal.
- the scale factors ⁇ , ⁇ , ⁇ and ⁇ are provided by a coefficient read only memory (ROM) 528 in response to a five-bit control signal generated by a modulo 32 counter 530 and applied to the address input port of the ROM 528.
- ROM read only memory
- This control signal is set to zero by the phase alignment signal PA, which is applied to the reset input terminal of the counter 530, and is incremented by one for every pulse of the signal CK. Since the counter 530 is a modulo 32 counter, the control signal is reset to zero on the clock pulse following the value 31 even in the absence of a pulse of the signal PA. Accordingly, each of the scale factors provided by the ROM 528 changes in a cycle of 32 values as the address values provided by the counter 530 change from 0 to 31. Exemplary values of the scale factors ⁇ , ⁇ , ⁇ and ⁇ are listed in Table I.
- the (R-Y) and (B-Y) signals provided by the chrominance demodulator 334 are applied to a chrominance processor 336.
- the processor 336 may include, for example, auto-flesh correction circuitry and digital-to-analog converters which develop the analog color difference signals (R-Y)' and (B-Y)' for application to the matrix 332 as set forth above.
- the chrominance demodulator circuitry shown in FIG. 5 includes two FIR filters having transfer functions T.sub.(R-Y) and T.sub.(B-Y) which may be represented in Z-transform notation as:
- Each of these filters develops an estimate of the values of its output color difference signal samples from the values of three consecutive chrominance samples.
- the chrominance signal is a sampled data signal having a sampling frequency of (32/13)f c .
- the phase angle between successive samples is 13 ⁇ /16 and the phase of a sample with respect to a predetermined initial phase repeats every 32 samples (13 cycles of the subcarrier signal). If the initial phase is the (B-Y) phase, the value of any chrominance sample C m may be described by the equation (4) which is derived from the equation (1) .
- n is the number of samples between the mth sample and the last (B-Y) sample
- ⁇ is 13 ⁇ /16
- (B-Y) m and (R-Y) m are the values of the (B-Y) and (R-Y) color difference signal components of the chrominance sample C m .
- the chrominance demodulator circuitry shown in FIG. 5 implements the equations (5) and (6).
- the scale factors ⁇ , ⁇ , ⁇ and ⁇ are defined by the equations:
- the chrominance signal demodulator described above may be used with chrominance signals having sampling frequencies of (N/D)f c where N and D have no other restrictions than that both are integers.
- the coefficients ⁇ , ⁇ , ⁇ and ⁇ have values determined by the equations 7-10 and the number of values in the cycle is the number of samples between two sampling clock pulses that have the same sampling phase value.
Abstract
Description
C.sub.s =(B-Y) cos φ+(R-Y) sin φ. (1)
TABLE I ______________________________________ Counter Value α β γ δ ______________________________________ 0 1 0 0 -0.90 1 -0.83 0.50 0.56 0.75 2 0.38 -0.83 -0.92 -0.34 3 0.20 0.88 0.98 -0.18 4 -0.71 -0.64 -0.71 0.64 5 0.98 0.18 0.20 -0.88 6 -0.92 0.34 0.38 0.83 7 0.56 -0.75 -0.83 -0.50 8 0 0.90 1 0 9 -0.56 -0.75 -0.83 0.50 10 0.92 0.34 0.38 -0.83 11 -0.98 0.18 0.20 0.88 12 0.71 -0.64 -0.71 -0.64 13 -0.20 0.88 0.98 0.18 14 -0.38 -0.83 -0.92 0.34 15 0.83 0.50 0.56 -0.75 16 -1 0 0 0.9 17 0.83 -0.50 -0.56 -0.75 18 -0.38 0.83 0.92 0.34 19 -0.20 -0.88 -0.98 0.18 20 0.71 0.64 0.71 -0.64 21 -0.98 -0.18 -0.20 0.88 22 0.92 -0.34 -0.38 - 0.83 23 -0.56 0.75 0.83 0.50 24 0 -0.90 -1 0 25 0.56 0.75 0.83 -0.50 26 -0.92 -0.34 -0.38 0.83 27 0.98 -0.18 -0.20 -0.88 28 -0.71 0.64 0.71 0.64 29 0.20 -0.88 -0.98 -0.18 30 0.38 0.83 0.92 -0.34 31 -0.83 -0.50 -0.56 0.75 ______________________________________
T.sub.(B-Y) =-β+δZ.sup.-1 +βZ.sup.-2 (2)
T.sub.(R-Y) =-δ+γZ.sup.-1 +δZ.sup.-2. (3)
C.sub.m =(B-Y).sub.m cos nΔ+(R-Y).sub.m sin nΔ (4)
(B-Y).sub.m =1/2(sin nΔ/sin Δ)(C.sub.m-1 -C.sub.m+1)+cos nΔC.sub.m (5)
(R-Y).sub.m =-1/2(cos nΔ/sin Δ)(C.sub.m-1 -C.sub.m+1)+sin nΔC.sub.m. (6)
α=cos nΔ (7)
β=1/2(sin nΔ/sin Δ) (8)
γ=sin nΔ (9)
δ=-1/2(cos nΔ/sin Δ) (10)
Claims (10)
α=cos (nΔ)
β=1/2(sin (nΔ))/sin (Δ)
T=-β+αZ.sup.-1 +βZ.sup.-2
α=cos (nΔ)
β=1/2(sin (nΔ))/sin (Δ)
T.sub.F =δ+γZ.sup.-1 +δZ.sup.-2
γ=sin (nΔ)
δ=-1/2(cos (nΔ))/sin (Δ).
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US06/911,424 US4745463A (en) | 1986-09-25 | 1986-09-25 | Generalized chrominance signal demodulator for a sampled data television signal processing system |
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Cited By (34)
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---|---|---|---|---|
US4890158A (en) * | 1988-09-15 | 1989-12-26 | Tektronix, Inc. | Recursive noise reduction filter for video test apparatus |
EP0364225A1 (en) * | 1988-10-12 | 1990-04-18 | Canon Kabushiki Kaisha | Color signal processing apparatus |
US4959718A (en) * | 1982-03-31 | 1990-09-25 | Ampex Corporation | Video device synchronization system |
US5132784A (en) * | 1991-05-20 | 1992-07-21 | Thomson Consumer Electronics, Inc. | Comb filter-burst locked clock circuitry |
US5315379A (en) * | 1989-05-15 | 1994-05-24 | Canon Kasbushiki Kaisha | Apparatus for the demodulation of a carrier chrominance signal into color difference signals |
US5555197A (en) * | 1993-04-12 | 1996-09-10 | Matsusita Electric Industrial Co., Ltd. | Video signal processor and method for processing a scanning line regardless of the synchronizing signal |
US5751375A (en) * | 1993-04-12 | 1998-05-12 | Matsushita Electric Industrial Co., Ltd. | Processing of pixel data at an operating frequency higher than the sampling rate of the input signal |
US6049706A (en) | 1998-10-21 | 2000-04-11 | Parkervision, Inc. | Integrated frequency translation and selectivity |
US6052157A (en) * | 1997-08-04 | 2000-04-18 | Innovision Labs | System and method for separating chrominance and luminance components of a color television system |
US6061551A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for down-converting electromagnetic signals |
US6061555A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for ensuring reception of a communications signal |
US6064446A (en) * | 1997-04-09 | 2000-05-16 | U.S. Philips Corporation | Color decoding |
US6091940A (en) | 1998-10-21 | 2000-07-18 | Parkervision, Inc. | Method and system for frequency up-conversion |
US6370371B1 (en) | 1998-10-21 | 2002-04-09 | Parkervision, Inc. | Applications of universal frequency translation |
US6542722B1 (en) | 1998-10-21 | 2003-04-01 | Parkervision, Inc. | Method and system for frequency up-conversion with variety of transmitter configurations |
US6560301B1 (en) | 1998-10-21 | 2003-05-06 | Parkervision, Inc. | Integrated frequency translation and selectivity with a variety of filter embodiments |
US6694128B1 (en) | 1998-08-18 | 2004-02-17 | Parkervision, Inc. | Frequency synthesizer using universal frequency translation technology |
US6704549B1 (en) | 1999-03-03 | 2004-03-09 | Parkvision, Inc. | Multi-mode, multi-band communication system |
US6704558B1 (en) | 1999-01-22 | 2004-03-09 | Parkervision, Inc. | Image-reject down-converter and embodiments thereof, such as the family radio service |
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US20090221257A1 (en) * | 1998-10-21 | 2009-09-03 | Parkervision, Inc. | Method and System For Down-Converting An Electromagnetic Signal, And Transforms For Same, And Aperture Relationships |
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US4959718A (en) * | 1982-03-31 | 1990-09-25 | Ampex Corporation | Video device synchronization system |
US4890158A (en) * | 1988-09-15 | 1989-12-26 | Tektronix, Inc. | Recursive noise reduction filter for video test apparatus |
EP0364225A1 (en) * | 1988-10-12 | 1990-04-18 | Canon Kabushiki Kaisha | Color signal processing apparatus |
US5315379A (en) * | 1989-05-15 | 1994-05-24 | Canon Kasbushiki Kaisha | Apparatus for the demodulation of a carrier chrominance signal into color difference signals |
US5132784A (en) * | 1991-05-20 | 1992-07-21 | Thomson Consumer Electronics, Inc. | Comb filter-burst locked clock circuitry |
US5555197A (en) * | 1993-04-12 | 1996-09-10 | Matsusita Electric Industrial Co., Ltd. | Video signal processor and method for processing a scanning line regardless of the synchronizing signal |
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US6064446A (en) * | 1997-04-09 | 2000-05-16 | U.S. Philips Corporation | Color decoding |
US6052157A (en) * | 1997-08-04 | 2000-04-18 | Innovision Labs | System and method for separating chrominance and luminance components of a color television system |
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