|Veröffentlichungsdatum||30. Mai 1989|
|Eingetragen||24. Sept. 1987|
|Prioritätsdatum||25. Sept. 1986|
|Auch veröffentlicht unter||DE3731865A1, DE3731865C2|
|Veröffentlichungsnummer||07100742, 100742, US 4835595 A, US 4835595A, US-A-4835595, US4835595 A, US4835595A|
|Erfinder||Shigeru Oho, Kazuji Yamada, Shigeki Tsuchitani|
|Ursprünglich Bevollmächtigter||Hitachi, Ltd.|
|Zitat exportieren||BiBTeX, EndNote, RefMan|
|Patentzitate (7), Nichtpatentzitate (2), Referenziert von (21), Klassifizierungen (30), Juristische Ereignisse (6)|
|Externe Links: USPTO, USPTO-Zuordnung, Espacenet|
The present invention relates to interconnections for semiconductor integrated circuits, and more particularly to optical interconnections which cause a multiplicity of elements in semiconductor integrated circuits to be activated or operated.
In the hitherto known semiconductor integrated circuits, wirings or interconnections for transferring clocks, timing signals or the like are realized by diffused resistive layers, metal layers (made of, for example, aluminum) or the like formed on a semiconductor chip. With such electrical interconnections, however, delays of signal transfer take place due to electrostatic capacitances associated with the electrical interconnections, thereby resulting in a hindrance to improvement in the operation speed of an integrated circuit.
In order to solve such a problem, an optical interconnection system using light for signal transfer has been proposed, as disclosed by, for example, J. W. Goodman et al, "Optical Interconnections for VLSI Systems", Proc. of the IEEE, Vol. 72, No. 7, pp. 850-866, July 1984. In the optical interconnection system, an optical signal is transferred through the propagation in a free space or via optical fibers or optical waveguides, thereby allowing the signal transfer at a very high speed which is equal to the propagation speed of light in such a medium.
FIG. 1 shows an example of the optical interconnection system, disclosed by the above-mentioned Goodman et al's article, in which light propagating in a free space is used. Referring to the figure, light as an optical signal emitted from a light source 110 is collimated by a lens 130 to irradiate a semiconductor integrated circuit chip 140. Light receiving elements 120 to 125 formed in the integrated circuit chip 140 receive the optical signals to convert them into electrical signals. If such optical signals are clock signals for logic circuits formed in the integrated circuit chip, the timings of electric clock signals reproduced or regenerated at any points on the chip would completely coincide with each other. This provides an advantage that the occurrence of a timing jitter resulting from the propagation delays which may take place in the case of electrical interconnections can be prevented.
In the above described conventional example of the optical interconnection system, however, since the entire upper surfaces of the semiconductor integrated circuit is uniformly irradiated, some photoelectrons are generated by optical excitation in the whole integrated circuit including the light receiving elements. Such generated photoelectrons can have an adverse influence, large and small, on the characteristics of transistors or diodes included in the integrated circuit, resulting in inferior operating characteristics of the integrated circuit and/or erroneous operation thereof.
As to the light illuminating the upper surface of the semiconductor integrated circuit, the effective light portion or a light portion incident on the light receiving elements 120 to 125 is extremely small since the areas of the light receiving elements are limited because of improvement of the integration degree. Therefore, the efficiency of utilization of light is poor.
Further, the above-described conventional example of the optical interconnection system assumes simultaneous activation of all the light receiving elements. Namely, no consideration is given with respect to selective activation of the light receiving elements.
An object of the present invention is to provide an optical interconnection in a semiconductor integrated circuit in which a reduction in the quality in the quality of the characteristics of the integrated circuit and/or an erroneous operation thereof do not take place.
Another object of the present invention is to provide an optical interconnection in a semiconductor integrated circuit in which the efficiency of utilization of light is improved.
A further object of the present invention is to provide an optical interconnection in a semiconductor integrated circuit in which light receiving elements can be selectively activated by use of simple means.
A still further object of the present invention is to provide an optical interconnection in a semiconductor integrated circuit in which the efficiency of utilization of light is improved and light receiving elements can be selectively activated by use of simple means.
To that end, in the present invention, a portion of the surface of the semiconductor integrated circuit excepting the upper surface of a light receiving element is coated with an opaque layer while the upper surface of the light receiving element is provided with a transparent layer. The transparent layer may be provided with a lens function to effectively utilize incident light. The transparent layer may have selectivity to wavelengths of light to selectively activate a plurality of light receiving elements. In that case, an optical pulse signal irradiating the light receiving elements has a plurality of corresponding wavelengths.
FIG. 1 is a perspective view of an example of the conventional optical interconnection in a semiconductor integrated circuit;
FIG. 2 shows an embodiment of the present invention with respect to one light receiving element or photo-electric conversion element;
FIG. 3 shows an equivalent circuit of the embodiment shown in FIG. 2;
FIG. 4 is a general illustration of the embodiment of the present invention;
FIG. 5 shows another embodiment of the present invention; and
FIG. 6 shows a further embodiment of the present invention.
An optical interconnection in a semiconductor integrated circuit of the present invention will now be described in detail by virtue of embodiments shown in the accompanying drawings.
An embodiment of the present invention is shown in FIG. 2 which is a cross section of a part of a semiconductor IC (integrated circuit) embodying the present invention. In FIG. 2, a reference numeral 1 generally designates a semiconductor IC chip. The chip 1 is fabricated by forming buried layers 50 and 55 of p-type conductivity in a semiconductor substrate (silicon) 40 of n-type conductivity and thereafter forming a photodiode 10, a resistor 20 and a transistor 30 in the buried lyers. The photodiode 10 is a p-i-n photodiode which includes an n-type layer 52, an intrinsic layer 51 and the p-type layer 50. A p-type layer 53 is a diffused resistor which forms the resistor 20 (see FIG. 3) together with an n-type layer 54. The transistor 30 is an N-channel MOS transistor which includes n-type source and drain layers 57 and 56 formed in the p-type buried layer 55, a gate insulating film 61, and a gate electrode 71. Reference numeral 60 designates a field oxide film, and numerals 70 and 72 to 77 designate contacts for wiring. Though for better understanding the wiring is shown in FIG. 2 in a form drawn out to the exterior, the wiring is actually provided by printed wiring or interconnections disposed on the field oxide film 60.
The chip 1 thus prepared is coated with an opaque insulating resin layer 200. More especially, the opaque resin layer 200 is formed by applying a mixture of silicone rubber, polyimide or epoxy with titanic white (titanium oxide), bengara or carbon in a form of thin film on the IC chip 1 by means of a spinner. Next, an opening 100 is provided in the opaque resin layer. The opening 100 is positioned just above the photodiode 10 and its size is larger than a working or operating area of the photodiode. The opening 100 may be formed by masking the opaque resin layer excepting a portion thereof where the opening is to be provided and then etching the exposed portion.
Thereafter, a filling material 210 made of a transparent resin is provided in the opening 100. The transparent resin layer 210 may be formed by applying silicone rubber, polyimide or epoxy into the opening 100 and onto the upper surface of the opaque resin layer by means of a spinner and etching away the resulting structure by a predetermined thickness. Next, a Fresnel lens 220 is formed on the surface of the filling material 210 by pressing. The lens 220 has a function of converging or collecting light incident from the opening larger than the working area of the photodiode into the working area of the photodiode. A spherical lens, a refractive index-distributed lens or the like may be used in place of the Fresnel lens. The transparent layer 210 may be a glass layer formed by sputtering. The thickness of each of the opaque layer 200 and the transparent layer 210 may be 2 to 3 microns.
In FIG. 2, a reference numeral 6 designates an electrical clock signal generating circuit for generating an electrical clock signal, and numeral 5 designates an optical clock signal generator means for generating an optical clock signal in response to the electrical clock signal. The optical clock signal is delivered in the form of a change in strength of light, the form of ON/OFF of light, or the like and is ultimately used as an electrical signal for operating a logic circuit section 300 (see FIG. 3). Although the clock signal generating circuit 6 is illustrated by way of example, other signals may be used with like meritorious effects. That is, the signal generating circuit 6 may be a pulse generator means for generating an electrical pulse signal. By converting the electrical pulse into an optical pulse signal the present invention is applicable to advantages.
Next, the operation of the embodiment shown in FIG. 2 will be explained referring to FIG. 3 which illustrates an equivalent circuit of the structure shown in FIG. 2. The optical clock signal emitted from the optical clock signal generator 5 irradiates the photodiode 10 on the IC chip 1. At this time, the light incident onto the photodiode passes through the transparent layer provided in the opening 100 and is converged by a lens action of the transparent layer to irradiate the working area of the photodiode 10. By irradiation with the light, the photodiode 10 becomes conductive so that a current from a power source +VCC (e.g. 5 V) flows through the resistor 20 (e.g. 1 KΩ) across which a voltage is developed. This voltage is amplified by the MOS transistor 30 and is supplied as an electrical clock signal to the logic circuit section 300. Alternatively, in the case where the signal generating circuit 6 is formed of a usual pulse generator but not a clock signal generator explained with reference to FIG. 2, an electrical pulse signal generated by the pulse generator 6 is converted into an optical pulse signal by the circuit 5. The photodiode 10 is driven by the optical pulse signal.
Though the above explanation has been made in conjunction with a single logic element which includes one photodiode 10, one resistor 20 and one MOS transistor 30, a multiplicity of such logic elements are actually formed in the IC chip. In the present embodiment, the multiplicity of logic elements are simultaneously activated by a single optical clock signal generating means. This situation is illustrated in FIG. 4. Referring to FIG. 4, the IC chip 1 includes the multiplicity of logic circuits. Reference numeral 2 represents a lower mold, numeral 3 lead terminals, and numeral 4 an upper mold. Inside the upper mold 4 is mounted the optical clock signal generator 5 such as a light emitting diode for receiving an electrical clock signal from the electrical clock signal generating circuit 6 to generate an optical clock signal. The optical signal or light emitted from the light emitting diode 5 irradiates the whole of the chip 1. Accordingly, the photodiodes on the chip 1 are all activated concurrently by one clock signal. As a result, the timings of activation of all the photodiodes coincide with each other so that any timing jitter due to delays in transfer of clock signals is not exhibited.
It is apparent from FIG. 2 that since those portions of the structure excepting the upper surfaces of the photodiodes are coated with the opaque resin layer 200, the generation of photoelectrons is inhibited except for the sites of the photodiodes, thereby preventing any reduction in the operating characteristics of the integrated circuit and/or erroneous operation thereof.
As has been described, the size of the opening 100 is made larger than the working area of the photodiode, the transparent layer is provided in the opening 100, and the transparent layer has a lens function. Therefore, light incident from the opening which is larger than the working area of the photodiode can be effectively utilized though only light irradiated onto an area corresponding to the working area of the photodiode is otherwise effective. In other words, light from the large opening 100 is converged into the working area of the photodiode by means of the lens provided at the opening, thereby enhancing the efficiency of utilization of incident light.
Though in the foregoing embodiment the light emitting diode (LED) 5 is mounted inside the upper mold 4 so that light emitted from the LED is used as a signal light, a construction may be employed in which a window made of a transparent material such as glass is provided in the upper mold 4 so that a signal light is introduced from the window to irradiate the internal chip 1.
FIG. 5 shows another embodiment of the present invention in which transparent layers provided in the openings 100 have different selectivities to wavelengths of light. More particularly, photodiodes on the IC chip 1 are grouped into a plurality of sets and transparent layers 230 provided in the openings 100 above the photodiodes in one set (only a photodiode 10a is shown) selectively transmit light having a wavelength λ1 while transparent layers 240 provided in the openings 100 above the photodiodes in another set (only a photodiode 10b is shown) selectively transmit light having a wavelength λ2. The number of the diode sets can be increased, as required. Reference numeral 80 designates a transparent resin layer.
Optical clock signal generating means provided above the IC chip 1 is divided into two sections 5a and 5b one of which emits the light of wavelength λ1 and the other of which emits the light of wavelength λ2. Therefore, by driving the sections 5a and 5b by clock signals having different phases, respectively, the plurality of photodiodes on the IC chip can be driven by multi-phase clock signals. The photodiodes belonging to each set are simultaneously activated, like the case of the embodiment shown in FIG. 2, so that no timing jitter takes place. Each of the transparent layers having different wavelength-selectivities can be formed by use of gelatin added with a dye having a predetermined wavelength-selectivity.
FIG. 6 shows a further embodiment of the present invention which is similar to the embodiment of FIG. 5 but aims to improve the efficiency of utilization of light. The size of the opening 100 is made larger than the working area of the photodiode. Transparent layers 250 and 260 filled in the openings 100 are provided with different wavelength-selectivities. Each transparent layer is further provided with a lens action by a Fresnel lens 220 or the like. As a result, light incident from the opening larger than the working area of the photodiode is converged into that working area.
The present invention has been disclosed with respect to the specific embodiments, but the invention is not limited to those embodiments.
While the invention has been described in terms of its preferred embodiments, numerous modifications and/or obvious variations may be made thereto without departing from the spirit and scope of the invention. It is intended that all such modifications and variations fall within the scope of the appended claims.
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|JPS5917286A *||Titel nicht verfügbar|
|JPS60153184A *||Titel nicht verfügbar|
|1||Goodman et al., "Optical Interconnections for VLSI Systems", Proceedings of the IEEE, vol. 72, No. 7, Jul. 1984, pp. 850-865.|
|2||*||Goodman et al., Optical Interconnections for VLSI Systems , Proceedings of the IEEE, vol. 72, No. 7, Jul. 1984, pp. 850 865.|
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|US-Klassifikation||250/551, 257/440, 250/227.23, 257/461, 257/E27.128, 250/332, 257/E31.122, 250/370.08, 257/458, 250/370.14, 257/435, 257/432, 257/E31.128|
|Internationale Klassifikation||H01L27/15, H01L31/12, H01L27/14, H01L31/10, H01L31/0232, H04B10/00, H01L27/144, H01L31/0216|
|Unternehmensklassifikation||H01L27/1443, H01L31/02164, H01L31/0232, H01L2924/16152, H01L2224/48247, H01L2224/48091|
|Europäische Klassifikation||H01L31/0232, H01L27/144B, H01L31/0216B2B|
|16. Nov. 1987||AS||Assignment|
Owner name: HITACHI, LTD., A CORP. OF JAPAN,JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHO, SHIGERU;YAMADA, KAZUJI;TSUCHITANI, SHIGEKI;REEL/FRAME:004784/0810
Effective date: 19871012
|28. Sept. 1992||FPAY||Fee payment|
Year of fee payment: 4
|30. Sept. 1996||FPAY||Fee payment|
Year of fee payment: 8
|19. Dez. 2000||REMI||Maintenance fee reminder mailed|
|27. Mai 2001||LAPS||Lapse for failure to pay maintenance fees|
|31. Juli 2001||FP||Expired due to failure to pay maintenance fee|
Effective date: 20010530