US4878101A - Single transistor cell for electrically-erasable programmable read-only memory and array thereof - Google Patents
Single transistor cell for electrically-erasable programmable read-only memory and array thereof Download PDFInfo
- Publication number
- US4878101A US4878101A US07/947,212 US94721286A US4878101A US 4878101 A US4878101 A US 4878101A US 94721286 A US94721286 A US 94721286A US 4878101 A US4878101 A US 4878101A
- Authority
- US
- United States
- Prior art keywords
- erase
- array
- eeprom
- cell
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title description 2
- 230000005641 tunneling Effects 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 7
- 230000007246 mechanism Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 238000003491 array Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- PWPJGUXAGUPAHP-UHFFFAOYSA-N lufenuron Chemical compound C1=C(Cl)C(OC(F)(F)C(C(F)(F)F)F)=CC(Cl)=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F PWPJGUXAGUPAHP-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Definitions
- the present invention relates, in general, to electrically-erasable, programmable read-only memories (EEPROM's). More particularly, the invention relates to a single transistor cell for EEPROM's and to an array of such cells forming an EEPROM.
- EEPROM electrically-erasable, programmable read-only memories
- An EEPROM cell varies the charge stored on a floating gate in order to vary the threshold voltage, V T , of a floating gate-type MOS transistor comprising a source, a drain, the floating gate and a control gate.
- V T threshold voltage
- an EEPROM cell is said to be “erased” when the V T of the transistor is less than some predetermined switch point voltage, V TSP .
- the cell is said to be "programmed” when the V T of the cell is greater than V TSP .
- V TSP is chosen to be less than the positive supply voltage V DD in static arrays and is approximately equal to V DD in dynamic arrays.
- EEPROM Nearly every commercially successful EEPROM uses at least two transistors per cell.
- a series select transistor is present in each cell to alleviate the problem of read errors caused by over-erasure. Because the erasure process is not self-limiting, it is likely that too much negative charge will be removed from (or positive charge added to) the floating gate when the cell is erased, rendering the V T of the transistor negative (in other words, making it a depletion-mode device). Without series select transistors used for read access, such depletion-mode devices cause read errors when any other cell on the shared bit-line is accessed.
- U.S. Pat. No. 4,451,905 discloses an EEPROM cell and array using a single transistor design.
- the approach of the '905 patent is to add extra decoders and an extra (-5V) power supply outside of the array itself to ensure that read errors are avoided. This saves area in the array itself, but may require just as much added area in the extra decoders and power supply.
- U.S. Pat. No. 4,317,272 discloses a two transistor EEPROM cell in which the two transistors are, to the greatest extent possible, merged together. This saves a certain amount of area, but is still limited to a two transistor design.
- U.S. Pat. No. 4,486,769 discloses what is apparently a single transistor EEPROM cell design. However, a complex triple poly (three layers of polysilicon) process, an additional bias electrode and four connections to each cell (as opposed to the more conventional three) are required by this design. No mention of a solution to the over-erasure problem is made in the '769 patent.
- Yet a further object of the present invention is to provide an improved EEPROM array with a convenient byte-at-a-time program and erase mechanism.
- an EEPROM cell comprising a semiconductor body predominantly of a first conductivity type; source and drain regions of a second conductivity type at a first face of said body, the source and drain regions being separated by a channel region of said first conductivity type; a floating gate formed of patterned conductive material overlying and isolated from said semiconductor body, the floating gate overlying said channel region; tunnel means for selectively providing a conduction path between said source region and said floating gate, said tunnel means being partially coextensive with said channel region; and a control gate formed of patterned conductive material overlying and isolated from said semiconductor body and said floating gate, the floating gate and the control gate being co-extensive over the channel region.
- FIG. 1 is a plan view illustrating the layout of a single transistor EEPROM cell and a portion of an array thereof according to one aspect of the present invention
- FIG. 2 is a cross-sectional view, taken along the indicated plane, of the device of FIG. 1;
- FIG. 3 is a cross-sectional view, taken along the indicated plane, of the device of FIG. 1;
- FIG. 4 is a simplified schematic illustration of an EEPROM according to one aspect of the present invention.
- FIG. 5 is a detailed schematic illustration of a portion of an EEPROM array according to one aspect of the present invention.
- FIGS. 6A-6C are flow charts illustrating the operation of an EEPROM array according to one aspect of the present invention.
- N-channel EEPROM cell and array The following description involves the structure and function of an N-channel EEPROM cell and array. That is, the structures are fabricated in a semiconductor substrate which is of predominantly P-type conductivity with N-type regions therein forming the source and drain regions. Those skilled in the art will recognize that while this is, by far, the most common choice for EEPROM's, it is also possible to reverse the conductivities and fabricate a P-channel EEPROM array.
- FIGS. 1-3 illustrate, in various views as set forth above, the layout and structure of an EEPROM cell according to one aspect of the present invention.
- FIG. 1 is a conventional depiction of the geometric shapes which comprise the outlines of the various masks used to fabricate the device according to standard semiconductor industry practice.
- FIG. 1 actually illustrates the layout of a portion of an EEPROM array comprising portions of two rows 10 and 11 thereof.
- the portions of rows 10 and 11 which are illustrated each comprise one byte (eight bits) of storage capacity. Since the two bytes are identical, only the byte along row 10 will be described in detail.
- the illustrated portion of row 10 comprises eight single transistor EEPROM cells 12a-12h (cells 12c-12g are not shown) and one erase select transistor 13.
- First outline 14 defines the "active area" of the 18 transistors which comprise the two illustrated bytes.
- the surface of a P-type semiconductor substrate 9 outside of outline 14 is covered with a relatively thick (thousands of Angstroms) field oxide 30.
- common practice includes the formation of relatively heavily doped channel stop regions underlying all or part of field oxide 30.
- the surface inside outline 14 is covered by a relatively thin (hundreds of Angstroms) gate oxide 31, except for the surface inside outlines 15, which is exposed to allow contact with a metal interconnection line, and the surface inside outlines 16, which is covered by a very thin (on the order of 100 Angstroms) tunneling oxide layer 32.
- the formation of these oxide layers of varying thickness is performed according to techniques well known in the semiconductor industry.
- outline 14 defines the extent of the N-type diffusions or implants which form the sources 33 and drains 34 of each of the transistors.
- source 33 is shared between rows 10 and 11. Because source 33 is used for erase selection and because byte-at-a-time erasure is desired, source 33 is shared only by the two illustrated bytes, not by the entirety of rows 10 and 11. All of the area inside outline 14 is of N-type conductivity except for channel regions 38, which are defined as the areas of substrate 9 underlying the intersections of outlines 12 and 17. Alternatively, it is possible that some portions of the active region, particularly surrounding drains 34, may be lightly doped with a P-type dopant, typically by means of ion implantation, to enhance the programming mechanism.
- Outlines 18 define the extent of floating gates 40. In fact, outlines 18 define the extent of the floating gates after a self-aligned etch which patterns the overlying control gates has been performed, not the actual mask which initially patterns the conductive material which forms the floating gates.
- Floating gates 40 overlie channel regions 38 of all transistors except erase select transistor 13.
- Floating gates 40 are fabricated according to familiar techniques by depositing and patterning a first conductive layer, most commonly a doped polysilicon layer, overlying oxides 30, 31 and 32. Stored charge on floating gates 40 is the source of the electric fields which alter the conductivity of channel regions 38 thus altering the threshold voltages of the transitors which comprise cells 12a-12h.
- Dielectric material 45 serves to electrically isolate floating gates 40 from any overlying conductive material.
- Dielectric 45 may be a deposited dielectric, such as CVD oxide or an oxide-nitride-oxide (ONO) multi-layer structure. It is also possible that dielectric 45 can be formed by thermally oxidizing the polysilicon of floating gates 40.
- Outline 17 defines the pattern of a second layer of conductive material, commonly another layer of doped polysilicon, which overlies dielectric material 45 and forms control gates 46. Outline 17 may also be referred to as defining the word lines which extend across the entire array and define the rows thereof.
- Control gates 46 serve to influence the potential of floating gates 40, respectively, during the programming and erasing of the cells and as the select gates during the reading of the cell. In the case of erase select transistor 13, control gate 46 is the sole gate of the transistor. The portion of control gates 46 which overlie floating gates 40 are co-extensive therewith. That is, there is no portion of channel regions 38 which is not overlain by both a floating gate and a control gate.
- Dielectric layer 48 serves to electrically isolate control gates 46 from overlying conductive layers such as metal lines and, of course, is opened where electrical contact thereto is required.
- Each single transistor EEPROM cell 12a-12h as described above may be characterized as having "merged" tunneling and channel regions. That is, instead of having the floating gates of each cell extend outside of the immediate vicinity of the channel region to a separate area in which the tunneling mechanism is provided, the tunnel oxide region and channel region are partially merged. This layout conserves area, making the cell and the array smaller.
- FIG. 4 depicts, in greatly simplified block diagram form, an EEPROM 50.
- EEPROM 50 is a hypothetical device which accepts a predetermined number of address bits, a predetermined number of data bits, three control signals (READ, PROGRAM and ERASE) and three power supply voltages (V DD , V PP and V SS ) as inputs and provides a predetermined number of data bits as outputs.
- V DD is approximately +5V
- V PP is approximately +12V to +20V
- V SS is ground, or 0V.
- EEPROM 50 comprises address decode and control logic 51, an array 52 of EEPROM cells, a plurality of sense amplifiers 53, a plurality of word lines 54 which couple control logic 51 to array 52, a plurality of erase lines 55 which couple control logic 51 to array 52 and a plurality of bit lines 56 which couple array 52 to control logic 51 and to sense amplifiers 53.
- Addresses are decoded in logic 51 to provide the identity of the particular word line being addressed (X-decoded) and to provide the identity of the particular set of bit lines (or column) being addressed (Y-decoded).
- the decoding is followed by applying signals to array 52 over word lines 54, erase lines 55 and/or bit lines 56 as are appropriate to the operation specified by the control signals applied to logic 51.
- FIG. 5 illustrates portions of a pair of rows (row i and row i+1) of cell array 52 of FIG. 5.
- FIG. 5 illustrates a preferred embodiment of the present invention in which the cells are organized so as to be conveniently erased one byte at a time. This byte-erasure scheme provides the ability to alter parameters stored in an EEPROM without suffering the overhead involved in reading, then re-programming an entire row or even larger unit of the array. Activities such as changing an account balance stored in an EEPROM on a "smartcard" are examples of the need for such a scheme.
- FIG. 5 illustrates just one byte (comprising column k of array 52) along each of rows i and i+1.
- each row extends across the entire width of array 52 and has more than one byte along its length.
- the interconnections to row i, column k of the array are word line i, erase line j and bit lines 0-7.
- Erase line j in the preferred embodiment, is Y-decoded along with bit lines 0-7, and is shared by all rows in column k.
- Word lines i and i+1 extend across the entire width of the array and are shared by all the columns thereof.
- Each of the eight cells comprising row i, column k of the array comprises a floating gate-type N-channel transistor as is described above.
- Each transistor comprises a control gate 60, a drain 61, a source 62 and a floating gate 64.
- Control gates 60 are each connected to word line i
- drains 61 are each connected to one of bit lines 0-7, respectively
- sources 62 are each connected to a common source/erase control line 63.
- each floating gate 64 is selectively coupled, during erase cycles, by tunneling to common source/erase control line 63.
- Common source/erase control line 63 is shared by each cell in column k along rows i and i+1, but does not extend into column k+1.
- common source/erase control line 63 may be extended across the entire width of the array and only one erase line would be required.
- Common source/erase control line 63 is connected to a source of an N-channel, enhancement-type erase select transistor 65.
- the gate of transistor 65 is connected to word line i and the drain is connected to erase line j.
- the circuit of FIG. 5 corresponds to the layout of FIG. 1.
- FIGS. 6A, 6B and 6C are flow charts illustrating the read, program and erase sequences, respectively.
- the sequences illustrated may not be as linear as is implied by a flow chart representation. In other words, events represented as occuring sequentially may, in fact, occur simultaneously.
- logic 51 responds to the assertion of the READ control signal by decoding the address on the address bus. This results in the identification of the word line, i, which corresponds to the row of the array to be read and of the particular set of bit lines 0-7 comprising the column, k, which is to be read.
- the word line i
- all bit lines have been precharged to a voltage level of approximately V DD prior to the read cycle.
- the selected word line, i is set to approximately V DD and all non-selected word lines are set to V SS . Static operation, in which no precharging of the selected bit lines is performed, is also possible.
- V DD both raises the control gates of each of the cells on the word line to V DD and "turns on" the N-channel erase select transistor (e.g. 65 of FIG. 5) through which each cell's source 62 is coupled to erase line j.
- All erase lines are at V SS , providing a path to ground for the charge on the bit lines. Once the path to ground has been provided, those cells which have been previously erased, thus lowering their V T 's to a value below V TSP , will discharge their associated bit lines, which is sensed by the associated sense amplifier. Cells which have been previously programmed, thus having V T 's above V DD , will not significantly discharge their associated bit lines.
- the read configuration is held for a time predetermined to allow accurate reading of the array, then the read sequence is terminated.
- FIG. 6B illustrates a program sequence for the above-described EEPROM.
- Logic 51 responds to the assertion of the PROGRAM control signal by first decoding the address to determine the identity of the selected row and column, i and k, respectively. Since a data word to be stored in row i of array 52 will typically be a combination of high and low logic values, programming must be responsive to the value of the data word received to determine which bits within the selected column are to be programmed. In the case of pre-programming preparatory to erasing (see below) all bits within the selected column will be programmed. Otherwise, data from the data bus will be used to determined which bits are to be programmed and which are not. For this reason, FIG. 6B indicates that the "selected" bit lines are set to approximately V PP . This indicates that the bit lines must both be selected by the Y-decode process and must correspond to a bit in the input data word with the appropriate value.
- first bit line O is set to approximately V PP .
- the selected word line, i is set to approximately V PP .
- the actual voltage applied may be slightly lower than V PP due to threshold voltage drops through the intervening circuits. It is advantageous to design the circuits such that the actual voltage applied to the bit line is lower than the actual voltage applied to the control gate, or word line. This provides the proper electric field to cause electrons to move toward the floating gate.
- Non-selected word lines are set to V SS . All erase lines are set to V SS , thus creating a large voltage drop from drain to source in the cell being programmed. This condition, combined with the large positive voltage on the selected control gate, serves to inject electrons into the selected floating gate, leaving it with a more negative charge and raising the V T of the cell.
- a normal program sequence will be terminated when the V T 's of the target cells are above V TSP , but usually before the V T 's reach the point at which charge build-up on the floating gates prevents the injection of more charge. This is done to make programming time as short as is reasonably possible.
- FIG. 6C illustrates an erase sequence for the above-described array.
- This erasure scheme is the subject of claims contained in co-pending U.S. patent application Ser. No. 947,213, which is assigned to the assignee of the present invention.
- logic 51 In response to the assertion of the ERASE control signal, logic 51 first decodes the address.
- an erase line selection must be made in addition to the usual row and column selections. This requires no additional logic since the erase line selection is performed by the same logic (the Y-decoder) as the column selection. This selection is avoided if only row-at-a-time erasing is performed, in which case all erase lines may be treated identically, or there will be only one erase line.
- V T threshold voltages
- each cell along the selected row has a low voltage on the control gate and a high voltage on the source, which encourages the tunneling of electrons off of the floating gate toward the source, through the tunneling oxide area, thus tending to lower the threshold of the cell.
- This condition is maintained for a predetermined, but very short, time.
- the hold time is selected in light of the programming characteristics of the particular cells, but is advantageously sufficient to alter the V T 's no more than one-quarter to one-half volt. For instance, the hold time may be approximately 10 to 100 microseconds.
- the selected byte is read according to the sequence described above. If any bits still read as programmed, then another erase pulse will be executed. If no cell reads as programmed, then the sequence will be terminated. Using this erase sequence depends upon a sufficient margin between V TSP and the point at which a cell has a negative threshold voltage to ensure that when the "last" cell in the selected byte is erased the "first" cell will not yet have acquired a negative V T .
- the expected threshold voltage spread, V T may be approximately 1 volt
- V TSP may be approximately 3 volts
- the erase pulse length may be chosen to alter V T no more than 0.5 volts per pulse, and one would expect the array to function properly.
- At least one alternate method of erasing single transistor EEPROM cells while avoiding over-erasure exists.
- the read sequence following each erase pulse is altered by leaving all word lines at approximately V SS .
- any cell which reads as erased has a V T of zero or less.
- a further modification or the read sequence is performed by slightly altering the bias of the sense amplifiers so that a cell reads as erased with a slightly higher V T than is the case with normal sense amplifier biasing. This assures that the "first" cell will be detected as erased while its threshold (with the control gate grounded) is still slightly positive.
- the erase sequence is terminated when the "first" cell reads as erased, depending on the margins discussed above to assure that the V T of the last cell is below V TSP .
- An EEPROM cell and array have been disclosed which offer a number of significant advantages over previous such cells and arrays.
- the cell is a true single transistor EEPROM cell and uses only manufacturing techniques which are familiar in the semiconductor industry.
- the disclosed cell offers significantly higher density than previous EEPROM cells.
- the array disclosed is efficiently organized to provide the capability of row and/or single byte erasing, thus offering speed advantages over EEPROM arrays which must be bulk erased in order to change stored values in any particular byte.
- the disclosed array and method of erasure which prevents over-erasure rather than compensating for its effects, offers the possibility of faster and more reliable operation.
Abstract
Description
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/947,212 US4878101A (en) | 1986-12-29 | 1986-12-29 | Single transistor cell for electrically-erasable programmable read-only memory and array thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/947,212 US4878101A (en) | 1986-12-29 | 1986-12-29 | Single transistor cell for electrically-erasable programmable read-only memory and array thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US4878101A true US4878101A (en) | 1989-10-31 |
Family
ID=25485745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/947,212 Expired - Lifetime US4878101A (en) | 1986-12-29 | 1986-12-29 | Single transistor cell for electrically-erasable programmable read-only memory and array thereof |
Country Status (1)
Country | Link |
---|---|
US (1) | US4878101A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4985717A (en) * | 1989-02-21 | 1991-01-15 | National Semiconductor | MOS memory cell with exponentially-profiled doping and offset floating gate tunnel oxidation |
US4992980A (en) * | 1989-08-07 | 1991-02-12 | Intel Corporation | Novel architecture for virtual ground high-density EPROMS |
US5019879A (en) * | 1990-03-15 | 1991-05-28 | Chiu Te Long | Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area |
US5051794A (en) * | 1988-07-05 | 1991-09-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method for manufacturing the same |
US5095461A (en) * | 1988-12-28 | 1992-03-10 | Kabushiki Kaisha Toshiba | Erase circuitry for a non-volatile semiconductor memory device |
US5162247A (en) * | 1988-02-05 | 1992-11-10 | Emanuel Hazani | Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array |
US5313427A (en) * | 1991-09-20 | 1994-05-17 | Texas Instruments Incorporated | EEPROM array with narrow margin of voltage thresholds after erase |
US5357463A (en) * | 1992-11-17 | 1994-10-18 | Micron Semiconductor, Inc. | Method for reverse programming of a flash EEPROM |
EP0630513A1 (en) * | 1992-03-13 | 1994-12-28 | Silicon Storage Technology, Inc. | A floating gate memory array device having improved immunity to write disturbance |
EP0718895A2 (en) * | 1994-12-20 | 1996-06-26 | Sharp Kabushiki Kaisha | Non-volatile memory and method for manufacturing the same |
US5591652A (en) * | 1993-11-08 | 1997-01-07 | Sharp Kabushiki Kaisha | Method of manufacturing flash memory with inclined channel region |
US20020067647A1 (en) * | 2000-12-05 | 2002-06-06 | Fujitsu Limited And Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4087795A (en) * | 1974-09-20 | 1978-05-02 | Siemens Aktiengesellschaft | Memory field effect storage device |
US4203158A (en) * | 1978-02-24 | 1980-05-13 | Intel Corporation | Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same |
US4317272A (en) * | 1979-10-26 | 1982-03-02 | Texas Instruments Incorporated | High density, electrically erasable, floating gate memory cell |
US4451905A (en) * | 1981-12-28 | 1984-05-29 | Hughes Aircraft Company | Electrically erasable programmable read-only memory cell having a single transistor |
US4486769A (en) * | 1979-01-24 | 1984-12-04 | Xicor, Inc. | Dense nonvolatile electrically-alterable memory device with substrate coupling electrode |
US4561004A (en) * | 1979-10-26 | 1985-12-24 | Texas Instruments | High density, electrically erasable, floating gate memory cell |
US4577215A (en) * | 1983-02-18 | 1986-03-18 | Rca Corporation | Dual word line, electrically alterable, nonvolatile floating gate memory device |
US4616340A (en) * | 1981-10-14 | 1986-10-07 | Agency Of Industrial Science & Technology | Non-volatile semiconductor memory |
US4668970A (en) * | 1982-01-29 | 1987-05-26 | Hitachi, Ltd. | Semiconductor device |
-
1986
- 1986-12-29 US US07/947,212 patent/US4878101A/en not_active Expired - Lifetime
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4087795A (en) * | 1974-09-20 | 1978-05-02 | Siemens Aktiengesellschaft | Memory field effect storage device |
US4203158A (en) * | 1978-02-24 | 1980-05-13 | Intel Corporation | Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same |
US4203158B1 (en) * | 1978-02-24 | 1992-09-22 | Intel Corp | |
US4486769A (en) * | 1979-01-24 | 1984-12-04 | Xicor, Inc. | Dense nonvolatile electrically-alterable memory device with substrate coupling electrode |
US4317272A (en) * | 1979-10-26 | 1982-03-02 | Texas Instruments Incorporated | High density, electrically erasable, floating gate memory cell |
US4561004A (en) * | 1979-10-26 | 1985-12-24 | Texas Instruments | High density, electrically erasable, floating gate memory cell |
US4616340A (en) * | 1981-10-14 | 1986-10-07 | Agency Of Industrial Science & Technology | Non-volatile semiconductor memory |
US4451905A (en) * | 1981-12-28 | 1984-05-29 | Hughes Aircraft Company | Electrically erasable programmable read-only memory cell having a single transistor |
US4668970A (en) * | 1982-01-29 | 1987-05-26 | Hitachi, Ltd. | Semiconductor device |
US4577215A (en) * | 1983-02-18 | 1986-03-18 | Rca Corporation | Dual word line, electrically alterable, nonvolatile floating gate memory device |
Non-Patent Citations (4)
Title |
---|
"How Seeq . . . Densities", Electronics, Aug. 21, 1986, 53-56. |
B. Cole, "The Exploding Rule in Memory", Electronics, Aug. 21, 1986, 47-52. |
B. Cole, The Exploding Rule in Memory , Electronics, Aug. 21, 1986, 47 52. * |
How Seeq . . . Densities , Electronics, Aug. 21, 1986, 53 56. * |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5162247A (en) * | 1988-02-05 | 1992-11-10 | Emanuel Hazani | Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array |
US5051794A (en) * | 1988-07-05 | 1991-09-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method for manufacturing the same |
US5095461A (en) * | 1988-12-28 | 1992-03-10 | Kabushiki Kaisha Toshiba | Erase circuitry for a non-volatile semiconductor memory device |
US4985717A (en) * | 1989-02-21 | 1991-01-15 | National Semiconductor | MOS memory cell with exponentially-profiled doping and offset floating gate tunnel oxidation |
US4992980A (en) * | 1989-08-07 | 1991-02-12 | Intel Corporation | Novel architecture for virtual ground high-density EPROMS |
US5019879A (en) * | 1990-03-15 | 1991-05-28 | Chiu Te Long | Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area |
US5313427A (en) * | 1991-09-20 | 1994-05-17 | Texas Instruments Incorporated | EEPROM array with narrow margin of voltage thresholds after erase |
EP0630513A1 (en) * | 1992-03-13 | 1994-12-28 | Silicon Storage Technology, Inc. | A floating gate memory array device having improved immunity to write disturbance |
EP0630513A4 (en) * | 1992-03-13 | 1995-07-19 | Silicon Storage Tech Inc | A floating gate memory array device having improved immunity to write disturbance. |
US5357463A (en) * | 1992-11-17 | 1994-10-18 | Micron Semiconductor, Inc. | Method for reverse programming of a flash EEPROM |
US5591652A (en) * | 1993-11-08 | 1997-01-07 | Sharp Kabushiki Kaisha | Method of manufacturing flash memory with inclined channel region |
EP0718895A2 (en) * | 1994-12-20 | 1996-06-26 | Sharp Kabushiki Kaisha | Non-volatile memory and method for manufacturing the same |
EP0718895A3 (en) * | 1994-12-20 | 1997-03-26 | Sharp Kk | Non-volatile memory and method for manufacturing the same |
US20020067647A1 (en) * | 2000-12-05 | 2002-06-06 | Fujitsu Limited And Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
US7075834B2 (en) * | 2000-12-05 | 2006-07-11 | Fujitsu Limited | Semiconductor integrated circuit device |
US20060221725A1 (en) * | 2000-12-05 | 2006-10-05 | Fujitsu Limited | Semiconductor integrated circuit device |
US7286424B2 (en) | 2000-12-05 | 2007-10-23 | Fujitsu Limited | Semiconductor integrated circuit device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4758986A (en) | Single transistor cell for electrically-erasable programmable read-only memory and array thereof | |
US5812452A (en) | Electrically byte-selectable and byte-alterable memory arrays | |
US5646886A (en) | Flash memory having segmented array for improved operation | |
US5245570A (en) | Floating gate non-volatile memory blocks and select transistors | |
US4375087A (en) | Electrically erasable programmable read only memory | |
US5319593A (en) | Memory array with field oxide islands eliminated and method | |
EP0247875B1 (en) | Block electrically erasable eeprom | |
US5414658A (en) | Electrically erasable programmable read-only memory array | |
US5457652A (en) | Low voltage EEPROM | |
US5583808A (en) | EPROM array segmented for high performance and method for controlling same | |
US5740107A (en) | Nonvolatile integrated circuit memories having separate read/write paths | |
US5687117A (en) | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | |
US4766473A (en) | Single transistor cell for electrically-erasable programmable read-only memory and array thereof | |
US5329487A (en) | Two transistor flash EPROM cell | |
US5790456A (en) | Multiple bits-per-cell flash EEPROM memory cells with wide program and erase Vt window | |
KR19980017439A (en) | Flash memory device and driving method thereof | |
JPH0845292A (en) | Memory cell,flash eeprom,method for erasing of memory cell and method for control of flash eeprom memory cell | |
US5521867A (en) | Adjustable threshold voltage conversion circuit | |
JPH03155667A (en) | New architecture for flash erasable eprom memory | |
JPH11265589A (en) | Programing method for nonvolatile memory including nand type cell array | |
US4878101A (en) | Single transistor cell for electrically-erasable programmable read-only memory and array thereof | |
US5469397A (en) | Semiconductor memory device with a reference potential generator | |
US5677871A (en) | Circuit structure for a memory matrix and corresponding manufacturing method | |
US4402064A (en) | Nonvolatile memory | |
US5576993A (en) | Flash memory array with self-limiting erase |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., SCHAUMBURG, ILLINOIS, A CORP. OF D Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:HSIEH, NING;KUO, CLINTON CHANG-KIANG;REEL/FRAME:004655/0727;SIGNING DATES FROM 19861219 TO 19861222 Owner name: MOTOROLA, INC., A CORP. OF DE.,ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, NING;KUO, CLINTON CHANG-KIANG;SIGNING DATES FROM 19861219 TO 19861222;REEL/FRAME:004655/0727 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 |