US5297273A - System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two - Google Patents
System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two Download PDFInfo
- Publication number
- US5297273A US5297273A US07/574,976 US57497690A US5297273A US 5297273 A US5297273 A US 5297273A US 57497690 A US57497690 A US 57497690A US 5297273 A US5297273 A US 5297273A
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- speed
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- parallel
- slow speed
- data signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
Definitions
- This invention relates to the field of digital testing apparatus for analyzing high speed data.
- the objective of digital testing is to determine whether for a given input signal (usually called “input test vector” since it is a set of parallel input bits) the output value (or state) of the device under test (DUT) is in error for any of its output channels.
- the test must determine the location of the error (i.e., specific bit and state) and the nature of the error (i.e., "1" instead of "0” or vice versa).
- State-of-the-art commercially available digital testers can test silicon based integrated circuits at speeds of the order of 200 MHz. Digital testing at 1-2 GHz rates as required for LSI GaAs integrated circuits or high-speed superconductive devices, however, is impossible with any known technology.
- a typical 100 MHz clock digital tester provides data pulsewidths of 10 ns with combined rise and fall times of about 30% the pulsewidth or 1.5 ns each.
- the timing resolution or accuracy with which the edges of the pulses are applied to the inputs of the DUT is typically 3-5% of the pulsewidth or about 300 ps. This requirement arises because of the need to verify the predicted propagation delay through the DUT.
- the tester must provide input test vectors whose elements (or bits) are positioned in time as accurately as possible.
- the tester skew (defined as the maximum timing error of a tester that measures the arrival of a pulse simultaneously applied to every pin of the tester's input) is typically 10% of the pulsewidth or 1 ns.
- the specifications of a 1.5 GHz (RZ) digital tester can be determined.
- the width of each bit is 666 ps which implies that square waveforms of about 330 ps must be generated having rise and fall times of 50 ps.
- the tester must be able to place the pulse edges as accurately as 35 ps.
- the system skew figure must be kept to less than 66 ps.
- a demultiplexer (DMUX) or serial-to-parallel converter is used to slow down the high-speed output DUT data so that they can be tested or stored using conventional low speed electronics.
- the highest speed DMUX device can operate at 1.5 G bit/s data rates and has a rise and fall time of 150 ps. This rise and fall time speed exceeds the specifications of the 1.5 GHz tester by a factor of 2. Consequently, there is a need for a digital testing device capable of testing high-speed data in excess of 1 GHz.
- an input signal generating means transmits high-speed input test vectors to the DUT.
- the DUT generates high-speed output test vectors.
- the high-speed output test vectors are then converted to slow-speed data signals. These slow-speed data signals ar compared with slow-speed reference vectors to determine whether the DUT is in error for any of its output channels.
- the first architecture we use a fiber optic splitter to split the high-speed output vector into parallel high-speed data signals.
- Avalanche photodiodes are connected to each parallel high-speed data signal and drive AND gates.
- the other input of the AND gate is driven by a gating signal, the pulse width of which is equal to 1/2 the pulsewidth of the high speed output vectors.
- the gating signal is delayed between any two successive AND gates by a delay equal to the bitwidth of the high-speed output vectors.
- IODC integrated optic directional coupling
- FIG. 1 is a schematic representation of a first presently preferred architecture of the high speed digital testing device of the present invention.
- FIG. 2 is a schematic representation of the timing relations of the various signals in the device of FIG. 1.
- FIG. 3 is a schematic representation of a second presently preferred architecture of the high speed digital testing device of the present invention.
- FIG. 4 is a schematic representation of an integrated optical directional coupler used in the device of FIG. 3.
- FIG. 5 is a schematic representation of a D Flip-Flop based high-to-low speed digital data electronic converter used in the device of FIGS. 1 and 3.
- Our invention can be embodied in two different architectures that are appropriate for receiving and slowing down the DUT's output data.
- the general idea of these architectures is to convert the high-speed output serial data from a single output pin on the DUT, into M parallel data, with speed reduced by a factor of M, so that they can be stored in a moderate speed parallel memory.
- the first architecture can be described as follows.
- the voltage generated at the output pin under test 12 of DUT 10 modulates the light intensity of a laser diode (LD) 14.
- the output of the laser diode 14 is coupled into an optical fiber which is then connected to an optical variable delay device 16 whose purpose is to compensate for possible output skew so that the timing through the rest of the system is appropriate.
- the output of the variable delay device 16 is then split into M channels via a fiber-optic 1:M splitter 18.
- the splitter's output fibers 20 are of the same length and thus the signals at the end of the fibers 20 are identical.
- the signals on the optical fibers 20 are readout and converted into electrical signals via the use of optical photodiodes 22.
- the outputs of the photodiodes 22 drive one input of M GaAs AND-gates 24.
- the other input of each of the AND gates 24 is driven by a gating signal 26.
- the gating signal 26 is delayed between two successive AND gates 24 by a delay equal to the bitwidth T b of the DUT 10.
- the output of the first AND gate 24 will consist of the first bit of the serial sequence followed by M-1 zeros
- the output of the second AND gate 24 will consist of a zero followed by the second bit of the serial sequence which in turn is followed by M-2 zeros
- the output of the third AND gate 24 will consist of two zeros followed by the third bit of the serial sequence which in turn is followed by M-3 zeros
- the output of the Mth AND gate 24 will consist of M-1 zeros followed by the last bit (mth) of the input serial sequence.
- the first AND gate output signal 25 is shown on FIG. 2.
- variable delay device 16 is also needed in order to synchronize the DUT 10 data with the gating signal 26.
- One such variable delay device 16 is disclosed in application Ser. No. 07/572,835, filed on Aug. 27, 1990, now U.S. Pat. No. 5,066,088 and incorporated herein by reference.
- the next step is to transform the high-speed low duty cycle data present in each of the M output channels into slow-speed data which can be stored in a moderate or slow speed memory 30.
- a pulse expander 28 to expand the bitwidth (from T b to T i as shown in pulse expander output signal 29 of FIG. 2) so that it is sufficiently long in order to be read by the memory 30.
- This can be achieved with a variety of one-shot multi-vibrator techniques, one of which is shown in FIG. 5.
- This technique uses a D flip-flop 40 with a reset 42 and an RC network 44 connected between the D flip-flop output 46 and the reset input 42.
- the RC constant is approximately equal to the desired bitwidth T i .
- the so-converted data 50 are then stored in an M-channel parallel memory 30.
- the next step is to compare the data of memory 30 with the reference data stored in another parallel memory 32. This can be achieved with slow speed comparators 34 under the control of a device such as a microprocessor.
- the proposed architecture is based on commercially available, well established optical and electronic technology, it is simple, practical and it can be easily implemented.
- the maximum speed is determined by the speed of the laser diode 14, photodiodes 22, AND gate 24, and Flip-Flop 40.
- Low cost, commercially available laser diodes 14 with speeds up to 12 GHz are available, such as the ORTEL 1515 B.
- photodiodes 22 with speeds of over 12 GHz are also Commercially available, such as ORTEL 2515 B.
- State-of-the-art GaAs AND gates 24 can operate at about 2.5 GHz, such as Gigabit Logic's 10G003.
- GaAs flip-flops 40 with inputs of about 2.7 GHz are commercially available, such as Gigabit Logic's 10G021A.
- this technique is limited by the speed of the AND gates 24 and is appropriate for up to 2.5 GHz (RZ) testers.
- the speeds and number of channels of the proposed serial-to-parallel converter cannot be achieved with any prior art technology including GaAs devices. The speed could be increased, however, if cryogenic superconductive AND gates 24 and D flip-flops 40 are used.
- an IODC 52 consists of two parallel waveguides which synchronously exchange power over a uniform interaction length L. Complete crossover is achieved when the waveguides 54 and 56 are phase matched and when the interaction length L is an exact odd multiple of the coupling length. The coupling length is the minimum length required to obtain complete crossover of the light.
- IODCs 52 can be used to implement an electrooptical 1:8 serial-to-parallel converter whose purpose is to separate the high-speed optical serial data which come from a single pin 12 of the DUT 10.
- V c1 , V c2 , and V c3 Three control signals (all raised cosines) are needed in the configuration shown in FIG. 3: V c1 , V c2 , and V c3 .
- the first signal, V c1 has a frequency equal to half of that of the DUT 10. Its purpose is to send "odd” numbered bits to ports P 1 -P 4 and "even” numbered bits to ports P 5 -P 8 .
- the V c2 signal has one quarter the frequency of the DUT 10, and its purpose is to separate the bits even further, by sending every other "odd" ("even") bit to ports P 1 -P 2 (P 5 -P 6 ).
- the V c3 signal has a frequency that equals an eighth of the DUT's 10 frequency and assigns the previously separated bits into the final ports.
- the frequency of each of the V ci signals can be determined by the relationship f/2 i where f is the frequency of DUT 10 and i is the level of the IODC structure in the tree type configuration.
- V ci data must be derived from a master clock, and a variable delay 16 must be used prior to the tree switches.
- the so-sorted data must be detected via the use of photodiodes 22.
- the outputs of the photodiodes 22 are then subject to pulse expansion 26 which will allow the data to be written in the memory 28, and subsequently tested.
- the major advantage of this architecture is that the GaAs-based electronic sorting is replaced by optoelectronic tree-type switches which allow operation at much higher speeds.
- IODC 52 devices operating at 4 GHz at 4V are commercially available and devices used for 8-Gbit/s data transmission are near commercial development. Higher frequency operation is also possible since experimental electrooptic devices with up to 40 GHz operation have been demonstrated.
Abstract
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US07/574,976 US5297273A (en) | 1990-08-30 | 1990-08-30 | System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two |
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US07/574,976 US5297273A (en) | 1990-08-30 | 1990-08-30 | System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two |
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US07/574,976 Expired - Lifetime US5297273A (en) | 1990-08-30 | 1990-08-30 | System for optically splitting high-speed digital signals using cascading tree-type configuration wherein the number of successive level of cascading increase by a factor of two |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996022030A1 (en) * | 1995-01-20 | 1996-07-25 | Mars, Incorporated | Edible products having inorganic coatings |
US5751242A (en) * | 1995-09-30 | 1998-05-12 | Northrop Grumman Corporation | Transmit-receive fiber-optic manifold for phase array antennas |
US6535661B2 (en) * | 2000-04-26 | 2003-03-18 | Nippon Telegraph And Telephone Corporation | Optical signal processing method and optical signal processing apparatus |
US20070237527A1 (en) * | 2006-03-31 | 2007-10-11 | Sanjay Dabral | Optical debug mechanism |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996022030A1 (en) * | 1995-01-20 | 1996-07-25 | Mars, Incorporated | Edible products having inorganic coatings |
US5751242A (en) * | 1995-09-30 | 1998-05-12 | Northrop Grumman Corporation | Transmit-receive fiber-optic manifold for phase array antennas |
US6535661B2 (en) * | 2000-04-26 | 2003-03-18 | Nippon Telegraph And Telephone Corporation | Optical signal processing method and optical signal processing apparatus |
US20070237527A1 (en) * | 2006-03-31 | 2007-10-11 | Sanjay Dabral | Optical debug mechanism |
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