US5339270A - AC drain voltage charging source for PROM devices - Google Patents

AC drain voltage charging source for PROM devices Download PDF

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Publication number
US5339270A
US5339270A US08/082,124 US8212493A US5339270A US 5339270 A US5339270 A US 5339270A US 8212493 A US8212493 A US 8212493A US 5339270 A US5339270 A US 5339270A
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drain
volts
signal
floating gate
programming
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Chun Jiang
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Callahan Cellular LLC
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VLSI Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

Definitions

  • This invention relates generally to the programming of programmable read-only memories, such as erasable programmable read-only memories (EPROMs).
  • EPROMs erasable programmable read-only memories
  • EPROMs are generally programmed using high DC voltages.
  • a voltage of 15 volts is placed on the gate, a voltage of 5 volts is placed on the drain and a voltage of 0 volts is placed on the source.
  • a negative voltage with high negative magnitude e.g. 11 volts
  • the programming and erasing results, for example, from current tunneling or current injection. See, for example, Y. Yamauchi, et al, "A 5V-Only Virtual Ground Flash Cell with An Auxiliary Gate for High Density and High Speed Application", IEDM, 1991, p. 11.7.1, or N. Kodama, et al., "A Symmetrical Side Wall(SSW)-DSA Cell for a 64Mbit Flash Memory", IEDM, 1991, p. 11.3.1.
  • the programming methods of the prior art have several drawbacks. For example, a high voltage source is needed to perform the programming. Also, EPROMs programmed according to the prior art often lack in endurance.
  • a method for programming a programmable read only memory is presented.
  • the PROM has a source, a drain and a control gate.
  • a DC signal is placed on the control gate.
  • the DC signal has a voltage of approximately 5 volts.
  • An oscillating signal is placed on the drain.
  • the oscillating signal for example, oscillates between approximately 0 volts and 5 volts and has a frequency of at least 100 MHz.
  • hot electron charges migrate through a tunnel oxide region to a floating gate, thus programming the PROM.
  • the present invention has several advantages over the prior art. For example, the present invention allows for a reduced gate and drain voltage amplitude during programming. The present invention also provides for more reliable operation of PROMs by avoiding hot holes being injected into the gate oxide. Additionally, the present invention allows for optimization of the oscillating frequency and pulse to increase programming efficiency.
  • FIG. 1 illustrates programming of an EPROM in accordance with the prior art.
  • FIG. 2 illustrates programming of an EPROM in accordance with the preferred embodiment of the present invention.
  • FIG. 3 shows a block diagram of an oscillator.
  • FIG. 1 illustrates programming of an EPROM in accordance with the prior art.
  • the EPROM includes a source 11, a drain 12 and a control gate 13.
  • source 11 is composed of n + type material doped at 5 ⁇ 10 15 per centimeter 2 or greater.
  • Drain 12 is composed of n + type material doped at 1 ⁇ 10 15 centimeter 2 or less.
  • Source 11 and drain 12 are within a substrate 10 of, for example, p-type material.
  • Control gate 13 is composed of, for example, polysilicon.
  • a floating gate 14 is composed of, for example, polysilicon.
  • Floating gate 14 is electrically isolated from control gate 13 by an inter-poly oxide region 17.
  • Inter-poly oxide region 17 is, for example, 16 nanometers thick and is composed of silicon-oxide.
  • Tunnel oxide region 16 electrically isolates floating gate 14 from substrate 10, source 11 and drain 12.
  • Tunnel oxide region 16 is, for example, 8 nanometers thick and is composed of silicon-oxide.
  • floating gate 14 is programmed, for example, by placing a 0 volt DC signal on drain 12 and source 11, as represented by waveform 19, and by placing a 15 volt DC signal on control gate 13. This results in current tunneling through tunnel oxide region 16 to floating gate 14.
  • floating gate 14 can be programmed, by placing a 7 volt DC signal on drain 12, as represented by waveform 19, by placing 0 volts on source 11 and by placing a 15 volt DC signal on control gate 13. This results in high energy electrons tunneling through tunnel oxide region 16 to floating gate 14.
  • FIG. 2 illustrates programming of an EPROM in accordance with the preferred embodiment of the present invention.
  • the EPROM includes a source 21, a drain 22 and a control gate 23.
  • source 21 is composed of n + type material doped at least 5 ⁇ 10 15 per centimeter 2 or greater.
  • Drain 22 is composed of n + type material doped at ⁇ 10 15 centimeter 2 or less.
  • Source 21 and drain 22 are within a substrate 20 of, for example, p-type material.
  • Control gate 23 is composed of, for example, polysilicon.
  • a floating gate 24 is composed of, for example, polysilicon. Floating gate 24 is electrically isolated from control gate 23 by an inter-poly oxide region 27.
  • Inter-poly oxide region 27 is, for example, 16 nanometers thick and is composed of silicon-oxide.
  • Tunnel oxide region 26 electrically isolates floating gate 24 from substrate 20, source 21 and drain 22.
  • Tunnel oxide region 26 is, for example, 8 nanometers thick and is composed of silicon-oxide.
  • floating gate 24 is programmed, for example, by placing a 5 volt DC signal on control gate 23, as represented by a waveform 28, and by placing a 0 to 5 volt oscillating signal on drain 22 by a waveform 29.
  • the oscillating signal oscillates at a frequency of at least 100 MHz.
  • Vd voltage
  • hot electrons are generated in the drain region and an equilibrium state is maintained.
  • Vd drops to 0 volts, due to the sudden lowering of the gate oxide barrier, the hot electrons in the drain regions can tunnel into the floating gate, before they have enough time to lose their energies.
  • the success of this programming process depends on achieving a short fall time of Vd from 5 volts to 0 volts.
  • the fall time should be 0.1 picoseconds or less. In general, the fall time should be less than the hot electron relaxation time.
  • the structure design of the preferred embodiment can be optimized by providing for a structure which allows hot electrons to easily tunnel through tunnel oxide region 26 to floating gate 24.
  • FIG. 3 shows an oscillator 31 which generates the oscillating signal on drain 22.

Abstract

A method for programming a programmable read only memory (PROM) is useful for a PROM which has a source, a drain and a control gate. A DC signal is placed on the control gate. For example, the DC signal has a voltage of approximately 5 volts. An AC signal is placed on the drain. The AC signal, for example, oscillates between approximately 0 volts and 5 volts and has a frequency of at least 100 Megahertz. As a result, charges tunnel through a tunnel oxide region to an floating gate, thus programming the PROM.

Description

BACKGROUND
This invention relates generally to the programming of programmable read-only memories, such as erasable programmable read-only memories (EPROMs).
In the prior art, EPROMs are generally programmed using high DC voltages. For example, when programming an EPROM, in order to program a floating gate of the EPROM, a voltage of 15 volts is placed on the gate, a voltage of 5 volts is placed on the drain and a voltage of 0 volts is placed on the source. When erasing the EPROM, a negative voltage with high negative magnitude (e.g. 11 volts) is placed on the control gate. The programming and erasing results, for example, from current tunneling or current injection. See, for example, Y. Yamauchi, et al, "A 5V-Only Virtual Ground Flash Cell with An Auxiliary Gate for High Density and High Speed Application", IEDM, 1991, p. 11.7.1, or N. Kodama, et al., "A Symmetrical Side Wall(SSW)-DSA Cell for a 64Mbit Flash Memory", IEDM, 1991, p. 11.3.1.
The programming methods of the prior art have several drawbacks. For example, a high voltage source is needed to perform the programming. Also, EPROMs programmed according to the prior art often lack in endurance.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a method for programming a programmable read only memory (PROM) is presented. The PROM has a source, a drain and a control gate. A DC signal is placed on the control gate. For example, the DC signal has a voltage of approximately 5 volts. An oscillating signal is placed on the drain. The oscillating signal, for example, oscillates between approximately 0 volts and 5 volts and has a frequency of at least 100 MHz. As a result, hot electron charges migrate through a tunnel oxide region to a floating gate, thus programming the PROM.
The present invention has several advantages over the prior art. For example, the present invention allows for a reduced gate and drain voltage amplitude during programming. The present invention also provides for more reliable operation of PROMs by avoiding hot holes being injected into the gate oxide. Additionally, the present invention allows for optimization of the oscillating frequency and pulse to increase programming efficiency.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates programming of an EPROM in accordance with the prior art.
FIG. 2 illustrates programming of an EPROM in accordance with the preferred embodiment of the present invention.
FIG. 3 shows a block diagram of an oscillator.
DESCRIPTION OF THE PRIOR ART
FIG. 1 illustrates programming of an EPROM in accordance with the prior art. The EPROM includes a source 11, a drain 12 and a control gate 13. For example, source 11 is composed of n+ type material doped at 5×1015 per centimeter2 or greater. Drain 12 is composed of n+ type material doped at 1×1015 centimeter2 or less. Source 11 and drain 12 are within a substrate 10 of, for example, p-type material. Control gate 13 is composed of, for example, polysilicon. A floating gate 14 is composed of, for example, polysilicon. Floating gate 14 is electrically isolated from control gate 13 by an inter-poly oxide region 17. Inter-poly oxide region 17 is, for example, 16 nanometers thick and is composed of silicon-oxide. Tunnel oxide region 16 electrically isolates floating gate 14 from substrate 10, source 11 and drain 12. Tunnel oxide region 16 is, for example, 8 nanometers thick and is composed of silicon-oxide.
In the prior art, floating gate 14 is programmed, for example, by placing a 0 volt DC signal on drain 12 and source 11, as represented by waveform 19, and by placing a 15 volt DC signal on control gate 13. This results in current tunneling through tunnel oxide region 16 to floating gate 14.
Alternately, in the prior art, floating gate 14 can be programmed, by placing a 7 volt DC signal on drain 12, as represented by waveform 19, by placing 0 volts on source 11 and by placing a 15 volt DC signal on control gate 13. This results in high energy electrons tunneling through tunnel oxide region 16 to floating gate 14.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 2 illustrates programming of an EPROM in accordance with the preferred embodiment of the present invention. The EPROM includes a source 21, a drain 22 and a control gate 23. For example, source 21 is composed of n+ type material doped at least 5×1015 per centimeter2 or greater. Drain 22 is composed of n+ type material doped at ×1015 centimeter2 or less. Source 21 and drain 22 are within a substrate 20 of, for example, p-type material. Control gate 23 is composed of, for example, polysilicon. A floating gate 24 is composed of, for example, polysilicon. Floating gate 24 is electrically isolated from control gate 23 by an inter-poly oxide region 27. Inter-poly oxide region 27 is, for example, 16 nanometers thick and is composed of silicon-oxide. Tunnel oxide region 26 electrically isolates floating gate 24 from substrate 20, source 21 and drain 22. Tunnel oxide region 26 is, for example, 8 nanometers thick and is composed of silicon-oxide.
In the preferred embodiment, floating gate 24 is programmed, for example, by placing a 5 volt DC signal on control gate 23, as represented by a waveform 28, and by placing a 0 to 5 volt oscillating signal on drain 22 by a waveform 29. For example, the oscillating signal oscillates at a frequency of at least 100 MHz. When the voltage (Vd) on drain 22 is at 5 volts, high energy (hot) electrons are generated in the drain region and an equilibrium state is maintained. When Vd drops to 0 volts, due to the sudden lowering of the gate oxide barrier, the hot electrons in the drain regions can tunnel into the floating gate, before they have enough time to lose their energies.
The success of this programming process depends on achieving a short fall time of Vd from 5 volts to 0 volts. Preferably the fall time should be 0.1 picoseconds or less. In general, the fall time should be less than the hot electron relaxation time. The structure design of the preferred embodiment can be optimized by providing for a structure which allows hot electrons to easily tunnel through tunnel oxide region 26 to floating gate 24.
FIG. 3 shows an oscillator 31 which generates the oscillating signal on drain 22.
The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. For example, the discussion of the preferred embodiment describes an EPROM built on a substrate of p-conductivity type. As will be clearly understood by those skilled in the art, the present invention could work with other types of PROMs which are, for example, built on a substrate of n-conductivity type.
Therefore, as will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims (4)

I claim:
1. A method for programming a programmable read only memory having a source, a drain, a floating gate and a control gate, wherein the floating gate region is separated from the drain by a tunnel oxide region, the method comprising the steps of:
(a) placing a DC signal on the control gate; and
(b) placing an oscillating signal on the drain, wherein an oscillating frequency and a fall time for the oscillating signal are selected so that upon the oscillating signal reaching a minimum voltage, hot electrons at the drain tunnel through the tunnel oxide region to the floating gate, thereby charging the floating gate.
2. A method as in claim 1 wherein, in step (a) the DC signal has a voltage of approximately 5 volts.
3. A method as in claim 1 wherein in step (b), the oscillating signal oscillates between approximately 0 volts and 5 volts and has a frequency greater than 100 Megahertz.
4. A method as in claim 1 wherein, in step (b), the oscillating signal fall time from high voltage to low voltage is less than or equal to 0.1 pico-second.
US08/082,124 1993-06-23 1993-06-23 AC drain voltage charging source for PROM devices Expired - Lifetime US5339270A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5604185A (en) * 1995-03-27 1997-02-18 Mobil Oil Corporation Inhibition of scale from oil well brines utilizing a slow release composition and a preflush and/or after flush
US5638320A (en) * 1994-11-02 1997-06-10 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5680341A (en) * 1996-01-16 1997-10-21 Invoice Technology Pipelined record and playback for analog non-volatile memory
US5969986A (en) * 1998-06-23 1999-10-19 Invox Technology High-bandwidth read and write architectures for non-volatile memories
US6314025B1 (en) 1998-06-23 2001-11-06 Sandisk Corporation High data rate write process for non-volatile flash memories
US6606267B2 (en) 1998-06-23 2003-08-12 Sandisk Corporation High data rate write process for non-volatile flash memories
USRE41021E1 (en) * 1993-09-21 2009-12-01 Kabushiki Kaisha Toshiba Multi-state EEPROM having write-verify control circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4057788A (en) * 1974-10-21 1977-11-08 Raytheon Company Semiconductor memory structures
US4279024A (en) * 1978-06-30 1981-07-14 Siemens Aktiengesellschaft Word-by-word electrically reprogrammable nonvolatile memory
US4449205A (en) * 1982-02-19 1984-05-15 International Business Machines Corp. Dynamic RAM with non-volatile back-up storage and method of operation thereof
US5239500A (en) * 1989-09-29 1993-08-24 Centre Suisse D'electronique Et De Microtechnique S.A. Process of storing analog quantities and device for the implementation thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4057788A (en) * 1974-10-21 1977-11-08 Raytheon Company Semiconductor memory structures
US4279024A (en) * 1978-06-30 1981-07-14 Siemens Aktiengesellschaft Word-by-word electrically reprogrammable nonvolatile memory
US4449205A (en) * 1982-02-19 1984-05-15 International Business Machines Corp. Dynamic RAM with non-volatile back-up storage and method of operation thereof
US5239500A (en) * 1989-09-29 1993-08-24 Centre Suisse D'electronique Et De Microtechnique S.A. Process of storing analog quantities and device for the implementation thereof

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
E. S ckingeret al., An Analog Trimming Circuit Based on a Floating Gate Device, IEEE Journal of Solid State Circuits, vol. 23 6, Dec. 1988, pp. 1437 1440. *
E. Sackingeret al., "An Analog Trimming Circuit Based on a Floating-Gate Device," IEEE Journal of Solid-State Circuits, vol. 23 #6, Dec. 1988, pp. 1437-1440.
N. Kodama, et al., "A Symmetrical Side Wall(SSW)-DSA Cell for a 64Mbit Flash Memory", IEDM, Dec. 1991, p. 11.3.1.
N. Kodama, et al., A Symmetrical Side Wall(SSW) DSA Cell for a 64Mbit Flash Memory , IEDM, Dec. 1991, p. 11.3.1. *
Y. Yamauchi, et al, "A 5V-Only Virtual Ground Flash with An Auxiliary Gate for High Density and High Speed Application", IEDM Dec. 1991, p. 11.7.1.
Y. Yamauchi, et al, A 5V Only Virtual Ground Flash with An Auxiliary Gate for High Density and High Speed Application , IEDM Dec. 1991, p. 11.7.1. *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41021E1 (en) * 1993-09-21 2009-12-01 Kabushiki Kaisha Toshiba Multi-state EEPROM having write-verify control circuit
US5553020A (en) * 1994-06-28 1996-09-03 Intel Corporation Structure and method for low current programming of flash EEPROMs
US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5638320A (en) * 1994-11-02 1997-06-10 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5687115A (en) * 1994-11-02 1997-11-11 Invoice Technology, Inc. Write circuits for analog memory
US5694356A (en) * 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5751635A (en) * 1994-11-02 1998-05-12 Invoice Technology, Inc. Read circuits for analog memory cells
US5604185A (en) * 1995-03-27 1997-02-18 Mobil Oil Corporation Inhibition of scale from oil well brines utilizing a slow release composition and a preflush and/or after flush
US5680341A (en) * 1996-01-16 1997-10-21 Invoice Technology Pipelined record and playback for analog non-volatile memory
US20050248986A1 (en) * 1998-02-23 2005-11-10 Wong Sau C High data rate write process for non-volatile flash memories
US7349255B2 (en) 1998-02-23 2008-03-25 Sandisk Corporation High data rate write process for non-volatile flash memories
US5969986A (en) * 1998-06-23 1999-10-19 Invox Technology High-bandwidth read and write architectures for non-volatile memories
US6944058B2 (en) 1998-06-23 2005-09-13 Sandisk Corporation High data rate write process for non-volatile flash memories
US20030206469A1 (en) * 1998-06-23 2003-11-06 Wong Sau C. High data rate write process for non-volatile flash memories
US6606267B2 (en) 1998-06-23 2003-08-12 Sandisk Corporation High data rate write process for non-volatile flash memories
US6314025B1 (en) 1998-06-23 2001-11-06 Sandisk Corporation High data rate write process for non-volatile flash memories

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