US5537648A - Geometric autogeneration of "hard" phase-shift designs for VLSI - Google Patents
Geometric autogeneration of "hard" phase-shift designs for VLSI Download PDFInfo
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- US5537648A US5537648A US08/290,625 US29062594A US5537648A US 5537648 A US5537648 A US 5537648A US 29062594 A US29062594 A US 29062594A US 5537648 A US5537648 A US 5537648A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F1/30—Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S706/00—Data processing: artificial intelligence
- Y10S706/902—Application using ai with detail of the ai system
- Y10S706/919—Designing, planning, programming, CAD, CASE
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S706/00—Data processing: artificial intelligence
- Y10S706/902—Application using ai with detail of the ai system
- Y10S706/919—Designing, planning, programming, CAD, CASE
- Y10S706/92—Simulation
Definitions
- the present invention generally relates to the manufacture of very large scale integrated (VLSI) circuit devices and, more particularly, to resolution enhancement of photolithographic images through the use of phase shifted masks. More specifically, a method and apparatus are provided to autogenerate data for creating phase shifted masks from existing circuit designs.
- VLSI very large scale integrated
- Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps.
- photosensitive polymers sometimes referred to as photoresists or resists
- the manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending in the removal of the expended photoresist to make way for a new resist to be applied for another iteration of this process sequence.
- the basic lithography system consists of a light source, a stencil or photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. Since a wafer containing from fifty to one hundred chips is patterned in steps of one to four chips at a time, these lithography tools are commonly referred to as steppers.
- the resolution, R, of an optical projection system such as a lithography stepper is limited by parameters described in Rayleigh's equation: ##EQU1## where ⁇ is the wavelength of the light source used in the projection system and NA is the numerical aperture of the projection optics used.
- k 1 is a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from 0.8 down to 0.5 for standard exposure systems.
- the highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm wavelengths, but mid ultra violet (MUV) steppers with a wavelength of 356 nm are also in widespread use.
- DUV deep ultra violet
- UUV mid ultra violet
- photomasks consist of chromium patterns on a quartz plate, allowing light to pass wherever the chromium is removed from the mask. Light of a specific wavelength is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which allows developer to dissolve and remove the resist in the exposed areas. (Negative resist systems allow only unexposed resist to be developed away.)
- the photomask when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chrome).
- Phase shifted mask (PSM) lithography improves the lithographic process latitude or allows operation of a lower k 1 value (see equation 1) by introducing a third parameter on the mask.
- the electric field vector like any vector quantity, has a magnitude and direction, so in addition to turning the electric field amplitude on and off, it can be turned on with a 0° phase or turned on with a 180° phase. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material.
- DRAM Dynamic Random Access Memory
- Phase edge PSM lithography makes use of contrast enhancement caused by a phase transition under an opaque feature on a mask. This phase transition is achieved by etching an appropriate depth into the quartz mask substrate on one side of a narrow line structure on the mask. Not all narrow line structures on the mask close upon themselves, some edges of the etched region will terminate in bare quartz regions. Since the 180° phase transition forces a minimum in the image intensity, narrow dark lines will be printed by these excess phase edges. Currently, the unwanted images are erased using a trim mask, a second mask that transmits light only in regions left unexposed by the residual phase edge.
- the computer aided design (CAD) system uses a series of basic geometric operations to design areas requiting phase assignment, group sets of interrelated features into runs, resolve conflicting phase assignments, and eliminate unwanted phase edges. This process allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm.
- phase regions are created by expanding the features in question by an amount deemed as the minimum necessary separation between structures with the same phase assignment. Since a phase transition is required across the major axis of the critical features, the expanded shapes are separated into two halves, using the original critical shape as a cutline. Merging all abutting or overlapping phase regions ensures unique phase assignment to each region. Regions in the design that do not allow for phase termination due to space limitations that would prevent the subsequent removal of residual phase edges are blocked out by designing "dummy" phase regions by filling all gaps in the design smaller than the required phase trim width.
- phase regions are merged in with the critical phase regions if they abut or overlap them, ensuring that edges of phase regions always are placed in design regions where they can be subsequently removed.
- the result consists of polygons that fill the space between critical features, requiring a phase transition, and any areas that do not allow for phase termination due to space constraints.
- Isolated features that have no phase regions from other critical features interfering with their own, now have a phase transition, left and right can be arbitrarily associated with 0° and 180° phase regions.
- Design trim feature A final series of geometric operations is used to clean up the design and to design assist features that will be used to erase lines printed by unwanted phase transitions.
- FIGS. 1A, 1B and 1C taken together, are a flow diagram showing the logic of the computer implemented method according to the present invention
- FIG. 2 is a plan view of a portion of a VLSI circuit design used to illustrate the method according to the present invention
- FIG. 3 is a plan view of the VLSI circuit design shown in FIG. 2 with small features extended over base;
- FIG. 4 is a plan view of the VLSI circuit design shown in FIG. 3 with ends of merged small features extended;
- FIG. 5 is a plan view of the VLSI circuit design shown in FIG. 2 with spaces filled between base shapes;
- FIG. 6 is a plan view of the VLSI circuit design shown in FIG. 2 with small features expanded;
- FIG. 7 is a plan view of the VLSI circuit design shown in FIG. 6 with fill shapes that contact potential phase regions merged;
- FIG. 8 is a plan view of the VLSI circuit design as shown in FIGS. 4 and 7 with areas formed by expanding small features and adding trim blockouts separated;
- FIG. 9 is a plan view of the VLSI circuit design shown in FIG. 8 with ends in phase regions removed;
- FIG. 10 is a plan view of the VLSI circuit design shown in FIGS. 2 and 9 with phase regions tagged;
- FIG. 11 is a plan view of the VLSI circuit design shown in FIG. 10 with phase assignments initiated;
- FIG. 12 is a plan view of the VLSI circuit design shown in FIG. 11 with a phase transition across first phase transition line (PTL) in every cluster.
- PTL phase transition line
- FIGS. 13 to 15 are plan views of the VLSI circuit design with alternating PTLs
- FIG. 16 is a plan view of the VLSI circuit design with PHASE 180 regions cleaned up.
- FIG. 17 is a plan view of the VLSI circuit design with the trim mask patterns designed.
- FIGS. 1A, 1B and 1C there is shown a flow diagram which illustrates the logic of the computer program for the autogeneration of a phase shifted mask design from a typical polygate structure in a VLSI circuit design.
- the source code for the program can be written in a computer language compatible with a particular CAD program in which it is to be implemented.
- the CAD system which embodies the invention includes a programmed computer having input/output (I/O) channels respectively connected to receive input data of existing circuit designs and to generate output phase shift mask designs.
- the input parameters are established. These include the cutoff (i.e., the largest feature width needing a phase shift mask (PSM)), the trim (i.e., the distance required for phase termination), and overlay or OL (i.e., the overlay of phase onto Cr, second level write OL). These input parameters are passed to blocks 102 and 103.
- Block 102 also receives the design data for the VLSI circuit design.
- FIG. 2 illustrates by way of example a portion of a typical VLSI circuit design.
- the small features of the VLSI circuit design are located. These features of the design, in this case polysilicon gate structures (shown in FIG.
- the next step in block 104 is to extend the ends of the located small features (i.e., the gates) over the base feature, as shown in FIG. 3. This is done to avoid phase termination close to a critical feature.
- the gaps between small features over the base features are filled in to avoid notching in jogs upon end extension.
- the ends of the merged small features are extended in block 106 (in FIG. 1B) to form a "cutline" to separate two halves of the phase region, as shown in FIG. 4.
- block 103 starting again with the portion of the VLSI circuit design shown in FIG. 2, the spaces between the base shapes that are too tight to trim are filled to create trim blockout regions, as shown in FIG. 5.
- block 107 the small features located in block 102 are expanded to start forming phase regions, as shown in FIG. 6.
- the results of the steps performed in blocks 103 and 107 are input to block 108 (in FIG. 1B) where the fill shapes that contact potential phase regions are selected and merged, as shown in FIG. 7. This avoids phase termination in small spaces between large features.
- the patterns generated in the steps of blocks 106 and 108 are input to block 109 where the area formed by expanding small features and adding trim blockouts is separated in two halves with the small feature needing phase contrast at the division. This is shown in FIG. 8, where base shapes and end extended small features are subtracted from phase regions.
- the next step in block 110 is to remove the ends in phase regions that extend past the ends of base features, as is illustrated in FIG. 9. The phase regions are trimmed back to the ends of the critical features or a desired phase termination line. This is done by merging halves and base shapes, then shrinking, expanding, and separating out halves and base shapes.
- phase transition line (PTL) data from block 102 (FIG. 1A) and phase region data from block 110 (FIG. 1A) are combined in block 111 where phase regions are tagged as "left” and "right". Tagging is shown in FIG. 10 with the convention that a "left” phase region is hatched with lines at 45°, while a “right” phase region is hatched with lines at 135°. Regions which conflict will appear to be double tagged; that is, with "x x x" hatching.
- phase assignments are initiated in each independent cluster of phase transition lines (PTLs).
- PTLs phase transition lines
- all phase regions which were tagged "right” and do not conflict with phase regions tagged "left” are assigned a phase (i.e., PHASE 180°).
- FIG. 11 This step is shown in FIG. 11, where the start of a run of interrelated phase regions is defined by selecting a uniquely defined phase region and assigning it a phase.
- a phase transition is created across the first PTL in every cluster of PTLs.
- an alternative phase is assigned to regions on the opposite side of a critical feature bounded by a phase regions assigned in a previous step (i.e., PHASE 0° where previous assignment was PHASE 180°).
- Phase alternation across phase transition lines shown in block 114, is continued until the longest run is complete. Illustration of this process is shown in FIGS. 13 to 15.
- phase design is cleaned up by filling small gaps and overlapping the phase regions with the regions defining chrome designs on the mask. This process is illustrated in FIG. 16.
- trim mask patterns are designed. Shown in FIG. 17, the trim features are used to erase unwanted line resulting from residual phase terminations.
Abstract
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US08/290,625 US5537648A (en) | 1994-08-15 | 1994-08-15 | Geometric autogeneration of "hard" phase-shift designs for VLSI |
US08/440,051 US5636131A (en) | 1994-08-15 | 1995-05-12 | Geometric autogeneration of"hard"phase-shift designs for VLSI |
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US08/290,625 US5537648A (en) | 1994-08-15 | 1994-08-15 | Geometric autogeneration of "hard" phase-shift designs for VLSI |
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US08/440,051 Division US5636131A (en) | 1994-08-15 | 1995-05-12 | Geometric autogeneration of"hard"phase-shift designs for VLSI |
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US08/440,051 Expired - Fee Related US5636131A (en) | 1994-08-15 | 1995-05-12 | Geometric autogeneration of"hard"phase-shift designs for VLSI |
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Cited By (74)
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US5629861A (en) * | 1995-05-19 | 1997-05-13 | International Business Machines Corporation | Nested maximum space computation and efficient generation of nested shape complementation |
US5636131A (en) * | 1994-08-15 | 1997-06-03 | International Business Machines Corporation | Geometric autogeneration of"hard"phase-shift designs for VLSI |
US5807649A (en) * | 1996-10-31 | 1998-09-15 | International Business Machines Corporation | Lithographic patterning method and mask set therefor with light field trim mask |
US5867401A (en) * | 1996-01-11 | 1999-02-02 | Fujitsu Limited | Phase shifter arranging method and computer readable medium storing program for carrying out the method |
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US5923562A (en) * | 1996-10-18 | 1999-07-13 | International Business Machines Corporation | Method for automatically eliminating three way intersection design conflicts in phase edge, phase shift designs |
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