US5721927A - Method for verifying contiquity of a binary translated block of instructions by attaching a compare and/or branch instruction to predecessor block of instructions - Google Patents

Method for verifying contiquity of a binary translated block of instructions by attaching a compare and/or branch instruction to predecessor block of instructions Download PDF

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US5721927A
US5721927A US08/689,357 US68935796A US5721927A US 5721927 A US5721927 A US 5721927A US 68935796 A US68935796 A US 68935796A US 5721927 A US5721927 A US 5721927A
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instructions
block
instruction
executable
translated
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Leonid Baraz
Yaron Farber
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Definitions

  • the invention relates to computer systems, and, in particular, increasing the performance of verifying binary translated blocks of instructions.
  • machine instructions are selected from a set of machine instructions unique to a particular instruction set architecture.
  • Computer program statements that have been decoded into machine instructions for a source instruction set computer architecture may undergo a binary translation in order to be executed on a target instruction set computer architecture, such as the reduced instruction-set computer (RISC) architecture or the very long instruction word (VLIW) architecture.
  • RISC reduced instruction-set computer
  • VLIW very long instruction word
  • the machine instructions are typically translated and stored in memory in a separate block of instructions. Each block of instructions consist of a contiguous sequence of non-branch machine-instructions ending with a branch instruction.
  • a computer program such as the Untranslated Source program of FIG. 1, typically consists of multiple blocks of instructions stored in a physical static sequence (e.g., BB 1 , BB 2 , BB 3 . . . )
  • the order that the blocks of instructions are executed can be different from the static sequence.
  • the execution order is determined by the behavior of the branch instructions in the block of instructions.
  • the order of execution branches (i.e., transfers) to a separate block of instructions that is separate in the static sequence of the program. Otherwise, the order of execution continues at the block of instructions that immediately follows in the static sequence.
  • the branch instruction of BB 1 if the branch instruction of BB 1 is taken, the order of execution branches from BB 1 to BB 3 . BB 2 , therefore, is not executed in the example order of execution.
  • BB 1 The block of instructions from which the order of execution continues from is hereinafter referred to as a "predecessor" block of instructions, regardless whether the branch is taken.
  • BB 1 would be considered a predecessor block of instructions with respect to BB 3 .
  • a predecessor block of instructions needs to obtain a memory address for the translation of a block of instructions that follows in the order of execution.
  • the memory address of a translated block of instructions is hereinafter referred to as the translation address.
  • the speed of obtaining translation addresses is increased by storing translation addresses in a special section of memory referred to as the Translated Address Table (TAT), such as the one shown in the memory of FIG. 1.
  • TAT Translated Address Table
  • the alternative look-up routine typically involves searching the contents of a larger data structure in memory, which stores a greater number of translation addresses.
  • the translation addresses stored in the TAT are typically indexed by the hash values of the memory addresses for the corresponding block of instructions untranslated (hereinafter referred to as the source addresses).
  • the source addresses For the example of using the 12 least significant bits (LSB) of source addresses to index the entries of the TAT. If a particular block of instructions has a source address with the 12 LSB equal to 25, than the translation address for that block of instructions would be stored at the 25th entry of the TAT.
  • LSB least significant bits
  • the present invention provides a method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution.
  • the method includes appending a compare instruction to the first block of instructions.
  • the compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution.
  • the method further includes appending a branching instruction to the first block of instructions.
  • the branching instruction is executed in response to the first value being unequal to the second value.
  • the branching instruction when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
  • FIG. 1 illustrates a computer system capable of implementing one embodiment of the present invention.
  • FIG. 2 is a flow diagram describing the steps of implementing one embodiment of the present invention.
  • FIG. 3 is a flow diagram describing the steps of performing one embodiment of the present invention.
  • a method is described for increasing the performance of verifying whether a binary translated block of instructions follows a predecessor translated block of instructions in the order of execution.
  • FIG. 1 Shown in FIG. 1, is a target instruction set computer architecture capable of performing the present invention. Included in the memory of FIG. 1 is the Untranslated Source Program consisting of multiple untranslated blocks of instructions. These blocks of instructions are executable on a separate source instruction set computer architecture.
  • the binary translator also shown in the memory of FIG. 1, translates the untranslated blocks of instructions, block by block, so that the instructions are executable on the target instruction set computer architecture.
  • the translator translates each untranslated instruction by decoding each untranslated instruction into an opcode and operands.
  • the opcode indicates an operation to be performed by the instruction, and the operands identify the memory or register addresses of data to be operated on by the opcode.
  • the translator then provides a separate sequence of instructions in place of a decoded instruction's opcode.
  • the instructions provided by the translator are selected from the target instruction set computer architecture's instruction set and typically achieve the same operation as the decoded instruction's opcode.
  • the translator also translates the memory addresses of the decoded instruction's operands to be compatible with the target computer architecture memory addressing.
  • the translator appends to the translated block of instructions additional instructions that enable a translated block of instructions to verify whether it is the correct translated block of instructions following the predecessor block of instructions in the order of execution.
  • the translated block of instructions are stored in the area of memory allocated for storing Binary Translated Blocks of Instructions, shown in FIG. 1.
  • the memory address for each translated block of instructions i.e., translation address
  • the Translation Address Table also shown in the memory of FIG. 1.
  • the binary translator, Untranslated Source Program, binary Translated Blocks of Instructions, and the TAT shown stored in the memory can also be stored on other computer-readable mediums, such as magnetic disks or optical disks, accessible via a disk drive. These items may also be stored on a cache memory.
  • FIG. 2 a flow diagram is shown describing the steps of translator enabling a translated block of instructions to verify whether it is the correct translated block of instructions following a translated predecessor block of instructions in an order of execution, according to one embodiment of the present invention.
  • an untranslated first block of instructions is identified by a program counter during the translation of an untranslated program.
  • the binary translator begins translating the untranslated first block instructions into a translated block of instructions that is executable with the target instruction set computer architecture. The translation may be performed dynamically during the execution of the untranslated block of instructions, or statically when the block of instructions is not being executed.
  • the translator provides a compare instruction to have the first block of instructions compare its source address with a source address provided by a predecessor block of instructions.
  • the source address provided by the predecessor block of instructions is the source address of the block of instructions that should follow the predecessor block of instructions in the order of execution.
  • the translator provides to the first block of instructions a branching instruction to branch to an alternative look-up routine if the source address of the first block of instructions is not equal to the source address provided by the predecessor block of instructions.
  • the alternative look-up routine is a procedure stored in the binary translator.
  • the alternative look-up routine may obtain the translation addresses by searching a larger section of memory allocated to storing translation addresses of binary translated blocks of instructions (hereinafter referred to as the Alternative Translation Address Memory Area) as shown in the memory of FIG. 1.
  • the translator sequentially performs a binary translation of each remaining untranslated instruction included in the first block of instructions.
  • the translator provides to the first block of instructions, a loading instruction to load the source address of the block of instructions that is to follow the first block of instructions in the order of execution.
  • the source address is typically loaded into a memory location that may be a register of a processor, a cache memory location, or a main memory address location.
  • the actual source address that is loaded depends on the results of the conditional branch instruction when executing the first block of instructions. If the branch is to be taken, then source address for the block of instructions that is a branch target of the first block of instructions is loaded. Otherwise, the source address of the block for instructions that follows the first block of instructions in the static sequence of the Untranslated Source Program.
  • the source address loaded by the first block of instructions can subsequently be used by a second translated block of instructions to verify whether the second translated block of instructions correctly follows the first block of instructions in the order of execution.
  • the second translated block of instructions compares its source address with the source address provided by the first block of instructions to perform the verification.
  • the translator adds an instruction, to the first block of instructions, to generate an index into the TAT.
  • the index is used to obtain the translation address for the block of instructions that is to follow in the order of execution.
  • the index generated is a hash value of the source address loaded by the first block of instructions.
  • the hash value generated is the 12 LSB of the source address.
  • the 12 LSB of the source address is then used to locate an entry in the TAT corresponding to the 12 LSB.
  • other hash values may be generated from the source address loaded by the first block of instructions without departing from the scope of the invention.
  • the entries of the TAT only include translation addresses.
  • the TAT entries do not include source addresses. Therefore, the TAT consumes less memory space.
  • the translator provides instructions, to the first block of instructions to use the hash value generated in block 214 and fetch a translation address from the TAT.
  • the order of execution continues at the block of instructions corresponding to the translation address obtained from the TAT.
  • the translator stores the translated first block of instructions, including the instructions appended to the first translated block of instruction by the Translator in blocks 206-216, in the area of memory allocated for storing Binary Translated blocks of instructions.
  • the translation address of the translated first block of instructions is stored in the Alternative Translated Address Memory Area.
  • the translation address for the translated first block of instructions may be copied from the Alternative Translated Address Memory Area into the TAT if the translated first block of instructions is considered to be frequently used.
  • FIG. 3 a flow diagram is shown describing the steps of a translated block of instructions verifying whether it is the correct translated block of instructions following a translated predecessor block of instructions in an order of execution according to one embodiment of the present invention.
  • a first translated block of instructions is executed on the target instruction set computer architecture up to the branch instruction.
  • decision block 304 it is determined whether the branch is to be taken. If the branch is to be taken, in block 306 the first translated block of instructions loads the source address for the block of instructions that is a branch target of the first block of instructions. Otherwise, in block 308 the first translated block of instructions loads the source address for the block of instructions that follows the first block in the static sequence of an untranslated source program.
  • the translated first block of instructions generates a hash value of the source address chosen in either block 306 or 308 in order to find an entry in the TAT to obtain a translation address of a block of instructions that is expected to follow in the order of execution. If no translation address is stored in the entry of the TAT corresponding to the hash value of the chosen source address, then the TAT provides an address defaulting to the alternative look-up routine.
  • execution of the program continues at a second translated block of instructions corresponding to a translation address obtained from the TAT.
  • the second translated block of instructions loads a copy of its source address into a register or other memory location.
  • the second translated block of instructions compares its source address with the source address provided by the first translated block of instructions.
  • the second translated block of instructions does not follow the first block instructions in the order of execution. Therefore, in block 320 the second block of instructions branches into the alternative look-up routine in order to find the correct translated block of instructions that follows the first block of instructions in the order of execution.
  • the order in which the second translated block of instructions verifies whether it is the correct block of instructions following the first translated block of instructions in the order of execution can vary from the order described in blocks 302-320 without departing from the scope of the invention.
  • the scheduling parallelism may be improved when executed on a multiscalar machine.
  • the instructions in the translated predecessor block of instructions which cause the branch into the next block of instructions can be scheduled concurrently with the main body of the translated predecessor block of instructions because validation is necessary prior to branching into the next block of instructions.

Abstract

A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.

Description

FIELD OF THE INVENTION
The invention relates to computer systems, and, in particular, increasing the performance of verifying binary translated blocks of instructions.
BACKGROUND OF THE INVENTION
Most often, computer program statements are decoded into machine instructions that a microprocessor can recognize and execute. The machine instructions are selected from a set of machine instructions unique to a particular instruction set architecture.
Computer program statements that have been decoded into machine instructions for a source instruction set computer architecture, such as the Intel ® X86, may undergo a binary translation in order to be executed on a target instruction set computer architecture, such as the reduced instruction-set computer (RISC) architecture or the very long instruction word (VLIW) architecture.
The machine instructions are typically translated and stored in memory in a separate block of instructions. Each block of instructions consist of a contiguous sequence of non-branch machine-instructions ending with a branch instruction. A computer program, such as the Untranslated Source program of FIG. 1, typically consists of multiple blocks of instructions stored in a physical static sequence (e.g., BB1, BB2, BB3. . . )
The order that the blocks of instructions are executed (i.e. order of execution) can be different from the static sequence. The execution order is determined by the behavior of the branch instructions in the block of instructions.
When the branch instruction is taken, the order of execution branches (i.e., transfers) to a separate block of instructions that is separate in the static sequence of the program. Otherwise, the order of execution continues at the block of instructions that immediately follows in the static sequence. Consider, for example, in the Untranslated Source Program shown in FIG. 1, if the branch instruction of BB1 is taken, the order of execution branches from BB1 to BB3. BB2, therefore, is not executed in the example order of execution.
The block of instructions from which the order of execution continues from is hereinafter referred to as a "predecessor" block of instructions, regardless whether the branch is taken. In the given order of execution example above, BB1 would be considered a predecessor block of instructions with respect to BB3.
To continue the order of execution when executing a binary translation of a program, a predecessor block of instructions needs to obtain a memory address for the translation of a block of instructions that follows in the order of execution. The memory address of a translated block of instructions is hereinafter referred to as the translation address.
The speed of obtaining translation addresses is increased by storing translation addresses in a special section of memory referred to as the Translated Address Table (TAT), such as the one shown in the memory of FIG. 1.
If a translation address is not found in the TAT, a slower alternative look-up routine is accessed. The alternative look-up routine typically involves searching the contents of a larger data structure in memory, which stores a greater number of translation addresses.
The translation addresses stored in the TAT are typically indexed by the hash values of the memory addresses for the corresponding block of instructions untranslated (hereinafter referred to as the source addresses). Consider the example of using the 12 least significant bits (LSB) of source addresses to index the entries of the TAT. If a particular block of instructions has a source address with the 12 LSB equal to 25, than the translation address for that block of instructions would be stored at the 25th entry of the TAT.
It is possible, however, for the source addresses of two or more blocks of instructions to have the same hash value. As such, it is necessary to verify that a translation address obtained from the TAT is the correct translation address for the block of instructions that is to follow a predecessor block of instructions in the order of execution.
SUMMARY AND OBJECTS OF THE INVENTION
The present invention provides a method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
BRIEF DESCRIPTION OF THE DRAWINGS
One embodiment of the invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
FIG. 1 illustrates a computer system capable of implementing one embodiment of the present invention.
FIG. 2 is a flow diagram describing the steps of implementing one embodiment of the present invention.
FIG. 3 is a flow diagram describing the steps of performing one embodiment of the present invention.
DETAILED DESCRIPTION
A method is described for increasing the performance of verifying whether a binary translated block of instructions follows a predecessor translated block of instructions in the order of execution.
Shown in FIG. 1, is a target instruction set computer architecture capable of performing the present invention. Included in the memory of FIG. 1 is the Untranslated Source Program consisting of multiple untranslated blocks of instructions. These blocks of instructions are executable on a separate source instruction set computer architecture.
The binary translator, also shown in the memory of FIG. 1, translates the untranslated blocks of instructions, block by block, so that the instructions are executable on the target instruction set computer architecture. The translator translates each untranslated instruction by decoding each untranslated instruction into an opcode and operands. The opcode indicates an operation to be performed by the instruction, and the operands identify the memory or register addresses of data to be operated on by the opcode.
The translator then provides a separate sequence of instructions in place of a decoded instruction's opcode. The instructions provided by the translator are selected from the target instruction set computer architecture's instruction set and typically achieve the same operation as the decoded instruction's opcode. The translator also translates the memory addresses of the decoded instruction's operands to be compatible with the target computer architecture memory addressing. In addition, in one embodiment of the invention, the translator appends to the translated block of instructions additional instructions that enable a translated block of instructions to verify whether it is the correct translated block of instructions following the predecessor block of instructions in the order of execution.
After the translator has translated a block of instructions to be executable on the target instruction set computer architecture, the translated block of instructions are stored in the area of memory allocated for storing Binary Translated Blocks of Instructions, shown in FIG. 1. Afterwards, during the execution of the translated blocks of instructions, the memory address for each translated block of instructions (i.e., translation address) is obtained from the Translation Address Table, also shown in the memory of FIG. 1.
The binary translator, Untranslated Source Program, binary Translated Blocks of Instructions, and the TAT shown stored in the memory, can also be stored on other computer-readable mediums, such as magnetic disks or optical disks, accessible via a disk drive. These items may also be stored on a cache memory.
Referring to FIG. 2, a flow diagram is shown describing the steps of translator enabling a translated block of instructions to verify whether it is the correct translated block of instructions following a translated predecessor block of instructions in an order of execution, according to one embodiment of the present invention.
In block 202, an untranslated first block of instructions is identified by a program counter during the translation of an untranslated program. In block 204, the binary translator begins translating the untranslated first block instructions into a translated block of instructions that is executable with the target instruction set computer architecture. The translation may be performed dynamically during the execution of the untranslated block of instructions, or statically when the block of instructions is not being executed.
In block 206, the translator provides a compare instruction to have the first block of instructions compare its source address with a source address provided by a predecessor block of instructions. The source address provided by the predecessor block of instructions is the source address of the block of instructions that should follow the predecessor block of instructions in the order of execution.
In block 208, the translator provides to the first block of instructions a branching instruction to branch to an alternative look-up routine if the source address of the first block of instructions is not equal to the source address provided by the predecessor block of instructions.
In one embodiment of the present invention, the alternative look-up routine is a procedure stored in the binary translator. The alternative look-up routine may obtain the translation addresses by searching a larger section of memory allocated to storing translation addresses of binary translated blocks of instructions (hereinafter referred to as the Alternative Translation Address Memory Area) as shown in the memory of FIG. 1.
In block 210 the translator sequentially performs a binary translation of each remaining untranslated instruction included in the first block of instructions.
In block 212, the translator provides to the first block of instructions, a loading instruction to load the source address of the block of instructions that is to follow the first block of instructions in the order of execution. The source address is typically loaded into a memory location that may be a register of a processor, a cache memory location, or a main memory address location.
The actual source address that is loaded depends on the results of the conditional branch instruction when executing the first block of instructions. If the branch is to be taken, then source address for the block of instructions that is a branch target of the first block of instructions is loaded. Otherwise, the source address of the block for instructions that follows the first block of instructions in the static sequence of the Untranslated Source Program.
For example, in FIG. 1, if the conditional branch instruction of the translated BB2 is taken then the source address for BB4 is loaded. On the other hand, if the conditional branch instruction of BB2 is not taken, then the source address for BB3 is loaded.
Therefore, when executing the translated blocks of instructions, the source address loaded by the first block of instructions can subsequently be used by a second translated block of instructions to verify whether the second translated block of instructions correctly follows the first block of instructions in the order of execution. As will be further explained, the second translated block of instructions compares its source address with the source address provided by the first block of instructions to perform the verification.
In block 214, the translator adds an instruction, to the first block of instructions, to generate an index into the TAT. The index is used to obtain the translation address for the block of instructions that is to follow in the order of execution.
In one embodiment, the index generated is a hash value of the source address loaded by the first block of instructions. The hash value generated is the 12 LSB of the source address. The 12 LSB of the source address is then used to locate an entry in the TAT corresponding to the 12 LSB. In alternative embodiments, other hash values may be generated from the source address loaded by the first block of instructions without departing from the scope of the invention.
In the present invention, the entries of the TAT only include translation addresses. The TAT entries do not include source addresses. Therefore, the TAT consumes less memory space.
In block 216, the translator provides instructions, to the first block of instructions to use the hash value generated in block 214 and fetch a translation address from the TAT. The order of execution continues at the block of instructions corresponding to the translation address obtained from the TAT.
In block 218, the translator stores the translated first block of instructions, including the instructions appended to the first translated block of instruction by the Translator in blocks 206-216, in the area of memory allocated for storing Binary Translated blocks of instructions. The translation address of the translated first block of instructions is stored in the Alternative Translated Address Memory Area. In one embodiment, when executing the binary translated blocks of instructions, the translation address for the translated first block of instructions may be copied from the Alternative Translated Address Memory Area into the TAT if the translated first block of instructions is considered to be frequently used.
In alternative embodiments the instructions appended to the block of instructions during the translation could be appended in an order other than the order described in blocks 206-216 without departing from the scope of the invention.
Referring to FIG. 3, a flow diagram is shown describing the steps of a translated block of instructions verifying whether it is the correct translated block of instructions following a translated predecessor block of instructions in an order of execution according to one embodiment of the present invention.
In block 302, a first translated block of instructions is executed on the target instruction set computer architecture up to the branch instruction. In decision block 304, it is determined whether the branch is to be taken. If the branch is to be taken, in block 306 the first translated block of instructions loads the source address for the block of instructions that is a branch target of the first block of instructions. Otherwise, in block 308 the first translated block of instructions loads the source address for the block of instructions that follows the first block in the static sequence of an untranslated source program.
In block 310, the translated first block of instructions generates a hash value of the source address chosen in either block 306 or 308 in order to find an entry in the TAT to obtain a translation address of a block of instructions that is expected to follow in the order of execution. If no translation address is stored in the entry of the TAT corresponding to the hash value of the chosen source address, then the TAT provides an address defaulting to the alternative look-up routine.
In block 312, execution of the program continues at a second translated block of instructions corresponding to a translation address obtained from the TAT. In block 314, the second translated block of instructions loads a copy of its source address into a register or other memory location. In decision block 316, the second translated block of instructions compares its source address with the source address provided by the first translated block of instructions.
If the source addresses are equal, the second block of instructions correctly follows the first block of instructions in the order of execution. Therefore, in block 318 execution of the second translated block of instructions continues.
If the source addresses are not equal, the second translated block of instructions does not follow the first block instructions in the order of execution. Therefore, in block 320 the second block of instructions branches into the alternative look-up routine in order to find the correct translated block of instructions that follows the first block of instructions in the order of execution.
In alternative embodiments, the order in which the second translated block of instructions verifies whether it is the correct block of instructions following the first translated block of instructions in the order of execution can vary from the order described in blocks 302-320 without departing from the scope of the invention.
By enabling a translated block of instructions to verify whether it is the correct translated block of instructions following a translated predecessor block of instructions in an order of execution, the scheduling parallelism may be improved when executed on a multiscalar machine. For example, the instructions in the translated predecessor block of instructions which cause the branch into the next block of instructions can be scheduled concurrently with the main body of the translated predecessor block of instructions because validation is necessary prior to branching into the next block of instructions.
In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.

Claims (14)

What is claimed is:
1. A computer-implemented method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution the method comprising the steps of:
a) appending a compare instruction to the first block of instructions, the compare instruction when executed compares a first value from the first block of instructions with a second value from the second block of instructions, said second block of instructions preceding said first block of instructions in the order of execution; and
b) appending a branching instruction to the first block of instructions, said branching instruction is executed in response to the first value being unequal to the second value, said branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
2. The computer-implemented method of claim 1, further including the step of:
c) appending a load instruction to the second block of instructions, the load instruction when executed loads the second value in a memory location.
3. The computer-implemented method of claim 2, wherein the compare and branching instructions are appended to the first block of instructions when the first block of instructions is translated from being executable on a source instruction set computer architecture to being executable on a target instruction set computer architecture; and
the load instruction is appended to the second block of instructions when the second block of instructions is translated from being executable on the source instruction set computer architecture to being executable on the target instruction set computer architecture.
4. The computer-implemented method of claim 3, wherein the first value is a memory address for the first block of instructions executable on the source instruction set computer architecture.
5. The computer-implemented method of claim 4, wherein the second value is a memory address for the block of instructions, executable on the source instruction set computer architecture, that follows the second block of instructions in the order of execution.
6. The computer-implemented method of claim 5, wherein the step of appending the load instruction to the second block of instructions further includes appending a fetch instruction to the second block of instructions, the fetch instruction when executed obtains a memory address for the first block of instructions executable on the target instruction set computer architecture, said memory address for the first block of instructions executable on the target instruction set computer architecture is obtained from a translated address table.
7. The computer-implemented method of claim 6, wherein each entry of the translated address table is exclusive of a memory address for blocks of instructions executable on the source instruction set computer architecture.
8. A computer-readable medium having stored thereon a plurality of sequences of instructions, the plurality of sequences of instructions including a first sequence of instruction for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions, the first sequence of instructions when executed by a processor, cause said processor to perform the steps of:
a) appending a compare instruction to the first block of instructions, the compare instruction when executed compares a first value from the first block of instructions with a second value from the second block of instructions, said second block of instructions preceding said first block of instructions in the order of execution; and
b) appending a branching instruction to the first block of instructions, said branching instruction is executed in response to the first value being unequal to the second value, said branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
9. The computer-readable medium of claim 8, where in the first sequence of instructions stored thereon further includes additional instructions, which when executed by a processor, cause the processor to perform the step of:
c) appending a load instruction to the second block of instructions, the load instruction when executed loads the second value in a memory location.
10. The computer-readable medium of claim 9, wherein the compare and branching instructions are appended to the first block of instructions when the first block of instructions is translated from being executable on a source instruction set computer architecture to being executable on the target instruction set computer architecture; and
the load instruction is appended to the second block of instructions when the second block of instructions is translated from being executable on the source instruction set computer architecture to being executable on the target instruction set computer architecture.
11. The computer-readable medium of claim 10, wherein the first value is a memory address for the first block of instructions executable on the source instruction set computer architecture.
12. The computer-readable medium of claim 11, wherein the second value is a memory address for the block of instructions, executable on the source instruction set computer architecture, that follows the second block of instructions in the order of execution.
13. The computer-readable medium of claim 12, wherein the step of appending the load instruction to the second block of instructions further includes appending a fetch instruction to the second block of instruction, the fetch instruction when executed obtains a memory address for the first block of instructions executable on the target instruction set computer architecture, said memory address for the first block of instructions executable on the target instruction set computer architecture is obtained from a translated address table.
14. The computer-readable medium of claim 13, wherein each entry of the translated address table is exclusive of a memory address for blocks of instructions executable on the source instruction set computer architecture.
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