US5965914A - Thin film transistor having a branched gate and channel - Google Patents
Thin film transistor having a branched gate and channel Download PDFInfo
- Publication number
- US5965914A US5965914A US08/996,811 US99681197A US5965914A US 5965914 A US5965914 A US 5965914A US 99681197 A US99681197 A US 99681197A US 5965914 A US5965914 A US 5965914A
- Authority
- US
- United States
- Prior art keywords
- gate
- channel
- branch
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title abstract description 65
- 239000004065 semiconductor Substances 0.000 claims description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 104
- 229920005591 polysilicon Polymers 0.000 claims description 104
- 239000000758 substrate Substances 0.000 claims description 43
- 239000010410 layer Substances 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 description 357
- 238000000034 method Methods 0.000 description 114
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 108
- 229910052581 Si3N4 Inorganic materials 0.000 description 61
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 61
- 235000012239 silicon dioxide Nutrition 0.000 description 54
- 239000000377 silicon dioxide Substances 0.000 description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 50
- 229910052710 silicon Inorganic materials 0.000 description 50
- 239000010703 silicon Substances 0.000 description 50
- 238000005530 etching Methods 0.000 description 40
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 36
- 238000006243 chemical reaction Methods 0.000 description 35
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 18
- 238000010586 diagram Methods 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
Definitions
- the present invention relates to a semiconductor device formed by a semiconductor thin film, and a method of fabricating such a semiconductor device.
- a polysilicon thin-film transistor (hereinafter referred to as TFT) is employed as a load element in a low-power SRAM.
- the TFT must take a small area and have a large current capacity to form an SRAM having an improved ability and a high degree of integration.
- the conventional gate all around TFT with a gate electrode wound around a channel polysilicon film has current capacity twice that of a single-gate TFT having the same area.
- FIGS. 49 to 51 show a conventional polysilicon thin film transistor.
- FIG. 49 is a perspective view of the thin-film transistor
- FIG. 50 is a sectional view taken on line A-A' in FIG. 49
- FIG. 51 is a sectional view taken on line B-B' in FIG. 49.
- FIGS. 49 to 51 Shown in FIGS. 49 to 51 are a silicon substrate 1, a silicon dioxide film 2 formed on a surface of the silicon substrate 1, a channel polysilicon film 6 serving as the channel of a thin-film transistor, a silicon dioxide film 7 formed over the surface of the polysilicon film 6 and the surface of the silicon dioxide film 2, and a gate polysilicon film 8 serving as the gate of the thin-film transistor.
- the silicon dioxide film 7 between the channel polysilicon film 6 and the gate polysilicon film 8 serves as the gate oxide film of the thin-film transistor.
- the gate 8 consists of a bottom branch gate 8a formed on a surface of an insulating film, and a branch gate 8b branching from the bottom branch gate 8a, extending over the bottom branch gate 8a and having through holes extending therebetween.
- the channel 6 is formed so as to branch from one side of the branch gates 8a and 8b, i.e., from one side of the through hole of the gate 8, and pass the through hole of the gate 8.
- a gate oxide film 7 is formed between the channel 6, and the branch gates 8a and 8b.
- a source/drain region is connected to the channel 6 on the sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
- FIGS. 52 to 56 are views for explaining a method of fabricating the foregoing conventional semiconductor device. The conventional semiconductor device fabricating method will be described with reference to FIGS. 52 to 56.
- a silicon dioxide film 2 of a predetermined thicknesses formed on a silicon substrate 1 by, for example, a thermal oxidation process.
- a silicon nitride film 3 of a predetermined thickness is deposited by, for example, a reduced pressure CVD process. Then, the silicon nitride film is patterned in a strip of a width corresponding to that of the channel of a desired 5 transistor.
- polysilicon is deposited over the surface of the workpiece to form a channel silicon film 6.
- Polysilicon not containing any impurity is deposited in a polysilicon film of a predetermined thickness, and the polysilicon film is patterned by a photolithographic etching process to form the channel silicon film 6 of a desired pattern.
- the silicon nitride film 3 is removed entirely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Consequently, an opening is formed in the channel silicon film 6.
- a gate silicon dioxide film 7 of a predetermined thickness i.e., a gate insulating film, is deposited over the entire surface of the workpiece so as to cover a first silicon dioxide film 1 and the channel silicon film 6 entirely.
- a gate polysilicon film 8 doped with phosphorus i.e. doped polysilicon film
- a reduced pressure CVD process is deposited in a predetermined thickness over the entire surface of the workpiece by a reduced pressure CVD process.
- the opening formed in the channel silicon film 6 is filled up with the second polysilicon film 8 because the film deposited by the reduced pressure CVD process has an excellent coverage.
- the gate polysilicon film 8 is patterned by a photolithographic etching process in a desired pattern to form a gate electrode.
- source/drain implantation is carried out for end portions of the channel silicon film 6 by using the gate electrode 8 superposed on the channel silicon film 6 as a mask.
- An interlayer insulating film is formed, and wiring lines, such as aluminum lines, are formed so as to extend from the source/drain region to complete a 10 desired transistor, although not shown.
- the foregoing gate all around TFT,having the gate electrode wound around the channel polysilicon film has a current capacity twice that of a single-gate TFT taking the same area. If the degree of integration of a low power SRAM increases, a TFT having a smaller area and a greater current capacity is required. However, the conventional TFT is unable to comply satisfactorily with such a request.
- the present invention has been made in view of such a problem and it is an object of the present invention to provide a semiconductor device. More specifically, a semiconductor device having a thin-film transistor, taking a relatively small area and having a large current capacity.
- a semiconductor device comprises a semiconductor substrate and an insulating film formed on a surface of the semiconductor substrate.
- a gate is provided which includes a bottom branch gate extended on a surface of the insulating film.
- the gate further includes a plurality of branch gates branching from the bottom branch gate, extending over the bottom branch gate.
- a plurality of gate through-holes are provided between each of the bottom branch gates and plurality of branch gates.
- a channel is provided which branches from one side of the gate through-holes, and has a plurality of branch channels passing the gate through-holes.
- the plurality of branch channels are unified on the other side of the gate through-holes.
- a gate insulating film is formed between the gate and the channel. Further, each source/drain region is formed so as to be connected to the channel on the opposite sides of the gate through-holes.
- a semiconductor device comprises a semiconductor substrate and an insulating film formed on a surface of the semiconductor substrate.
- a gate is provided which includes a bottom branch gate formed on a surface of the insulating film so as to form a tunnel on the insulating film.
- the gate further includes at least one other branch gate branching from end extending over the bottom branch gate.
- At least one gate through-hole is provided between each of the bottom branch gate end the other branch gates.
- a channel is provided which includes a bottom branch channel branching from one side of the gate through-hole and passing the tunnel.
- the channel further includes at least one other branch channel passing the gate through-holes.
- the bottom branch channel and the other branch channels are united on the other side of the gate through-holes. Further, each source/drain region is connected to the channel on the opposite sides of the gate through-holes.
- a semiconductor device comprises a semiconductor substrate and an insulating film formed on a surface of the semiconductor substrate.
- a gate is provided which includes a bottom branch channel formed on a surface of the insulating film.
- the channel further includes a plurality of other branch channels branching from and extending over the bottom branch charnel.
- a plurality of channel through-holes are provided between each of the bottom branch channel and the other branch charnels.
- Each source/drain region is formed so as to be connected to the channel on the opposite ends of the channel.
- a gate is provided which includes a branching from one side of the channel through-holes and passing the channel through-holes. The plurality of branch gates are united on the other side of the channel through-holes.
- the selected branch channels other than the uppermost branch channel may be divided into a plurality of sections with gaps therebetween, and the branch gates extend in the gaps.
- the channel and/or the gate are preferably composed of a single-Layer conductive film respectively.
- the channel and/or the gate are preferably composed of polysilicon film respectively.
- the branch channels and the branch gates are preferably formed so as to extend perpendicularly to each other in a three-dimensional way.
- FIGS. 1 to 3 are views for explaining the structure of a semiconductor device in a first embodiment of the present invention.
- FIG. 1 is a perspective view of a thin-film transistor.
- FIGS. 2 and 3 are sectional views.
- FIGS. 4 to 9 are views for explaining a semiconductor device fabricating method in a second embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 1 to 3.
- FIGS. 10 to 12 are views for explaining the structure of a semiconductor device in a third embodiment of the present invention.
- FIG. 10 is a perspective view of a thin-film transistor.
- FIGS. 11 and 12 are sectional views.
- FIGS. 13 to 17 are views for explaining a semiconductor device fabricating method in a fourth embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 10 to 12.
- FIGS. 18 to 20 are views for explaining a semiconductor device in a fifth embodiment of the present invention.
- FIG. 18 is a perspective view of a thin-film transistor.
- FIGS. 19 and 20 are sectional views.
- FIGS. 21 to 25 are views for explaining a semiconductor device fabricating method in a sixth embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 18 to 20.
- FIGS. 26 to 28 are views for explaining a structure of a semiconductor device in a seventh embodiment of the present invention.
- FIG. 26 is a perspective view of a thin-film transistor.
- FIGS. 27 and 28 are sectional views.
- FIGS. 29 to 34 are views for explaining a semiconductor device fabricating method in an eighth embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 26 to 28.
- FIGS. 35 to 37 are views for explaining a structure of a semiconductor device in a ninth embodiment of the present invention.
- FIG. 35 is a perspective view of a thin-film transistor.
- FIGS. 36 and 37 are sectional views.
- FIGS. 38 to 41 are views for explaining a semiconductor device fabricating method in a tenth embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 35 to 37.
- FIGS. 42 to 44 are views for explaining a structure of a semiconductor device in an eleventh embodiment of the present invention.
- FIG. 42 is a perspective view of a thin-film transistor.
- FIGS. 43 and 44 are sectional views.
- FIGS. 45 to 48 are views for explaining a semiconductor device fabricating method in a twelfth embodiment of the present invention for fabricating the thin-film transistor shown in FIGS. 42 to 44.
- FIGS. 49 to 51 show a conventional polysilicon thin film transistor.
- FIG. 49 is a perspective view of the thin-film transistor.
- FIGS. 50 and 51 are sectional views.
- FIGS. 52 to 56 are views for explaining a method of fabricating the conventional semiconductor device shown in FIGS. 49 to 51.
- FIGS. 1 to 3 are views for explaining the structure of a semiconductor device in a first embodiment according to the present invention.
- FIG. 1 is a perspective view of a thin-film transistor
- FIG. 2 is a sectional view taken on line A-A' in FIG. 1
- FIG. 3 is a sectional view taken on line B-B' in FIG. 1.
- FIGS. 1 to 3 Shown in FIGS. 1 to 3 are a silicon substrate (semiconductor substrate) 1, a silicon dioxide film (insulating film) 2 formed on a surface of the silicon substrate land serving is a base insulating film, a channel polysilicon film 6 serving as the channel of a thin-film transistor, a silicon dioxide film (surface insulating film) 7 formed over the surface of the channel polysilicon film 6 and the surface of the silicon dioxide film 2, and a gate polysilicon film 8 serving as the gate of the thin-film transistor.
- the silicon dioxide film 7 between the channel polysilicon film 6 and the gate polysilicon film 8 serves as the gate oxide film of the thin-film transistor.
- the gate 8 has a bottom branch gate 8a overlying the insulating film 2, and a plurality of branch gates 8b to 8e branching from and extending over the bottom branch gate 8a and having through holes therebetween.
- the channel 6 has branch channels 6a to 6d branching from one side of the branch gates 8a to 8e, i.e., one side of the through holes of the gate 8, end passing the through holes of the gate 8.
- the branch channels 6a to 6d are united on the other side of the branch gates 8a to 8e, i.e., on the other side of the gate through holes.
- the gate oxide film 7 is formed between the branch channels 6a to 6d and the branch gates 8a to 8e.
- a source/drain region is formed at each portion of the channel 6 on the opposite sides of the branch gates 8b to 8e, i.e., on the opposite sides of the through holes of the gate 8.
- the thin-film transistor in the first embodiment thus constructed has a channel area more than four times that of a single-gate TFT taking the same area and a current capacity at least more than eight times that of the single-gate TFT.
- a TFT is employed as a load element (i.e. load transistor) in a SRAM, and the rest of the elements of the SRAM, i.e., a driver transistor and an access transistor, are formed on the semiconductor substrate.
- a driver transistor and an access transistor are first formed on a semiconductor substrate, an insulating film is formed over the driver transistor and the access transistor, a TFT is formed on the insulating film, another insulating film is formed over the TFT, and than wiring lines of aluminum or the like are formed. Therefore, the gate electrodes of the driver transistor and the access transistor underlie the TFT, and the aluminum wiring lines or the like overlie the TFT.
- the channel of the TFT is affected by electric fields created by the electrodes, which may possibly cause the characteristics of the TFT, such as threshold voltage, to vary.
- the channel of the TFT in this embodiment is surrounded by the gates, the channel is not affected by the upper and the lower wiring lines.
- FIGS. 4 to 9 are views for explaining a semiconductor device fabricating method in a second embodiment according to the present invention for fabricating the thin-film transistor explained in the first embodiment.
- a silicon dioxide film 2 (base insulating film) of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 (semiconductor substrate) by, for example, a thermal oxidation process.
- a silicon nitride film 3 (first dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is formed on the silicon dioxide film 2 by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 700 to 800° C.
- the silicon nitride film 3 is patterned in a strip of a width corresponding to that of the channel of the transistor so as to include a transistor forming position (or an element forming position).
- a non-doped polysilicon film 4 (second dummy member) is formed in a predetermined thickness of, for example, 1000 ⁇ over the patterned silicon nitride film 3 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C.
- the polysilicon film 4 is patterned in a desired pattern by a photolithographic etching process so as to intersect the patterned silicon nitride film 3 and to include the element forming position.
- the silicon nitride film is removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Consequently, an opening is formed in the polysilicon film 4.
- a silicon nitride film 5 (third dummy member) is deposited by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C., and the silicon nitride film 5 is patterned in a desired pattern by a photolithographic etching process.
- the polysilicon film 4 is removed completely by, for example, an isotropic etching process. Consequently, an opening is formed in the silicon nitride film 5.
- FIGS. 4 to 6 are repeated to form two openings in the silicon nitride film 5, as shown in FIG. 7.
- the processes illustrated in FIGS. 4 to 6 are repeated once again to form three openings in the silicon nitride film 5, as shown in FIG. 8.
- a plurality of openings are formed in the silicon nitride film 5 by further repeating the processes illustrated in FIGS. 4 to 6.
- Polysilicon not containing any impurity is deposited over the final silicon nitride film 5 (final dummy member) with the plurality of openings.
- a reduced pressure CVD process or the like is used to form a channel polysilicon film 6 (channel conductive film) of a thickness of 400 ⁇ , having a reaction temperature in the range of, for example, 400 to 700° C.
- the polysilicon film 6 is patterned in a desired pattern by a photolithographic etching process so as to intersect the final silicon nitride film 5 and to include the element forming position.
- the silicon nitride film 5 is remove completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution, the silicon dioxide film 2 remains intact. Thus, four openings are formed in the channel silicon film 6.
- a gate silicon dioxide film 7 (surface insulating film) of a predetermined thickness of, for example, 200 ⁇ as a gate insulating film is formed over the entire surface of the workpiece by a reduced pressure CVD process.
- a reaction temperature in the range of, for example, 600 to 700° C., is used so that the base silicon dioxide film 2 and the channel silicon film 6 are covered entirely with the gate silicon dioxide film 7.
- a phosphorus-doped gate polysilicon film 9 i.e. a doped polysilicon film (gate conductive film) of a thickness of about 1000 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD using SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C. Since the film deposited by the reduced pressure CVD process has excellent coverage, the openings formed in the channel silicon film 5 are filled up with the gate polysilicon film 8.
- the gate polysilicon film is patterned in a desired pattern so as to intersect the channel silicon film 6 and to include the element forming position by a photolithographic etching process to form a gate electrode 8 (see FIG. 1).
- the opposite ends of the channel silicon film are subjected to source/drain implantation using the gate electrode 8 superposed on the channel silicon film 6. Then, a layer insulating oxide film is formed, and wiring lines of aluminum or the like are extended from the gate electrode and the source/drain region to complete a desired transistor.
- the thin-film transistor in the second embodiment constructed has a channel area more than four times that of a single-gate TFT, taking the same area and a current capacity at least more than four times that of the single-gate TFT.
- the thin-film transistor illustrated and described above has a current capacity at least more than eight times that of the single-gate TFT.
- the channel of the TFT in this embodiment is surrounded by the gates, the channel is not affected by the upper and the lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process respectively.
- a strip-shaped first dummy member is formed in a region including an element forming position on a base insulating film on a semiconductor substrate (a first step). Then, a strip-shaped second dummy member is formed so as to intersect the first dummy member at the element forming position, and the first dummy member is removed (a second step). A strip-shaped third dummy member is formed so as to intersect the second dummy member at the element forming position, removing the second dummy member (a third step). The first to third steps are repeated by a predetermined number of times to form dummy members over the third dummy members.
- a strip-shaped channel conductive film for a channel is formed so as to intersect the last dummy member at the element forming position, and the last dummy member is removed.
- a surface insulating film is formed over the entire surface of the channel conductive film.
- a strip-shaped gate conductive film for a gate is formed so as to intersect the channel conductive film coated with the surface 5 insulating film at the element forming position.
- each of the channel conductive films and/or the gate conductive films are formed preferably by a single-layer conductive film, respectively. Further, the channel conductive film and/or the gate conductive film are formed preferably by polysilicon film, respectively. Further, the first and the third dummy member are formed preferably by silicon nitride films, and the second dummy member is formed preferably by a polysilicon film. Still further, the channel conductive film and the gate conductive film are formed so as to extend perpendicularly to each other in a three-dimensional way.
- FIGS. 10 to 12 are exemplary diagrams of the structure of a semiconductor device in a third embodiment according to the present invention.
- FIG. 10 is a perspective view of a thin-film transistor
- FIG. 11 is a sectional view taken on lines A-A' in FIG. 10
- FIG. 12 is a sectional view taken on line B-B' in FIG. 10.
- a gate 8 has a bottom branch gate 8a formed on the surface of an insulating film 2 to partially form a tunnel between the insulating film 2 and the bottom branch gate 8a, and a branch gate 8b branching from and extending over the bottom branch gate 8a to form a through hole therebetween, and connected to the bottom branch gate 8a via the through hole.
- a channel 6 has a branch channel 6a branching from one side of the branch gates 8a and 8b, i.e., from one side of the through hole of the gate 8, and passing the tunnel of the gate 8, and a branch channel 6b passing the through hole.
- the branch channels 6a and 6b are united on the other side of the branch gate 8a or 8b, i.e., on the side of the other end of the through hole of the gate 8.
- the branch channels 6a and 6b are separated from the branch gates 8a and 8b by a gate oxide film 7.
- a source/drain region is formed so as to be connected to the channel 6, respectively, on the sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
- the thin-film transistor in the third embodiment constructed has a channel area three times that of a single-gate TFT, taking the same area and a current capacity at least three times that of the single-gate TFT.
- the gate overlies the channel of the TFT in this embodiment, the channel is not affected by the upper wiring lines, and the characteristics of the TFT are not subject to variation.
- FIGS. 13 to 17 are exemplary diagrams of a semiconductor device fabricating method in a fourth embodiment according to the present invention for fabricating the thin-film transistor shown in the third embodiment.
- a silicon dioxide film 2 (base insulating film) of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 by, for example, a thermal oxidation process.
- a polysilicon film 4 (second dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is deposited by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 400 to 700° C. (The fourth embodiment does not have any member corresponding to the first dummy member 3 of the second embodiment.)
- the polysilicon film 4 is patterned in a strip of a width corresponding to that of the channel of the transistor.
- a silicon nitride film 5 (third dummy member) is deposited by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C., and then the silicon nitride film is patterned in a desired pattern by a photolithographic etching process.
- the polysilicon film 4 is removed by, for example, an isotropic polysilicon etching process. Consequently, an opening is formed under the silicon nitride film 5.
- non-doped polysilicon is deposited over the silicon nitride film 5 to form a channel silicon film 6 of a thickness of, for example, 400 ⁇ by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 400 to 700° C. Then, the channel silicon film 6 is patterned in a desired pattern by a photolithographic etching process.
- the silicon nitride film 5 is removed completely as shown in FIG. 17 by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution, the silicon dioxide film 2 remains intact. Thus, an opening is formed in the channel silicon film 6.
- a second silicon dioxide film 7 of a predetermined thickness of, for example, 200 ⁇ , serving as a gate insulating film is formed over the entire surface of the workpiece by a reduced pressure CVD process.
- a reaction temperature in the range of, for example, 600 to 900° C. is used so that the first silicon dioxide film 2 and the channel silicon film 6 are covered entirely with the second silicon dioxide film 7.
- a phosphorus-doped second polysilicon film 8 (i.e. doped polysilicon film) of a thickness of about 1000 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD using SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C. Since films deposited by a reduced pressure CVD process have excellent coverage, the opening formed in the channel silicon film 6 is filled up with the second polysilicon film 8.
- the second polysilicon film 8 is patterned in a desired pattern by a photolithographic etching process (see FIG. 10) to form a gate electrode.
- source/drain implantation is carried out by using the gate electrode 8 formed over the channel silicon film 6 as a mask.
- An interlayer insulating oxide film is formed, and wiring lines of aluminum or the like are extended from the gate electrode and the source/drain regions to complete a desired transistor.
- the thin-film transistor constructed in this embodiment has a channel area three times that of a single-gate TFT, taking the same area and a current capacity at least three times that of the single-gate TFT.
- the thin-film transistor illustrated and described above has a current capacity at least more than eight times that of the single-gate TFT.
- the gate overlies the channel of the TFT in this embodiment, the channel is not affected by the upper wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process, respectively.
- a strip-shaped second dummy member is formed in a region including an element forming position on a base insulating film on a semiconductor substrate. Then, a strip-shaped third dummy member is formed so as to intersect the second dummy member at the element forming position, and removing the second dummy member.
- a strip-shaped channel conductive film for a channel is formed so as to intersect the third dummy member at the element forming position, and the third dummy member is removed.
- a surface insulating film is formed over the entire surface of the channel conductive film.
- a strip-shaped gate conductive film for a gate is formed so as to intersect the channel conductive film coated with the surface insulating film at the element forming position.
- FIGS. 18 to 20 are exemplary diagrams of a semiconductor device in a fifth embodiment according to the present invention.
- FIG. 18 is a perspective view of a thin-film transistor
- FIG. 19 is a sectional view taken on line A-A' in FIG. 18
- FIG. 20 is a sectional view taken on line B-B' in FIG. 18.
- the thin-film transistor has an insulating film 2 provided at an element forming position in its surface with a recess 9.
- a gate 8 has a bottom branch gate 8a formed in a portion of the surface of the insulating film 2 corresponding to the recess 9, and a plurality of branch gates 8b and 8c lying over the bottom branch gate 8a and having a through hole, respectively, therebetween.
- a channel 6 has branch channels 6a and 6b branching from one side of the branch gates 8a to 8c, i.e., from one side of the through hole of the gate 8, and passing each through hole of the gate 8.
- the branch channels 6a and 6b are united on the other side of the branch gates 8a to 8c, i.e., the other side of the through hole.
- the branch channels 6a and 6b are separated from the branch gates 8a to 8c by a gate oxide film 7.
- a source/drain region (not shown) is connected to the channel 6, respectively, on the opposite sides of the branch gates 8b and 8c, i.e., on the opposite sides of the through hole.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the height of steps in this embodiment is reduced by a height corresponding to the depth of the recess 9.
- the channel of the TFT in this embodiment is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the semiconductor device comprises a semiconductor substrate provided with a recess.
- An insulating film is formed on a surface of the recess and on a surface of the semiconductor substrate.
- a gate is provided which includes a bottom branch gate formed so as to extend on the surface of the insulating film formed on the surface of the recess and on the surface of the insulating film.
- the gate further includes a plurality of other branch gates, branching from end extending over the bottom branch gate.
- a plurality of gate through-holes are provided between each of the bottom branch gate end the other branch gates.
- a channel is provided which includes a plurality of branch channels, branching from one side of the gate through-holes and passing the gate through-holes.
- the branch channels are united on the other side of the gate through-holes.
- each of source/drain regions is formed so as to be connected to the channel on the opposite side of the gate through-holes.
- FIGS. 21 to 25 are exemplary diagrams of a semiconductor device fabricating method in a sixth embodiment, according to the present invention, for fabricating the thin-film transistor shown in the fifth embodiment.
- the semiconductor device fabricating method in the sixth embodiment will be described with reference to FIGS. 18 to 20 and 21 to 25.
- a silicon dioxide film 2 of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 by, for example, a thermal oxidation process.
- a resist mask of a desired pattern is formed by a photolithographic process, and part of the silicon dioxide film 2 is removed by an anisotropic dry etching process to form a recess 9 of a predetermined size (see FIG. 21).
- a portion of the silicon dioxide film 2 corresponding to the recess 9 may be completely removed.
- a portion of the surface of the silicon substrate corresponding to the recess 9 is exposed, or some part of the portion of the silicon dioxide film 2 corresponding to the recess 9 may be left unremoved.
- the portion of the surface of the silicon substrate may not be exposed, provided that the recess is formed in a predetermined depth of, for example, about 500 ⁇ .
- the size (or area) of the recess 9 is slightly greater than the size (L and W) of the channel of the thin-film transistor to be fabricated.
- silicon nitride is deposited so as to fill up the recess 9 by a reduced pressure CVD process at a reaction temperature in the range of, for example, 400 to 700° C. to form a silicon nitride film 3 (first dummy member).
- the silicon nitride film 3 is etched back by anisotropic dry etching to remove the silicon nitride film 3 gradually, and etching is stopped when the surface of the oxide film 2 is exposed.
- the silicon nitride film 3 is formed only in the recess 9 and the surface of the workpiece becomes flat.
- a non-doped polysilicon film 4 (second dummy member) of a predetermined thickness of, for example, 1000 ⁇ is deposited by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 400 to 700° C.
- the polysilicon film 4 is patterned in a desired pattern by a photolithographic etching process.
- a silicon nitride film 5 (third dummy member) of a predetermined thickness of, for example about 1000 ⁇ is deposited by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C., and then the silicon nitride film 5 is patterned in a desired pattern by a photolithographic etching process.
- the polysilicon film 4 is removed completely by, for example, an isotropic polysilicon etching process. Consequently, an opening is formed in a structure consisting of the silicon nitride film 3 and the silicon nitride film 5.
- non-doped polysilicon is deposited over the silicon nitride film 5 to form a channel silicon film 6 of a thickness of, for example, 400 ⁇ by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 400 to 700° C. Then, the channel silicon film 6 is patterned in a desired pattern by a photolithographic etching process.
- the silicon nitride films 3 and 5 are removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution, the silicon dioxide film 2 remains intact. Thus, an opening is formed in the channel silicon film 6.
- a silicon dioxide film 7 of a predetermined thickness of, for example, 200 ⁇ serving as a gate insulating film is formed over the entire surface of the workpiece by a reduced pressure CVD process using a reaction temperature in the range of, for example, 600 to 900° C.
- a reaction temperature in the range of, for example, 600 to 900° C.
- a gate polysilicon film 8 (i.e. doped polysilicon film) of a thickness of about 1000 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD using SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C. Since films deposited by a reduced pressure CVD process have excellent coverage, the opening formed in the channel silicon film 6 is filled up with the gate polysilicon film 8.
- the gate polysilicon film 8 is patterned in a desired pattern by a photolithographic etching process (see FIG. 18) to form a gate electrode 8.
- source/drain implantation is carried out by using the gate electrode 8 formed over the channel silicon film 6 as a mask.
- a layer insulating oxide film is formed, and wiring lines of aluminum or the like are extended from the gate electrode and the source/drain region to complete a desired transistor.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the height of the steps is reduced by a height corresponding to the depth of the recess 9 formed in the silicon dioxide film 2.
- the channel of the TFT in this embodiment is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process, respectively.
- a recess is formed in a semiconductor substrate at an element forming position.
- a base insulating film is formed to cover a surface of the recess and a surface of a semiconductor substrate.
- the recess is filled up with a first dummy member.
- a strip-shaped second dummy member is formed so as to extend over the first dummy member filling up the recess, and also the surface of the semiconductor substrate coated with the base insulating film.
- a strip-shaped third dummy member is formed so as to intersect the second dummy member at the element forming position.
- a strip-shaped channel conductive film for a channel is formed so as to intersect the third dummy member at the element forming position, removing the third and the first dummy member.
- a surface insulating film is formed on the surface of the channel conductive film.
- a strip-shaped gate conductive film for a gate is formed so as to intersect the channel conductive film coated with the surface insulating film at the element forming position.
- FIGS. 26 to 28 are exemplary diagrams of a structure of a semiconductor device in a seventh embodiment according to the present invention.
- FIG. 26 is a perspective view of a thin-film transistor
- FIG. 27 is a sectional view taken on line A-A' in FIG. 26
- FIG. 28 is a sectional view taken on line B-B' in FIG. 26.
- a gate 8 has a bottom branch gate 8a formed on the surface of an insulating film 2.
- the gate 8 also has a plurality of branch gates 8b and 8c branching from and lying over the bottom branch gate 8a, having a through hole respectively therebetween.
- a channel 6 has branch channels 6a and 6b branching from one side of the branch gates 8a to 8c, i.e., from one side of the through hole of the gate 8, and passing each through hole of the gate 8.
- the branch channels 6a and 6b are united on the other side of the branch gates 8a to 8c, i.e., the other side of the through hole.
- the branch channels 6a and 6b are separated from the branch gates 8a to 8c by a gate oxide film 7.
- a source/drain region (not shown) is connected to the channel 6, respectively, on the opposite sides of the branch gates 8a and 8c, i.e., on the opposite sides of the through hole.
- the thin-film transistor in the seventh embodiment differs from the thin-film transistor in the first embodiment in the number of branch gates and the number of branch channels, the thin-film transistors in the first end the seventh embodiment are based on the same structural conception.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the channel of the TFT in this embodiment is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- FIGS. 29 to 34 are exemplary diagrams of a semiconductor device fabricating method in an eighth embodiment, according to the present invention, for fabricating the thin-film transistor shown in the seventh embodiment.
- a silicon dioxide film 2 (base insulating film) of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 (semiconductor substrate) by, for example, a thermal oxidation process.
- a silicon nitride film 3 (first dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is formed on the silicon dioxide film 2 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C.
- a polysilicon film 4 (second dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is formed by a reduced pressure CVD process using a reaction temperature in the range of, for example, 600 to 900° C.
- the polysilicon film 4 is patterned in a desired pattern by a photolithographic etching process.
- a silicon nitride film 5 (third dummy member) is formed in a predetermined thickness of, for example, 1000 ⁇ by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C. Then, the silicon nitride film 5 is patterned in a desired pattern by a photolithographic etching process using a resist mask 101.
- the polysilicon film 4 is removed completely by, for example, an isotropic etching process.
- the silicon nitride film 3 is patterned in a desired pattern by an anisotropic etching process. Consequently, an opening is formed in a structure consisting of the first silicon nitride film 3 and the silicon nitride film 5.
- non-doped polysilicon is deposited in a predetermined thickness of, for example, 400 ⁇ over the surface of the workpiece by, for example, a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C. to form a channel silicon film 6.
- the channel silicon film 6 is patterned in a desired pattern by a photolithographic etching process using a resist mask 102.
- the silicon nitride films 3 and 5 are etched by anisotropic etching to remove the silicon nitride films, other than portions thereof. Hence, the openings of the channel silicon film 6 are filled up and then the resist mask 102 is removed (see FIG. 33).
- the silicon nitride films are removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution, the silicon dioxide film 2 remains intact. Thus, an opening is formed in the channel silicon film 6.
- a gate silicon dioxide film 7 of a predetermined thickness of, for example, 200 ⁇ is deposited so as to entirely cover the silicon dioxide film 2 and the channel silicon film 6.
- a reduced pressure CVD process is used with a reaction temperature in the range of, for example, 600 to 900° C.
- a gate polysilicon film 8 (i.e. a doped polysilicon film) of a thickness of, for example, about 1000 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD using SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C. Since films deposited by a reduced pressure CVD process have excellent coverage, the opening formed in the channel silicon film 6 is filled up with the gate polysilicon film 8.
- the gate polysilicon film 8 is patterned in a desired pattern by a photolithographic etching process to form a gate electrode 8 (see FIG. 26).
- source/drain implantation is carried out by using the gate electrode 8 formed over the channel silicon film 6 as a mask.
- An interlayer insulating oxide film is formed, and wiring lines of aluminum or the like are extended from the gate electrode and the source/drain region to complete a desired transistor.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate, TFT taking the same area and a current capacity at least four times that of the single-gate TFT.
- the TFT channel is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process, respectively.
- a first dummy member is formed on a surface of a base insulating film formed on a surface of a semiconductor substrate. Then, a strip-shaped second dummy member is formed in a region including an element forming position on a semiconductor substrate on which the first dummy member is formed. A strip-shaped third dummy member coated with a resist mask is formed so as to intersect the second dummy member at the element forming position. The second dummy member is removed through the resist mask, and the first dummy member is patterned along the third dummy member. A strip-shaped channel conductive film for a channel coated with a resist mask is formed so as to intersect the third dummy member at the element forming position.
- the third dummy member and the patterned first dummy member are patterned by anisotropic etching by using the resist mask. A portion of the third dummy member covered with the channel conductive film and remaining after anisotropic etching is removed, and the first dummy member is removed. A surface insulating film is formed over the entire surface of the channel conductive film. A strip-shaped gate conductive film for a gate is formed so as to intersect the channel conductive film coated with the surface insulating film at the element forming position.
- FIGS. 35 to 37 are exemplary diagrams of a structure of a semiconductor device in a ninth embodiment according to the present invention.
- FIG. 35 is a perspective view of a thin-film transistor
- FIG. 36 is a sectional view taken on line A-A' in FIG. 35
- FIG. 37 is a sectional view taken on line B-B' in FIG. 35.
- a channel 6 included in this thin-film transistor has a bottom branch channel 6a lying on the surface of an insulating film 2, and a plurality of branch channels 6b and 6c branching from and overlying the bottom branch channel 6a.
- a gate 8 has branch gates 8a and 8b branching from one side of the branch channels 6a to 6c, i.e., from one side of a through hole of the channel 6, and passing each through hole of the channel 6, and united on the other side of the branch channels 6a to 6c, i.e., on the other side of the through hole of the channel 6.
- the branch channels 6a to 6c are separated from the branch gates 8a and 8b by a gate oxide film 7.
- a source/drain region (not shown) is connected to the channel 6, respectively, on the opposite sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the TFT channel is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- FIGS. 38 to 41 are exemplary diagrams of a semiconductor device fabricating method in a tenth embodiment according to the present invention for fabricating the thin-film transistor shown in the ninth embodiment.
- a silicon dioxide film 2 of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 by, for example, a thermal oxidation process.
- a silicon nitride film 3 (first dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is formed on the silicon dioxide film 2 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C.
- the silicon nitride film 3 is patterned in the shape of a strip of a width corresponding to the channel of a transistor to be fabricated.
- a non-doped polysilicon film 4 (second dummy member) of a predetermined thickness of, for example, 1000 ⁇ is formed on the silicon nitride film 3 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C.
- the polysilicon film 4 is patterned in a desired pattern by a photolithographic etching process, as shown in FIG. 39.
- the silicon nitride film is removed completely by immersing the workpiece in, for example, a hot phosphoric acid solution of 150° C. Consequently, an opening is formed in the polysilicon film 4.
- a silicon nitride film 5 is formed over the entire surface of the workpiece by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C.
- the silicon nitride film 5 is patterned in a desired pattern by a photolithographic etching process, as shown in FIG. 40.
- the polysilicon film 4 is removed completely by, for example, an isotropic polysilicon etching process. Consequently, an opening is formed in the silicon nitride film 5.
- a gate electrode 8 of polysilicon is formed on the surface of the workpiece.
- a polysilicon film 8 i.e. a doped polysilicon film
- SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C.
- the polysilicon film 8 is patterned in a desired pattern by a photolithographic etching process.
- the silicon nitride film 5 is removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution,the silicon dioxide film 2 remains intact. Thus, an opening is formed in the gate polysilicon film 8.
- a gate silicon dioxide film 7, i.e., a gate insulating film, of a predetermined thickness of, for example, 200 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD process using a reaction temperature in the range of, for example, 600 to 900° C.
- the silicon dioxide film 2 and the gate polysilicon film 8 are coated entirely with the silicon dioxide film 7.
- a non-doped polysilicon is deposited by a reduced pressure CVD process or the like using a reaction temperature in the range of, for example, 400 to 700° C. to form a channel polysilicon film 6 of a predetermined thickness of, for example, 400 ⁇ . Since films deposited by a reduced pressure CVD process have excellent coverage, the opening formed in the gate polysilicon film 8 is filled up with the channel polysilicon film 6.
- the channel polysilicon film 6 is patterned in a desired pattern by a photolithographic etching process to form the channel silicon film 6 (see FIG. 35).
- a resist mask is formed on the channel silicon film 6 by photolithography, and source/drain implantation is carried out by using the thus formed resist mask.
- An interlayer insulating oxide film is formed, and wiring lines of aluminum or the like are extended from the gate electrode and the source/drain region to complete a desired transistor.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT taking the same area and a current capacity at least four times that of the single-gate TFT.
- etching of the gate polysilicon is difficult because of the low etching selectivity between the polysilicon and the oxide film.
- the gate polysilicon film can be etched without difficulty, because the channel polysilicon film is thinner than the gate polysilicon film.
- the TFT channel is surrounded by the gate in this embodiment, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process, respectively.
- a strip-shaped first dummy member is formed in a region including an element forming position on a base insulating film on a semiconductor substrate. Then, a strip-shaped second dummy member is formed so as to intersect the first dummy member at the element forming position, and the first dummy member is removed. A strip-shaped third dummy member is formed so as to intersect the second dummy member at the element forming position, and the second dummy member is removed. A strip-shaped gate conductive film for a gate is formed so as to intersect the third dummy member at the element forming position and removing the third dummy member. A surface insulating film is formed on the gate conductive film. A strip-shaped channel conductive film for a channel is formed so as to intersect the gate conductive film coated with the surface insulating film at the element forming position.
- FIGS. 42 to 44 are exemplary diagrams of a structure of a semiconductor device in an eleventh embodiment according to the present invention.
- FIG. 42 is a perspective view of a thin-film transistor
- FIG. 43 is a sectional view taken on line A-A' in FIG. 42
- FIG. 44 is a sectional view taken on line B-B' in FIG. 42.
- a channel 6 in this thin-film transistor comprises a bottom branch channel 61 lying on the surface of an insulating film 2, parallel bottom branch channels 6a branching from the bottom channel 61 at an element forming position, a side channel 62 continuous with the bottom channel 61, an upper channel 6c continuous with the side channel 62, and parallel middle branch channels 6b branching from the side channel 62, lying over the parallel bottom branch channels 6a.
- a through hole is provided between bottom, middle and upper channels. Further, each bottom branch channel 6a and each middle branch channel 6b lying over the bottom branch channel 6a are spaced from each other.
- a gate 8 has branch gates 8a and 8b branching from one side of the branch channels 6a to 6c, i.e., from one side of the through hole of the channel 6, and passing each through hole of the channel 6, and united on the other side of the branch channels 6a to 6c, i.e., the other side of the through hole of the channel 6. Further, the branch gate is filled in a space between the parallel bottom branch channels 6a, and in a space between the parallel middle branch channels 6b.
- the branch channels 6a to 6c are separated from the branch gates 8a and 8b by a gate oxide film 7.
- a source/drain region (not show) is connected to the channel 6, respectively, on the opposite sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the thickness of the channel film is not less than half the interval between the adjacent channels, the area of the channels is greater than that of a channel when the area taken by the TFT is the same.
- the TFT channel is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- FIGS. 45 to 48 are exemplary diagrams of a semiconductor device fabricating method in a twelfth embodiment, according to the present invention, for fabricating the thin-film transistor shown in the eleventh embodiment.
- a silicon dioxide film 2 of a predetermined thickness of, for example, about 1000 ⁇ is formed on a surface of a silicon substrate 1 by, for example, a thermal oxidation process.
- a silicon nitride film 3 (first dummy member) of a predetermined thickness of, for example, about 1000 ⁇ is formed on the silicon dioxide film 2 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C.
- the silicon nitride film 3 is patterned in the shape of a strip of a width corresponding to the channel of a transistor to be fabricated.
- the silicon nitride film 3 may be patterned in a plurality of parallel strips, if necessary.
- a non-doped polysilicon film 4 (second dummy member) of a predetermined thickness of, for example, 1000 ⁇ is formed on the silicon nitride film 3 by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C. Then, the polysilicon film 4 is patterned in a desired pattern by a photolithographic etching process, as shown in FIG. 46.
- the silicon nitride film 3 is removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Consequently, an opening is formed in the polysilicon film 4.
- a silicon nitride film 5 (third dummy member) is formed over the entire surface of the workpiece by a reduced pressure CVD process using a reaction temperature in the range of, for example, 700 to 800° C., as shown in FIG. 47.
- the silicon nitride film 5 is patterned in a desired pattern by a photolithographic etching process by using a mask employed in etching the silicon nitride film 3.
- the polysilicon film 4 is removed completely by, for example, an isotropic polysilicon etching process. Consequently, an opening is formed in the silicon nitride film 5.
- a gate electrode 8 of polysilicon is formed on the surface of the workpiece, as shown in FIG. 48.
- a polysilicon film 8 i.e. a doped polysilicon film
- SiH4 gas containing PH3 SiH4 gas containing PH3 at a reaction temperature in the range of, for example, 500 to 700° C.
- the polysilicon film 8 is patterned in a desired pattern by a photolitho-graphic etching process.
- the silicon nitride film 5 is removed completely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150° C. Since silicon dioxide films are not corroded by the phosphoric acid solution, the silicon dioxide film 2 remains intact. Thus, an opening is formed in the gate polysilicon film 8, forming gate electrode 8.
- a gate silicon dioxide film 7, i.e., a gate insulating film, of a predetermined thickness of, for example, 200 ⁇ is formed over the entire surface of the workpiece by a reduced pressure CVD process using a reaction temperature in the range of, for example, 600 to 900° C.
- the silicon dioxide film 2 and the gate polysilicon film 8 are coated entirely with the silicon dioxide film 7.
- Non-doped polysilicon is deposited in a predetermined thickness of, for example, 400 ⁇ by a reduced pressure CVD process using a reaction temperature in the range of, for example, 400 to 700° C.
- the opening formed in the gate polysilicon film 8 is filled up with a channel polysilicon film 6, because films deposited by a reduced pressure CVD process have excellent coverage.
- the channel polysilicon film 6 is patterned in a desired pattern by a photolithographic etching process to form a channel silicon film (see FIG. 42).
- a resist mask is formed on the channel silicon film 6 by photolithography, and source/drain implantation is carried out.
- An interlayer insulating oxide film is formed, wiring lines of aluminum or the like is extended from the gate electrode and a source/drain region to complete a desired transistor.
- the thin-film transistor constructed in this embodiment has a channel area four times that of a single-gate TFT, taking the same area, and a current capacity at least four times that of the single-gate TFT.
- the thickness of the channel film is not less than half the interval between the adjacent channels, the area of the channels is greater than that of a channel when the area taken by the TFT is the same.
- the TFT channel is surrounded by the gate, the channel is not affected by the upper and lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film by a single process, respectively.
- a plurality of substantially parallel strip-shaped first dummy members are formed in a region including an element forming position on a base insulating film on a semiconductor substrate.
- a strip-shaped second dummy member is formed so as to intersect the plurality of first dummy members at the element forming position and removing the first dummy members.
- a plurality of substantially parallel strip-shaped third dummy members are formed so as to intersect the second dummy member at the element forming position and removing the second dummy member.
- a strip-shaped gate conductive film for a gate is formed so as to intersect the plurality of third dummy members at the element forming position, and the plurality third dummy member are removed.
- a surface insulating film is formed on the gate conductive film.
- a strip-shaped channel conductive film for a channel is formed so as to intersect the gate conductive film coated with the surface insulating film at the element forming position.
- the channel and the gate have each the plurality of branches, and at least one or all of the branch channels are surrounded by the branch gates in a three dimensional way.
- the semiconductor device has a channel area three or four times (or more) than four times that of a single-gate TFT taking the same area, and a current capacity three or four times (or more) than four times that of the single-gate TFT.
- the semiconductor device, particularly, the thin-film transistor, of the present invention has a small area and has a large current capacity.
- the channel of the semiconductor device is not affected by the upper and/or the lower wiring lines, and the characteristics of the TFT are not subject to variation.
- the channel and the gate can be formed by processing a single conductive film respectively, so that the increase of the steps of the semiconductor device fabricating process can be suppressed.
Abstract
Description
Claims (13)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9161118A JPH118390A (en) | 1997-06-18 | 1997-06-18 | Semiconductor device and its manufacture |
JP9-16118 | 1997-06-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5965914A true US5965914A (en) | 1999-10-12 |
Family
ID=15728951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/996,811 Expired - Lifetime US5965914A (en) | 1997-06-18 | 1997-12-23 | Thin film transistor having a branched gate and channel |
Country Status (5)
Country | Link |
---|---|
US (1) | US5965914A (en) |
JP (1) | JPH118390A (en) |
KR (1) | KR100306178B1 (en) |
DE (1) | DE19803479A1 (en) |
TW (1) | TW401643B (en) |
Cited By (72)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2806833A1 (en) * | 2000-03-27 | 2001-09-28 | St Microelectronics Sa | Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region |
FR2823010A1 (en) * | 2001-04-02 | 2002-10-04 | St Microelectronics Sa | Insulated-gate vertical transistor production comprises forming semiconductor column on semiconductor substrate, and forming insulated semiconductor gate on column sides and substrate upper surface |
US20030094637A1 (en) * | 2000-03-31 | 2003-05-22 | Fujitsu Limited | Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit |
WO2003075355A1 (en) * | 2002-03-01 | 2003-09-12 | Forschungszentrum Jülich GmbH | Self-aligning method for producing a double-gate mosfet |
US20040063286A1 (en) * | 2002-10-01 | 2004-04-01 | Kim Sung-Min | Field effect transistors having multiple stacked channels |
FR2853454A1 (en) * | 2003-04-03 | 2004-10-08 | St Microelectronics Sa | High density MOS transistor with a surrounding grid incorporating one or more thin channels, fabricated without using supplementary masks |
US20040227181A1 (en) * | 2003-05-15 | 2004-11-18 | Yeo Kyoung-Hwan | Multichannel metal oxide semiconductor (MOS) transistors and methods of fabricating the same |
US20040235283A1 (en) * | 2003-05-21 | 2004-11-25 | Advanced Micro Devices, Inc. | Multiple-gate MOS device and method for making the same |
US20040256693A1 (en) * | 2003-05-07 | 2004-12-23 | Tsutomu Sato | Semiconductor device and method of manufacturing the same |
US6864129B2 (en) * | 1999-05-28 | 2005-03-08 | Infineon Technologies Ag | Double gate MOSFET transistor and method for the production thereof |
FR2860099A1 (en) * | 2003-09-18 | 2005-03-25 | St Microelectronics Sa | Field effect transistor fabrication method, involves forming temporary monocrystalline material portion over surface of conducting substrate, and depositing semiconductor material on portion of temporary material |
FR2861501A1 (en) * | 2003-10-22 | 2005-04-29 | Commissariat Energie Atomique | Field effect microelectronics device able to form one or more transistor channels, for integrated circuit applications |
US20050112851A1 (en) * | 2003-11-21 | 2005-05-26 | Lee Sung-Young | Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures |
US20050167650A1 (en) * | 2003-07-31 | 2005-08-04 | Orlowski Marius K. | Transistor having multiple channels |
US20050224880A1 (en) * | 2003-12-26 | 2005-10-13 | Lee Dae W | Multi-gate MOS transistor and method of manufacturing the same |
US20050266645A1 (en) * | 2004-05-25 | 2005-12-01 | Jin-Jun Park | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US20060024874A1 (en) * | 2004-07-30 | 2006-02-02 | Eun-Jung Yun | Methods of forming a multi-bridge-channel MOSFET |
US20060049429A1 (en) * | 2004-09-07 | 2006-03-09 | Sungmin Kim | Field effect transistor (FET) having wire channels and method of fabricating the same |
US20060125018A1 (en) * | 2004-10-11 | 2006-06-15 | Lee Sung-Young | Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same |
US20060216897A1 (en) * | 2005-03-24 | 2006-09-28 | Samsung Electronics Co., Ltd. | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
WO2006108987A1 (en) * | 2005-04-13 | 2006-10-19 | Commissariat A L'energie Atomique | Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels |
US20070029586A1 (en) * | 2005-08-08 | 2007-02-08 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
US20070126035A1 (en) * | 2004-10-21 | 2007-06-07 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
US20070196973A1 (en) * | 2004-05-25 | 2007-08-23 | Samsung Electronics Co., Ltd. | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US20070228372A1 (en) * | 2004-10-19 | 2007-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Fabricating a Body Contact in a Finfet Structure and a Device Including the Same |
US20070241420A1 (en) * | 2006-04-14 | 2007-10-18 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating same |
US20070257322A1 (en) * | 2006-05-08 | 2007-11-08 | Freescale Semiconductor, Inc. | Hybrid Transistor Structure and a Method for Making the Same |
US20080020537A1 (en) * | 2004-09-07 | 2008-01-24 | Samsung Electronics Co., Ltd. | Method of fabricating field effect transistor (FET) having wire channels |
US20080036001A1 (en) * | 2004-01-06 | 2008-02-14 | Samsung Electronics Co., Ltd. | Semiconductor devices having field effect transistors |
US20080237641A1 (en) * | 2004-04-09 | 2008-10-02 | Samsung Electronics Co., Ltd. | Surrounded-Channel Transistors with Directionally Etched Gate or Insulator Formation Regions |
US20080277691A1 (en) * | 2005-12-30 | 2008-11-13 | Commissariat A L'energie Atomique | Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US20090080237A1 (en) * | 2007-09-24 | 2009-03-26 | Commissariat A L'energie Atomique | Sram memory with reference bias cell |
US20090085119A1 (en) * | 2007-09-28 | 2009-04-02 | Commissariat A L'energie Atomique | Double-gate transistor structure equipped with a multi-branch channel |
WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US20100047973A1 (en) * | 2006-12-21 | 2010-02-25 | Commissariat A L'energie Atomique | Method for forming microwires and/or nanowires |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20100230674A1 (en) * | 2006-12-21 | 2010-09-16 | Commissariate A L'energie Atomique | Method for forming non-aligned microcavities of different depths |
US20110014769A1 (en) * | 2007-12-21 | 2011-01-20 | Nxp B.V. | Manufacturing method for planar independent-gate or gate-all-around transistors |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US20110031473A1 (en) * | 2009-08-06 | 2011-02-10 | International Business Machines Corporation | Nanomesh SRAM Cell |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7902014B2 (en) | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7915167B2 (en) | 2004-09-29 | 2011-03-29 | Intel Corporation | Fabrication of channel wraparound gate structure for field-effect transistor |
US7960794B2 (en) | 2004-08-10 | 2011-06-14 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US20120007051A1 (en) * | 2010-07-06 | 2012-01-12 | International Business Machines Corporation | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
CN101673767B (en) * | 2006-03-31 | 2012-05-30 | 海力士半导体有限公司 | Semiconductor device with increased channel area and method for manufacturing the same |
US8193567B2 (en) | 2005-09-28 | 2012-06-05 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
WO2013101004A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
US8617945B2 (en) | 2006-08-02 | 2013-12-31 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8766349B2 (en) | 2009-07-09 | 2014-07-01 | Seoul National University R&Db Foundation | Semiconductor device having stacked array structure, NAND flash memory array using the same and fabrication thereof |
US20160056236A1 (en) * | 2013-08-20 | 2016-02-25 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US9337307B2 (en) | 2005-06-15 | 2016-05-10 | Intel Corporation | Method for fabricating transistor with thinned channel |
US20160380003A1 (en) * | 2015-06-26 | 2016-12-29 | International Business Machines Corporation | Gate all-around finfet device and a method of manufacturing same |
US9590038B1 (en) | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
US9614068B2 (en) | 2015-09-02 | 2017-04-04 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9614034B1 (en) * | 2015-09-17 | 2017-04-04 | United Microelectronics Corp. | Semiconductor structure and method for fabricating the same |
JP2018011070A (en) * | 2013-01-24 | 2018-01-18 | インテル・コーポレーション | Integrated circuit structure, non-planar semiconductor device, and method for manufacturing non-planar semiconductor device |
CN109496363A (en) * | 2017-07-13 | 2019-03-19 | 华为技术有限公司 | Tunneling field-effect transistor device making method and tunneling field-effect transistor device |
US10332809B1 (en) * | 2018-06-21 | 2019-06-25 | International Business Machines Corporation | Method and structure to introduce strain in stack nanosheet field effect transistor |
US10916658B2 (en) * | 2017-11-30 | 2021-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device |
US20210057544A1 (en) * | 2019-08-21 | 2021-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-All-Around Structure with Dummy Pattern Top in Channel Region and Methods of Forming the Same |
US11404325B2 (en) | 2013-08-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19928564A1 (en) * | 1999-06-22 | 2001-01-04 | Infineon Technologies Ag | Multi-channel MOSFET and method for its manufacture |
FR2799305B1 (en) | 1999-10-05 | 2004-06-18 | St Microelectronics Sa | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH ENVELOPING GRID AND DEVICE OBTAINED |
DE10045045C2 (en) | 2000-09-12 | 2002-09-19 | Infineon Technologies Ag | Manufacturing process of field effect transistors in semiconductor integrated circuits |
JP4943576B2 (en) * | 2000-10-19 | 2012-05-30 | 白土 猛英 | MIS field effect transistor and manufacturing method thereof |
KR100508545B1 (en) * | 2002-12-14 | 2005-08-17 | 한국전자통신연구원 | Thin film transistor with vertical structure |
KR100652381B1 (en) | 2004-10-28 | 2006-12-01 | 삼성전자주식회사 | Multi bridge channel field effect transistor comprising nano-wire channels and method of manufacturing the same |
KR100615096B1 (en) | 2004-11-15 | 2006-08-22 | 삼성전자주식회사 | Method of fabricating a MOS transistor having multiple channel |
KR100618900B1 (en) | 2005-06-13 | 2006-09-01 | 삼성전자주식회사 | Mos field effect transistor having a plurality of channels and method of fabricating the same |
KR101020099B1 (en) * | 2008-10-17 | 2011-03-09 | 서울대학교산학협력단 | Semiconductor device having stacked array structure and fabrication method for the same |
JP6162583B2 (en) * | 2013-11-20 | 2017-07-12 | 猛英 白土 | Semiconductor device |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63250155A (en) * | 1987-04-07 | 1988-10-18 | Nec Corp | Manufacture of semiconductor device |
WO1991004574A1 (en) * | 1989-09-21 | 1991-04-04 | Interuniversitair Micro-Elektronica Centrum Vzw | Method of manufacturing a field effect transistor and a semiconductor element |
JPH03133158A (en) * | 1989-10-19 | 1991-06-06 | Toshiba Corp | Electrode forming method for semiconductor device |
JPH04114437A (en) * | 1990-09-04 | 1992-04-15 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH06112482A (en) * | 1992-09-28 | 1994-04-22 | Sanyo Electric Co Ltd | Mos transistor and manufacture thereof |
US5338959A (en) * | 1992-03-30 | 1994-08-16 | Samsung Electronics Co., Ltd. | Thin film transistor with three dimensional multichannel structure |
JPH06265346A (en) * | 1993-03-13 | 1994-09-20 | Casio Comput Co Ltd | Distance-measuring sensor and autofocus adjusting device |
US5372959A (en) * | 1992-07-01 | 1994-12-13 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor having a multi-layer stacked channel and its manufacturing method |
US5583362A (en) * | 1993-09-17 | 1996-12-10 | Mitsubishi Denki Kabushiki Kaisha | Gate all around thin film transistor |
-
1997
- 1997-06-18 JP JP9161118A patent/JPH118390A/en active Pending
- 1997-12-23 US US08/996,811 patent/US5965914A/en not_active Expired - Lifetime
-
1998
- 1998-01-29 DE DE19803479A patent/DE19803479A1/en not_active Ceased
- 1998-02-03 TW TW087101339A patent/TW401643B/en not_active IP Right Cessation
- 1998-02-20 KR KR1019980005383A patent/KR100306178B1/en not_active IP Right Cessation
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63250155A (en) * | 1987-04-07 | 1988-10-18 | Nec Corp | Manufacture of semiconductor device |
WO1991004574A1 (en) * | 1989-09-21 | 1991-04-04 | Interuniversitair Micro-Elektronica Centrum Vzw | Method of manufacturing a field effect transistor and a semiconductor element |
JPH04501937A (en) * | 1989-09-21 | 1992-04-02 | アンテルユニヴェルシテール・ミクロ・エレクトロニカ・サントリュム・ヴェー・ゼット・ドゥブルヴェ | Field effect transistor and semiconductor device manufacturing method |
JPH03133158A (en) * | 1989-10-19 | 1991-06-06 | Toshiba Corp | Electrode forming method for semiconductor device |
JPH04114437A (en) * | 1990-09-04 | 1992-04-15 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US5338959A (en) * | 1992-03-30 | 1994-08-16 | Samsung Electronics Co., Ltd. | Thin film transistor with three dimensional multichannel structure |
US5372959A (en) * | 1992-07-01 | 1994-12-13 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor having a multi-layer stacked channel and its manufacturing method |
JPH06112482A (en) * | 1992-09-28 | 1994-04-22 | Sanyo Electric Co Ltd | Mos transistor and manufacture thereof |
JPH06265346A (en) * | 1993-03-13 | 1994-09-20 | Casio Comput Co Ltd | Distance-measuring sensor and autofocus adjusting device |
US5583362A (en) * | 1993-09-17 | 1996-12-10 | Mitsubishi Denki Kabushiki Kaisha | Gate all around thin film transistor |
Cited By (188)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6864129B2 (en) * | 1999-05-28 | 2005-03-08 | Infineon Technologies Ag | Double gate MOSFET transistor and method for the production thereof |
US6555482B2 (en) | 2000-03-27 | 2003-04-29 | Stmicroelectronics S.A. | Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor |
FR2806833A1 (en) * | 2000-03-27 | 2001-09-28 | St Microelectronics Sa | Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region |
US20030094637A1 (en) * | 2000-03-31 | 2003-05-22 | Fujitsu Limited | Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit |
US6885041B2 (en) * | 2000-03-31 | 2005-04-26 | Fujitsu Limited | Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit |
US7078764B2 (en) | 2001-04-02 | 2006-07-18 | Stmicroelectronics, S.A. | Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor |
FR2823010A1 (en) * | 2001-04-02 | 2002-10-04 | St Microelectronics Sa | Insulated-gate vertical transistor production comprises forming semiconductor column on semiconductor substrate, and forming insulated semiconductor gate on column sides and substrate upper surface |
US6746923B2 (en) | 2001-04-02 | 2004-06-08 | Stmicroelectronics S.A. | Method of fabricating a vertical quadruple conduction channel insulated gate transistor |
US20040266112A1 (en) * | 2001-04-02 | 2004-12-30 | Stmicroelectronics Sa | Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor |
WO2003075355A1 (en) * | 2002-03-01 | 2003-09-12 | Forschungszentrum Jülich GmbH | Self-aligning method for producing a double-gate mosfet |
FR2845203A1 (en) * | 2002-10-01 | 2004-04-02 | Samsung Electronics Co Ltd | FIELD EFFECT TRANSISTOR HAVING MULTIPLE STACKED CHANNELS AND MANUFACTURING METHOD |
CN100456498C (en) * | 2002-10-01 | 2009-01-28 | 三星电子株式会社 | Field effect transistor with multi-superposed channels |
US20040209463A1 (en) * | 2002-10-01 | 2004-10-21 | Kim Sung-Min | Methods of fabricating field effect transistors having multiple stacked channels |
GB2395603B (en) * | 2002-10-01 | 2006-05-03 | Samsung Electronics Co Ltd | Field effect transistors having multiple stacked channels |
US20050189583A1 (en) * | 2002-10-01 | 2005-09-01 | Samsung Electronics Co., Ltd. | Field effect transistors having multiple stacked channels |
US20080090362A1 (en) * | 2002-10-01 | 2008-04-17 | Samsung Electronics Co., Ltd. | Methods of fabricating field effect transistors having multiple stacked channels |
GB2395603A (en) * | 2002-10-01 | 2004-05-26 | Samsung Electronics Co Ltd | Multichannel TFT having gate formed around channels |
US7615429B2 (en) | 2002-10-01 | 2009-11-10 | Samsung Electronics Co., Ltd. | Methods of fabricating field effect transistors having multiple stacked channels |
US7026688B2 (en) | 2002-10-01 | 2006-04-11 | Samsung Electronics Co., Ltd. | Field effect transistors having multiple stacked channels |
US7381601B2 (en) | 2002-10-01 | 2008-06-03 | Samsung Electronics Co., Ltd. | Methods of fabricating field effect transistors having multiple stacked channels |
DE10339920B4 (en) * | 2002-10-01 | 2014-03-13 | Samsung Electronics Co., Ltd. | Method of manufacturing an integrated circuit field effect transistor |
US20040063286A1 (en) * | 2002-10-01 | 2004-04-01 | Kim Sung-Min | Field effect transistors having multiple stacked channels |
US7002207B2 (en) * | 2002-10-01 | 2006-02-21 | Samsung Electronics Co., Ltd. | Field effect transistors having multiple stacked channels |
FR2853454A1 (en) * | 2003-04-03 | 2004-10-08 | St Microelectronics Sa | High density MOS transistor with a surrounding grid incorporating one or more thin channels, fabricated without using supplementary masks |
US7141837B2 (en) | 2003-04-03 | 2006-11-28 | Stmicroelectronics S.A. | High-density MOS transistor |
US20040262690A1 (en) * | 2003-04-03 | 2004-12-30 | Stmicroelectronics S.A. | High-density MOS transistor |
US7372086B2 (en) * | 2003-05-07 | 2008-05-13 | Kabushiki Kaisha Toshiba | Semiconductor device including MOSFET and isolation region for isolating the MOSFET |
US20040256693A1 (en) * | 2003-05-07 | 2004-12-23 | Tsutomu Sato | Semiconductor device and method of manufacturing the same |
US7670912B2 (en) * | 2003-05-15 | 2010-03-02 | Samsung Electronics Co., Ltd. | Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors |
US20040227181A1 (en) * | 2003-05-15 | 2004-11-18 | Yeo Kyoung-Hwan | Multichannel metal oxide semiconductor (MOS) transistors and methods of fabricating the same |
US6919250B2 (en) * | 2003-05-21 | 2005-07-19 | Advanced Micro Devices, Inc. | Multiple-gate MOS device and method for making the same |
US20040235283A1 (en) * | 2003-05-21 | 2004-11-25 | Advanced Micro Devices, Inc. | Multiple-gate MOS device and method for making the same |
US7820513B2 (en) | 2003-06-27 | 2010-10-26 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
US8273626B2 (en) | 2003-06-27 | 2012-09-25 | Intel Corporationn | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US20050167650A1 (en) * | 2003-07-31 | 2005-08-04 | Orlowski Marius K. | Transistor having multiple channels |
US7112832B2 (en) * | 2003-07-31 | 2006-09-26 | Freescale Semiconductor, Inc. | Transistor having multiple channels |
FR2860099A1 (en) * | 2003-09-18 | 2005-03-25 | St Microelectronics Sa | Field effect transistor fabrication method, involves forming temporary monocrystalline material portion over surface of conducting substrate, and depositing semiconductor material on portion of temporary material |
US7297578B2 (en) | 2003-09-18 | 2007-11-20 | Stmicroelectronics S.A. | Method for producing a field effect transistor |
US20050085024A1 (en) * | 2003-09-18 | 2005-04-21 | Stmicroelectronics S.A. | Method for producing a field-effect transistor and transistor thus obtained |
US7902575B2 (en) | 2003-10-22 | 2011-03-08 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
US20090194826A1 (en) * | 2003-10-22 | 2009-08-06 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
FR2861501A1 (en) * | 2003-10-22 | 2005-04-29 | Commissariat Energie Atomique | Field effect microelectronics device able to form one or more transistor channels, for integrated circuit applications |
WO2005041309A1 (en) * | 2003-10-22 | 2005-05-06 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
US7800172B2 (en) | 2003-11-21 | 2010-09-21 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures |
US20050112851A1 (en) * | 2003-11-21 | 2005-05-26 | Lee Sung-Young | Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures |
US20080093628A1 (en) * | 2003-11-21 | 2008-04-24 | Samsung Electronics Co., Ltd. | Methods of Forming Semiconductor Devices Having Multiple Channel MOS Transistors and Related Intermediate Structures |
US7316968B2 (en) | 2003-11-21 | 2008-01-08 | Samsung Electronics Co., Ltd. | Methods of forming semiconductor devices having multiple channel MOS transistors |
US7335945B2 (en) * | 2003-12-26 | 2008-02-26 | Electronics And Telecommunications Research Institute | Multi-gate MOS transistor and method of manufacturing the same |
US20050224880A1 (en) * | 2003-12-26 | 2005-10-13 | Lee Dae W | Multi-gate MOS transistor and method of manufacturing the same |
US7768070B2 (en) * | 2004-01-06 | 2010-08-03 | Samsung Electronics Co., Ltd. | Semiconductor devices having field effect transistors |
US20080036001A1 (en) * | 2004-01-06 | 2008-02-14 | Samsung Electronics Co., Ltd. | Semiconductor devices having field effect transistors |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20080237641A1 (en) * | 2004-04-09 | 2008-10-02 | Samsung Electronics Co., Ltd. | Surrounded-Channel Transistors with Directionally Etched Gate or Insulator Formation Regions |
US7648883B2 (en) | 2004-05-25 | 2010-01-19 | Samsung Electronics Co., Ltd. | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US7309635B2 (en) | 2004-05-25 | 2007-12-18 | Samsung Electronics Co., Ltd | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US7229884B2 (en) | 2004-05-25 | 2007-06-12 | Samsung Electronics Co., Ltd. | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US20070196973A1 (en) * | 2004-05-25 | 2007-08-23 | Samsung Electronics Co., Ltd. | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US20050266645A1 (en) * | 2004-05-25 | 2005-12-01 | Jin-Jun Park | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7402483B2 (en) | 2004-07-30 | 2008-07-22 | Samsung Electronics Co., Ltd. | Methods of forming a multi-bridge-channel MOSFET |
US20060024874A1 (en) * | 2004-07-30 | 2006-02-02 | Eun-Jung Yun | Methods of forming a multi-bridge-channel MOSFET |
US7960794B2 (en) | 2004-08-10 | 2011-06-14 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7274051B2 (en) * | 2004-09-07 | 2007-09-25 | Samsung Electronics Co., Ltd. | Field effect transistor (FET) having wire channels and method of fabricating the same |
US20060049429A1 (en) * | 2004-09-07 | 2006-03-09 | Sungmin Kim | Field effect transistor (FET) having wire channels and method of fabricating the same |
US7374986B2 (en) | 2004-09-07 | 2008-05-20 | Samsung Electronics Co., Ltd. | Method of fabricating field effect transistor (FET) having wire channels |
DE102005038943B4 (en) * | 2004-09-07 | 2011-12-22 | Samsung Electronics Co., Ltd. | Method for producing a field effect transistor (FET) with line channels |
US20080020537A1 (en) * | 2004-09-07 | 2008-01-24 | Samsung Electronics Co., Ltd. | Method of fabricating field effect transistor (FET) having wire channels |
US7915167B2 (en) | 2004-09-29 | 2011-03-29 | Intel Corporation | Fabrication of channel wraparound gate structure for field-effect transistor |
US8399922B2 (en) | 2004-09-29 | 2013-03-19 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US20080233693A1 (en) * | 2004-10-11 | 2008-09-25 | Samung Electronics Co., Ltd. | Complementary metal-oxide semiconductor (cmos) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same |
US7781290B2 (en) | 2004-10-11 | 2010-08-24 | Samsung Electronics Co., Ltd. | Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same |
US20060125018A1 (en) * | 2004-10-11 | 2006-06-15 | Lee Sung-Young | Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same |
US20070228372A1 (en) * | 2004-10-19 | 2007-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Fabricating a Body Contact in a Finfet Structure and a Device Including the Same |
US7943986B2 (en) * | 2004-10-19 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a body contact in a finfet structure and a device including the same |
US7518195B2 (en) | 2004-10-21 | 2009-04-14 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
US20070126035A1 (en) * | 2004-10-21 | 2007-06-07 | Commissariat A L'energie Atomique | Field-effect microelectronic device, capable of forming one or several transistor channels |
US10236356B2 (en) | 2004-10-25 | 2019-03-19 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9741809B2 (en) | 2004-10-25 | 2017-08-22 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9190518B2 (en) | 2004-10-25 | 2015-11-17 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8749026B2 (en) | 2004-10-25 | 2014-06-10 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8502351B2 (en) | 2004-10-25 | 2013-08-06 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9614083B2 (en) | 2005-02-23 | 2017-04-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9748391B2 (en) | 2005-02-23 | 2017-08-29 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8664694B2 (en) | 2005-02-23 | 2014-03-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9368583B2 (en) | 2005-02-23 | 2016-06-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US10121897B2 (en) | 2005-02-23 | 2018-11-06 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8816394B2 (en) | 2005-02-23 | 2014-08-26 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8368135B2 (en) | 2005-02-23 | 2013-02-05 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9048314B2 (en) | 2005-02-23 | 2015-06-02 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US8110471B2 (en) | 2005-03-24 | 2012-02-07 | Samsung Electronics Co., Ltd. | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
US20060216897A1 (en) * | 2005-03-24 | 2006-09-28 | Samsung Electronics Co., Ltd. | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
US20100068862A1 (en) * | 2005-03-24 | 2010-03-18 | Samsung Electronics Co., Ltd. | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
US7642578B2 (en) | 2005-03-24 | 2010-01-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same |
US20080149919A1 (en) * | 2005-04-13 | 2008-06-26 | Commissariat A L'energie Atomique | Structure and Method For Realizing a Microelectronic Device Provided With a Number of Quantum Wires Capable of Forming One or More Transistor Channels |
WO2006108987A1 (en) * | 2005-04-13 | 2006-10-19 | Commissariat A L'energie Atomique | Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels |
FR2884648A1 (en) * | 2005-04-13 | 2006-10-20 | Commissariat Energie Atomique | STRUCTURE AND METHOD FOR PRODUCING A MICROELECTRONIC DEVICE HAVING ONE OR MORE QUANTUM THREADS FOR FORMING A CHANNEL OR MORE CHANNELS OF TRANSISTORS |
US7910917B2 (en) | 2005-04-13 | 2011-03-22 | Commissariat A L'energie Atomique | Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels |
US20110124161A1 (en) * | 2005-04-13 | 2011-05-26 | Commissariat A L'energie Atomique | Structure and method for fabricating a microelectronic device provided with one or more quantum wires able to form one or more transistor channels |
US8367487B2 (en) | 2005-04-13 | 2013-02-05 | Commissariat A L'energie Atomique | Structure and method for fabricating a microelectronic device provided with one or more quantum wires able to form one or more transistor channels |
US9337307B2 (en) | 2005-06-15 | 2016-05-10 | Intel Corporation | Method for fabricating transistor with thinned channel |
US9806195B2 (en) | 2005-06-15 | 2017-10-31 | Intel Corporation | Method for fabricating transistor with thinned channel |
US9385180B2 (en) | 2005-06-21 | 2016-07-05 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US8071983B2 (en) | 2005-06-21 | 2011-12-06 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8933458B2 (en) | 2005-06-21 | 2015-01-13 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US9761724B2 (en) | 2005-06-21 | 2017-09-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8581258B2 (en) | 2005-06-21 | 2013-11-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US20070029586A1 (en) * | 2005-08-08 | 2007-02-08 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
US7354831B2 (en) * | 2005-08-08 | 2008-04-08 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
US7608893B2 (en) | 2005-08-08 | 2009-10-27 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
US20080142853A1 (en) * | 2005-08-08 | 2008-06-19 | Freescale Semiconductor, Inc. | Multi-channel transistor structure and method of making thereof |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US8193567B2 (en) | 2005-09-28 | 2012-06-05 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US8294180B2 (en) | 2005-09-28 | 2012-10-23 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7902014B2 (en) | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US20080277691A1 (en) * | 2005-12-30 | 2008-11-13 | Commissariat A L'energie Atomique | Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions |
US8492232B2 (en) | 2005-12-30 | 2013-07-23 | Commissariat A L'energie Atomique | Production of a transistor gate on a multibranch channel structure and means for isolating this gate from the source and drain regions |
CN101673767B (en) * | 2006-03-31 | 2012-05-30 | 海力士半导体有限公司 | Semiconductor device with increased channel area and method for manufacturing the same |
US20070241420A1 (en) * | 2006-04-14 | 2007-10-18 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating same |
US7709328B2 (en) | 2006-04-14 | 2010-05-04 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating same |
US8373223B2 (en) | 2006-04-14 | 2013-02-12 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
US20100276739A1 (en) * | 2006-04-14 | 2010-11-04 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
US20070257322A1 (en) * | 2006-05-08 | 2007-11-08 | Freescale Semiconductor, Inc. | Hybrid Transistor Structure and a Method for Making the Same |
US8617945B2 (en) | 2006-08-02 | 2013-12-31 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8236698B2 (en) | 2006-12-21 | 2012-08-07 | Commissariat A L'energie Atomique | Method for forming non-aligned microcavities of different depths |
US20100230674A1 (en) * | 2006-12-21 | 2010-09-16 | Commissariate A L'energie Atomique | Method for forming non-aligned microcavities of different depths |
US7985632B2 (en) | 2006-12-21 | 2011-07-26 | Commissariat A L'energie Atomique | Method for forming microwires and/or nanowires |
US20100047973A1 (en) * | 2006-12-21 | 2010-02-25 | Commissariat A L'energie Atomique | Method for forming microwires and/or nanowires |
US7787286B2 (en) | 2007-09-24 | 2010-08-31 | Commissariat A L'energie Atomique | SRAM memory with reference bias cell |
US20090080237A1 (en) * | 2007-09-24 | 2009-03-26 | Commissariat A L'energie Atomique | Sram memory with reference bias cell |
US8288823B2 (en) | 2007-09-28 | 2012-10-16 | Commissariat A L'energie Atomique | Double-gate transistor structure equipped with a multi-branch channel |
US20090085119A1 (en) * | 2007-09-28 | 2009-04-02 | Commissariat A L'energie Atomique | Double-gate transistor structure equipped with a multi-branch channel |
US20100264496A1 (en) * | 2007-11-09 | 2010-10-21 | Comm. A L'Energie Atom. et aux Energies Alterna | Sram memory cell provided with transistors having a vertical multichannel structure |
FR2923646A1 (en) * | 2007-11-09 | 2009-05-15 | Commissariat Energie Atomique | MEMORY CELL SRAM WITH TRANSISTORS WITH VERTICAL MULTI-CHANNEL STRUCTURE |
WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
US8502318B2 (en) | 2007-11-09 | 2013-08-06 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | SRAM memory cell provided with transistors having a vertical multichannel structure |
US7923315B2 (en) * | 2007-12-21 | 2011-04-12 | Nxp B.V. | Manufacturing method for planar independent-gate or gate-all-around transistors |
US20110014769A1 (en) * | 2007-12-21 | 2011-01-20 | Nxp B.V. | Manufacturing method for planar independent-gate or gate-all-around transistors |
US8741733B2 (en) | 2008-06-23 | 2014-06-03 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9224754B2 (en) | 2008-06-23 | 2015-12-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9450092B2 (en) | 2008-06-23 | 2016-09-20 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9806193B2 (en) | 2008-06-23 | 2017-10-31 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8766349B2 (en) | 2009-07-09 | 2014-07-01 | Seoul National University R&Db Foundation | Semiconductor device having stacked array structure, NAND flash memory array using the same and fabrication thereof |
US8395220B2 (en) | 2009-08-06 | 2013-03-12 | International Business Machines Corporation | Nanomesh SRAM cell |
WO2011015440A1 (en) * | 2009-08-06 | 2011-02-10 | International Business Machines Corporation | A nanomesh sram cell |
US8216902B2 (en) | 2009-08-06 | 2012-07-10 | International Business Machines Corporation | Nanomesh SRAM cell |
US20110031473A1 (en) * | 2009-08-06 | 2011-02-10 | International Business Machines Corporation | Nanomesh SRAM Cell |
US9337264B2 (en) | 2010-07-06 | 2016-05-10 | Globalfoundries Inc. | Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric |
US20120007051A1 (en) * | 2010-07-06 | 2012-01-12 | International Business Machines Corporation | Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric |
US9029834B2 (en) * | 2010-07-06 | 2015-05-12 | International Business Machines Corporation | Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric |
US10020371B2 (en) | 2011-12-28 | 2018-07-10 | Intel Corporation | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
US9461141B2 (en) | 2011-12-28 | 2016-10-04 | Intel Corporation | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
WO2013101004A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
TWI489631B (en) * | 2011-12-28 | 2015-06-21 | Intel Corp | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
US9123790B2 (en) | 2011-12-28 | 2015-09-01 | Intel Corporation | Contact techniques and configurations for reducing parasitic resistance in nanowire transistors |
JP2018011070A (en) * | 2013-01-24 | 2018-01-18 | インテル・コーポレーション | Integrated circuit structure, non-planar semiconductor device, and method for manufacturing non-planar semiconductor device |
US10163729B2 (en) * | 2013-08-20 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US9634091B2 (en) * | 2013-08-20 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US11854905B2 (en) | 2013-08-20 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
US20160056236A1 (en) * | 2013-08-20 | 2016-02-25 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US11404325B2 (en) | 2013-08-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and silicon germanium nanowire formation |
US10943833B2 (en) * | 2013-08-20 | 2021-03-09 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US9935016B2 (en) * | 2013-08-20 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Silicon and silicon germanium nanowire formation |
US10699964B2 (en) * | 2013-08-20 | 2020-06-30 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US20170194215A1 (en) * | 2013-08-20 | 2017-07-06 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US20200051870A1 (en) * | 2013-08-20 | 2020-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon and Silicon Germanium Nanowire Formation |
US20190103322A1 (en) * | 2013-08-20 | 2019-04-04 | Taiwan Semiconductor Manufacturing Company Limited | Silicon and silicon germanium nanowire formation |
US20160380003A1 (en) * | 2015-06-26 | 2016-12-29 | International Business Machines Corporation | Gate all-around finfet device and a method of manufacturing same |
US9721970B2 (en) * | 2015-06-26 | 2017-08-01 | International Business Machines Corporation | Gate all-around FinFET device and a method of manufacturing same |
US9929270B2 (en) | 2015-06-26 | 2018-03-27 | International Business Machines Corporation | Gate all-around FinFET device and a method of manufacturing same |
US9614068B2 (en) | 2015-09-02 | 2017-04-04 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9614034B1 (en) * | 2015-09-17 | 2017-04-04 | United Microelectronics Corp. | Semiconductor structure and method for fabricating the same |
US9590038B1 (en) | 2015-10-23 | 2017-03-07 | Samsung Electronics Co., Ltd. | Semiconductor device having nanowire channel |
CN109496363A (en) * | 2017-07-13 | 2019-03-19 | 华为技术有限公司 | Tunneling field-effect transistor device making method and tunneling field-effect transistor device |
US10916658B2 (en) * | 2017-11-30 | 2021-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device |
US11637205B2 (en) | 2017-11-30 | 2023-04-25 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10332809B1 (en) * | 2018-06-21 | 2019-06-25 | International Business Machines Corporation | Method and structure to introduce strain in stack nanosheet field effect transistor |
US20210057544A1 (en) * | 2019-08-21 | 2021-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-All-Around Structure with Dummy Pattern Top in Channel Region and Methods of Forming the Same |
US11152488B2 (en) * | 2019-08-21 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-all-around structure with dummy pattern top in channel region and methods of forming the same |
Also Published As
Publication number | Publication date |
---|---|
DE19803479A1 (en) | 1998-12-24 |
JPH118390A (en) | 1999-01-12 |
KR100306178B1 (en) | 2002-03-08 |
KR19990006350A (en) | 1999-01-25 |
TW401643B (en) | 2000-08-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5965914A (en) | Thin film transistor having a branched gate and channel | |
US8330246B2 (en) | Intermediate structures for forming circuits | |
KR100221115B1 (en) | Fabricating method of semiconductor device | |
JPS6014510B2 (en) | Manufacturing method of V-MOS dynamic semiconductor device | |
US20160233218A1 (en) | Semiconductor device | |
KR100673673B1 (en) | Dram cell arrangement and method for fabricating it | |
JP3229665B2 (en) | Method of manufacturing MOSFET | |
US20210125998A1 (en) | Semiconductor memory device and a method of fabricating the same | |
US6504200B2 (en) | DRAM cell configuration and fabrication method | |
KR20020050115A (en) | Semiconductor memory device with silicide layer formed selectively | |
KR960039222A (en) | Semiconductor device and manufacturing method | |
US5312769A (en) | Method of making a semiconductor memory device | |
US5390144A (en) | Semiconductor memory | |
JPH065814A (en) | Contact matching for integrated circuit | |
US5459341A (en) | Semiconductor device and method of manufacturing the same | |
KR0135690B1 (en) | Fabrication method of contact in semiconductor device | |
US5821573A (en) | Field effect transistor having an arched gate and manufacturing method thereof | |
KR950012033B1 (en) | Method of manufacturing a contact for vlsi device | |
JPH09205187A (en) | Semiconductor device and its manufacture | |
JPS6324657A (en) | Manufacture of semiconductor memory | |
KR100202198B1 (en) | Self align contact fabrication method | |
US7052955B2 (en) | Semiconductor memory device and manufacturing method thereof | |
KR100300063B1 (en) | Manufacturing method for semiconductor memory | |
KR19990014889A (en) | Integrated circuit device having at least two elements insulated from each other, and method of manufacturing the same | |
KR100280526B1 (en) | Semiconductor Memory Manufacturing Method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MIYAMOTO, SHOICHI;REEL/FRAME:008948/0790 Effective date: 19971209 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:025980/0219 Effective date: 20110307 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |