US6320225B1 - SOI CMOS body contact through gate, self-aligned to source- drain diffusions - Google Patents
SOI CMOS body contact through gate, self-aligned to source- drain diffusions Download PDFInfo
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- US6320225B1 US6320225B1 US09/351,647 US35164799A US6320225B1 US 6320225 B1 US6320225 B1 US 6320225B1 US 35164799 A US35164799 A US 35164799A US 6320225 B1 US6320225 B1 US 6320225B1
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- 238000009792 diffusion process Methods 0.000 title description 5
- 239000004020 conductor Substances 0.000 claims abstract description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 32
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 21
- 210000000746 body region Anatomy 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to a semiconductor device, and more particularly to a method for forming a silicon on insulator structured substrate with body-contacts under the gate conductor.
- a further object of the invention is to provide a method and structure for an SOI body-contact that requires only one additional masking level.
- the present invention is directed to a method of forming a silicon on insulator body contact under a gate conductor on a silicon on insulator substrate.
- the method comprises depositing a first insulating layer, such as tetraethoxysilane, over the silicon on insulator substrate.
- An opening is formed in the first insulating layer and extends through the first insulating layer, through the gate conductor to the semiconductor substrate.
- the opening has an insulating spacer on each of its sidewalls which are adjacent the first insulating layer and gate conductor regions.
- the insulating spacers are silicon nitride.
- a layer of a first conductive material is deposited in the opening.
- the first conductive material layer is recessed so that the top of the first conductive material layer maintains electrical contact with a monocrystalline semiconductor layer of the silicon on insulator substrate. It is also preferred to deposit a second insulating material, preferably tetraethoxysilane, over the first conductive material layer.
- the method also comprises depositing a layer of a second conductive material, such as polysilicon, over the second insulating layer and depositing a layer of a metal such as tungsten, titanium or cobalt over the second conductive material layer.
- the metal layer is reacted with the second conductive material layer to form a silicide that is self aligned to the gate conductor.
- the method includes implanting a dopant, such as boron, into the semiconductor substrate at the bottom of the body-contact via.
- a dopant such as boron
- the invention comprises a body contact structure under a gate conductor on a silicon on insulator substrate.
- the preferred embodiment comprises a first insulating layer, such as tetraethoxysilane, lying over, and in electrical contact with, the gate conductor.
- a first insulating layer such as tetraethoxysilane
- there is an opening in the substrate which extends from a top surface of the first insulating layer, through the gate conductor to the semiconductor substrate.
- an insulating spacer is formed on each sidewall of the opening, in the area adjacent the first insulating layer and the gate conductor.
- the insulating spacer is preferably a silicon nitride.
- the opening is filled with a layer of a second insulating material, preferably tetraethoxysilane, on top of the first conductive material layer, which is preferably P+ polysilicon.
- a second conductive material layer such as polysilicon, is over the second insulating layer.
- a salicide is found over the gate conductor.
- a dopant such as boron
- FIG. 1 is a top plan view of the SOI structure of the present invention showing the gate conductor region and nitride spacers.
- FIG. 2 is cross-sectional view of FIG. 1 taken along the line 2 — 2 of FIG. 1 .
- FIG. 3 is a top plan view of the SOI structure of the present invention showing the body-contact mask opening.
- FIG. 4 is a cross-sectional view of FIG. 3 taken along the line 4 — 4 of FIG. 3 .
- FIG. 5 is an elevational view of the SOI structure of the present invention showing the nitride layer opened to the TEOS layer.
- FIG. 6 is an elevational view of the SOI structure of the present invention after opening the gate conductor to the polysilicon surface.
- FIG. 7 is an elevational view of the SOI structure of the present invention showing the formation of nitride spacers on the sidewalls of the body-contact opening.
- FIG. 8 is an elevational view of the SOI structure of the present invention after opening of the body-contact via to the semiconductor substrate.
- FIG. 9 is a top plan view of the SOI structure of the present invention showing the body contact of the present invention.
- FIG. 10 is a cross-sectional view of FIG. 9 taken along the line 10 — 10 of FIG. 9 .
- FIG. 11 is an elevational view of the SOI structure of the present invention after deposition of a low-resistance region in the body-contact opening.
- FIG. 12 is a top plan view of the SOI structure of the present invention showing a low resistance salicide over the gate conductor.
- FIG. 13 is a cross-sectional view of FIG. 12 taken along the line 13 — 13 of FIG. 12 .
- FIGS. 1-13 of the drawings in which like numerals refer to like features of the invention.
- the terms “insulating” or “insulator” means “electrically insulating” and the term “contact” mean “electrical contact.”
- the terms “on top of” or “over” are also used to denote “electrical contact.”
- the present invention creates a semiconductor device with SOI body-contacts under the gate conductor.
- the body-contacts are self aligned and borderless to adjacent source/drain diffusions, thus preventing diffusion-to-body shorts.
- the body charge must traverse along the width direction of the transistor with a relatively long path.
- the present invention partitions the gate conductor into segments and provides body-contacts under each gate conductor segment over the whole width of the device. This results in a relatively short path between adjacent MOSFET channel regions and allows accumulated charge to be removed from the body region under the gate.
- the present invention may be used selectively on semiconductor structures that are wide and require special stability considerations, such as a PASS gate transistor. While stability may be less of a concern with grounded source transistors, the present invention may also be used with grounded source transistors.
- SOI semiconductor structure 52 generally comprises a monocrystalline silicon layer 18 on top of, and in electrical contact with, a back oxide layer 20 that is on top of a thick monocrystalline silicon semiconductor substrate 22 .
- Monocrystalline silicon layer 18 may be a P-SOI layer.
- Back oxide layer 20 may be a buried oxide (“BOX”) layer and monocrystalline silicon semiconductor substrate 22 may be a P-substrate layer.
- Normal CMOS processing may be followed for forming the n and p doping in the body of the transistors, growing gate dielectric 11 , and depositing gate conductor 10 .
- Gate conductor 10 may comprise either doped polysilicon or undoped polysilicon that is later doped. Gate conductor 10 may also comprise a multi-layered structure such as polysilicon with a silicide on top. The height of gate conductor 10 may be in the range of 1000 to 2500 angstroms.
- gate conductor 10 may be patterned with a gate conductor mask to form regions that will be the gate conductors of the MOSFETS.
- a pair of source/drain extensions 14 is implanted. These implants may be N-extensions for an N-MOSFET (P-extensions for a P-MOSFET), and can be relatively lightly doped for a source/drain.
- a nitride spacer 12 is formed on either side of gate conductor 10 .
- Nitride spacer 12 is used to prevent body-contact 50 from shorting to the diffusion region.
- the width of nitride spacer 12 may be about the width of gate conductor 10 .
- the width of gate conductor 10 is preferably in the range of 0.1 to 0.25 microns, and the width of nitride spacer 12 is on the order of 0.5 to 1 times the width of gate conductor 10 .
- more heavily doped N-source and drain regions 16 are formed to create an N-MOSFET. While an NFET process is described, a similar process may be used to form a PFET.
- a first layer of tetraethoxysilane 24 (“TEOS”) is deposited over the top of nitride spacer 12 , gate conductor 10 and substrate 22 .
- TEOS layer 24 may be deposited to a thickness in the range of 1500 to 3000 angstroms.
- TEOS layer 24 may then be planarized using a process such as chemical mechanical polishing.
- a layer of silicon nitride may then be deposited over TEOS layer 24 to form nitride hard mask layer 26 .
- the thickness of nitride hard mask layer 26 may be in the range of 1000 to 2000 angstroms.
- Nitride hard mask layer 26 serves as a hardmask that resists etching for the subsequent etching of body-contact opening 30 .
- Photoresist layer 28 is deposited on top of nitride hardmask layer 26 , and a masking layer 29 is then used to form body-contact opening 30 in photoresist layer 28 over gate conductor 10 .
- Body-contact opening 30 will subsequently contain the body-contact.
- Body-contact opening 30 is preferably borderless to the edge of gate conductor 10 as shown in FIG. 3 .
- the rectangular regions in FIG. 3 show the formation of a plurality of body-contact openings 30 in photoresist layer 28 . It should be noted that while the process described herein is for the formation of a single body-contact, a typical semiconductor manufacturing process entails the formation of a plurality of body contacts on an SOI structure.
- Nitride hard mask layer 26 is then opened to TEOS layer 24 and photoresist layer 28 is removed as shown in FIG. 5 .
- a silicon oxide reactive ion etch which is selective to nitride may be performed using nitride hardmask layer 26 as a mask.
- TEOS layer 24 is opened to expose the top surface of gate conductor 10 and each nitride spacer 12 .
- gate conductor 10 may also be reactive ion etched selective to nitride and oxide, stopping at the surface of the oxide of gate dielectric 11 remaining under gate conductor 10 at the surface as shown in FIG. 6 .
- a second nitride spacer 32 is then preferably formed on the each sidewall 48 of opening 30 as shown in FIG. 7 .
- Spacer 32 preferably has a thickness in the range of 100 to 300 angstroms, and may be formed by depositing a thin layer of silicon nitride by chemical vapor deposition and doing a reactive ion etch to remove nitride from the horizontal surfaces leaving spacer 32 on each sidewall 48 .
- the purpose of second nitride spacer 32 is to space the body-contact from the edge of source and drain diffusions 14 and 16 .
- any remaining gate oxide on top of P-SOI layer 18 is removed, preferably using a short isotropic etch containing fluorine which may be a buffered HF or hydrofluoric acid vapor.
- body-contact opening 30 is extended to P-substrate 22 .
- a reactive ion silicon etch selective to nitride and oxide may be used to etch through P-SOI layer 18 .
- a reactive ion oxide etch selective to nitride may be performed to etch through BOX layer 20 to P-substrate 22 .
- Over etch control here is not critical and it is permissible to over etch slightly into P-substrate 22 .
- a p type dopant species 36 may be implanted into P-substrate 22 at the bottom of body-contact opening 30 to reduce the resistance of the body-contact.
- Implant 36 is preferably boron. It is preferable that the doping concentration of implant 36 be in the range of 10 14 to 10 16 atoms per square centimeter.
- Body-contact opening 30 is then filled with a conductive material, preferably a layer of P+ polysilicon 38 .
- the P+ polysilicon layer 38 completely fills opening 30 and extends out on top of nitride layer 26 .
- P+ polysilicon layer 38 may then go through a planarization process to remove any P+ polysilicon from the top of nitride layer 26 , leaving P+ polysilicon layer 38 flush with nitride layer 26 .
- P+ polysilicon layer 38 is then recessed to a depth so that the top of P+ polysilicon layer 38 is in contact with P-SOI layer 18 . As shown in FIG.
- the top of P+ polysilicon layer 38 is approximately 1 ⁇ 2 to 3 ⁇ 4 of the way down the thickness of P-SOI layer 18 . It is preferable that P+ polysilicon layer 38 be recessed far enough to keep P+ polysilicon layer 38 an adequate distance from diffusion region 16 and extension region 14 which might cause leakage problems, yet maintain contact with P-SOI layer 18 .
- a second insulating layer 40 preferably TEOS, is deposited over P+ polysilicon layer 38 .
- TEOS layer 40 is preferably planarized to the top of nitride layer 26 to form body-contact 50 . As shown in FIG. 9, a plurality of body-contacts 50 are distributed across the length of gate conductor 10 .
- TEOS layer 40 is recessed, selective to nitride, to below the top surface of gate conductor 10 , but shallow enough to assure that a region of TEOS remains to provide insulation to body contact 50 .
- a conductive layer 42 preferably polysilicon, is deposited over the remaining TEOS layer 40 . Polysilicon layer 42 may be doped or undoped. Polysilicon layer 42 is then polished to the top of nitride layer 26 and implanted to provide a low resistance region having a workfunction which matches the workfunction of the polysilicon of gate conductor 10 . Now, regions of polysilicon layer 42 are surrounded by nitride in the contact holes that are adjacent to the gate conductor regions.
- a reactive ion etch is preferably used to remove nitride hardmask layer 26 , a top portion of polysilicon layer 42 and a portion of nitride spacer 32 .
- the remaining surface may then be polished, typically by chemical mechanical polishing, to planarize the top of polysilicon layer 42 , TEOS layer 24 with the tops of spacers 12 and 32 . Then, as shown in FIG.
- a thin metal layer 44 such as tungsten, titanium or cobalt, may be deposited over the tops of layers 42 , 24 and spacers 12 and 32 , and reacted with polysilicon layer 42 to form a silicide layer 46 which is self-aligned (“SALICIDE”) to the exposed gate conductor 10 polysilicon and the top surface of polysilicon layer 42 .
- SALICIDE self-aligned
- the formation of silicide by the reaction of metal and silicon (polysilicon) is typically achieved at elevated temperatures in an inert ambient.
- the metal overlying the oxide areas is unreacted and may be etched off selectively to the salicide. This leaves the low-resistance salicide 46 over gate conductor 10 to provide gate continuity as shown in FIG. 12 .
- the charge associated with the SOI body travels a relatively short path. This allows excess majority carrier charge to be removed from the body region under the gate and provides for efficient body contact operation for SOI MOSFETS of any width operating at high speeds.
- the method and structure of the present invention is easily integrated into existing SOI processes requiring only one additional masking level, and does not consume additional real estate on a semiconductor substrate.
Abstract
Description
Claims (9)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/351,647 US6320225B1 (en) | 1999-07-13 | 1999-07-13 | SOI CMOS body contact through gate, self-aligned to source- drain diffusions |
TW089105948A TW512435B (en) | 1999-07-13 | 2000-03-30 | SOI CMOS body contact through gate, self-aligned to source-drain diffusions |
SG200003706A SG85712A1 (en) | 1999-07-13 | 2000-06-28 | Soi cmos body contact through gate, self-aligned to source-drain diffusions |
KR10-2000-0037777A KR100366965B1 (en) | 1999-07-13 | 2000-07-03 | Soi cmos body contact through gate, self-aligned to source-drain diffusions |
MYPI20003023A MY121158A (en) | 1999-07-13 | 2000-07-03 | Soi cmos body contact through gate, self-aligned to source-drain diffusions. |
JP2000209836A JP3468294B2 (en) | 1999-07-13 | 2000-07-11 | Method of forming silicon-on-insulator body contact and body contact structure |
CN00120329A CN1128473C (en) | 1999-07-13 | 2000-07-12 | Silicon complementary metal oxide semiconductor body contact on insulator formed by grating |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/351,647 US6320225B1 (en) | 1999-07-13 | 1999-07-13 | SOI CMOS body contact through gate, self-aligned to source- drain diffusions |
Publications (1)
Publication Number | Publication Date |
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US6320225B1 true US6320225B1 (en) | 2001-11-20 |
Family
ID=23381739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/351,647 Expired - Fee Related US6320225B1 (en) | 1999-07-13 | 1999-07-13 | SOI CMOS body contact through gate, self-aligned to source- drain diffusions |
Country Status (7)
Country | Link |
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US (1) | US6320225B1 (en) |
JP (1) | JP3468294B2 (en) |
KR (1) | KR100366965B1 (en) |
CN (1) | CN1128473C (en) |
MY (1) | MY121158A (en) |
SG (1) | SG85712A1 (en) |
TW (1) | TW512435B (en) |
Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030111693A1 (en) * | 1999-12-10 | 2003-06-19 | Sreenath Unnikrishnan | Body contact silicon-on-insulator transistor and method |
US20030203546A1 (en) * | 2002-04-29 | 2003-10-30 | Gert Burbach | SOI transistor element having an improved backside contact and method of forming the same |
US20030215988A1 (en) * | 2001-04-27 | 2003-11-20 | Zahurak John K. | Self-aligned dual-gate transistor device and method of forming self-aligned dual-gate transistor device |
US6670675B2 (en) * | 2001-08-06 | 2003-12-30 | International Business Machines Corporation | Deep trench body SOI contacts with epitaxial layer formation |
US6762477B2 (en) | 2000-03-24 | 2004-07-13 | Renesas Technology Corp. | Semiconductor device |
US20060027867A1 (en) * | 2000-12-31 | 2006-02-09 | Houston Theodore W | Sub-lithographics opening for back contact or back gate |
WO2007115002A2 (en) | 2006-04-04 | 2007-10-11 | International Business Machines Corporation | Self-aligned body contact for an semiconductor-on-insulator trench device and method of fabricating same |
US20080224229A1 (en) * | 2007-03-14 | 2008-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20100052053A1 (en) * | 2008-08-28 | 2010-03-04 | International Business Machines Corporation | Soi body contact using e-dram technology |
US20120018809A1 (en) * | 2010-06-25 | 2012-01-26 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy | Mos device for eliminating floating body effects and self-heating effects |
US8299544B2 (en) | 2011-01-04 | 2012-10-30 | International Business Machines Corporation | Field effect transistor having ohmic body contact(s), an integrated circuit structure incorporating stacked field effect transistors with such ohmic body contacts and associated methods |
US8405147B2 (en) | 2005-07-11 | 2013-03-26 | Peregrine Semiconductor Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
US8564069B1 (en) | 2012-08-21 | 2013-10-22 | International Business Machines Corporation | Field effect transistors with low body resistance and self-balanced body potential |
US8583111B2 (en) | 2001-10-10 | 2013-11-12 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
US8649754B2 (en) | 2004-06-23 | 2014-02-11 | Peregrine Semiconductor Corporation | Integrated RF front end with stacked transistor switch |
US8669804B2 (en) | 2008-02-28 | 2014-03-11 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
US8698245B2 (en) | 2010-12-14 | 2014-04-15 | International Business Machines Corporation | Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure |
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KR100629264B1 (en) | 2004-07-23 | 2006-09-29 | 삼성전자주식회사 | Semiconductor device having a body contact through gate and method of fabricating the same |
JP4989921B2 (en) * | 2006-06-05 | 2012-08-01 | ラピスセミコンダクタ株式会社 | Semiconductor device |
CN100428476C (en) * | 2006-07-10 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | CMOS part |
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Also Published As
Publication number | Publication date |
---|---|
CN1280388A (en) | 2001-01-17 |
KR100366965B1 (en) | 2003-01-09 |
KR20010015148A (en) | 2001-02-26 |
TW512435B (en) | 2002-12-01 |
JP3468294B2 (en) | 2003-11-17 |
MY121158A (en) | 2005-12-30 |
CN1128473C (en) | 2003-11-19 |
JP2001060698A (en) | 2001-03-06 |
SG85712A1 (en) | 2002-01-15 |
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