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Patente

  1. Erweiterte Patentsuche
VeröffentlichungsnummerUS6322903 B1
PublikationstypErteilung
AnmeldenummerUS 09/456,225
Veröffentlichungsdatum27. Nov. 2001
Eingetragen6. Dez. 1999
Prioritätsdatum6. Dez. 1999
GebührenstatusBezahlt
Auch veröffentlicht unterEP1247294A1, EP1247294A4, US6693361, WO2001041207A1, WO2001041207A9
Veröffentlichungsnummer09456225, 456225, US 6322903 B1, US 6322903B1, US-B1-6322903, US6322903 B1, US6322903B1
ErfinderOleg Siniaguine, Sergey Savastiouk
Ursprünglich BevollmächtigterTru-Si Technologies, Inc.
Zitat exportierenBiBTeX, EndNote, RefMan
Externe Links: USPTO, USPTO-Zuordnung, Espacenet
Package of integrated circuits and vertical integration
US 6322903 B1
Zusammenfassung
A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
Bilder(14)
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Ansprüche(29)
What is claimed is:
1. A fabrication method comprising:
forming one or more vias in a first side of a first substrate;
forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;
exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and
bonding at least one contact on the second side of the first substrate to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate, wherein the wiring substrate is a non-semiconductor substrate.
2. The method of claim 1 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the wiring substrate.
3. The method of claim 1 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.
4. A method for fabricating a vertical integrated circuit, the method comprising:
providing a vertically integrated stack of two or more structures M(1), . . . M(N), wherein each structure comprises one or more contacts directly attached to one or more contacts of another one of said structures, wherein the structure M(N) is an end structure in the stack, and the structure M(N) comprises a first side and a second side, the second side not being attached to any other one of said structures;
processing the first side of the end structure M(N) of the stack with a blanket process comprising blanket removal of material from the second side, wherein the blanket process exposes one or more first contacts protruding from the second side by at least a predetermined amount.
5. The method of claim 4 further comprising bonding each first contact to a structure M(N+1), wherein the blanket process exposes one or more features which are used as alignment marks during the bonding to the structure M(N+1).
6. The method of claim 4 wherein:
the structure M(N) comprises a wafer which comprises one or more dice;
the method comprises separating the stack into separate parts, at least one of the parts including a die from the structure M(N);
the structure M(N) has a first side attached to the structure M(N−1), and before the blanket process the structure M(N) has one or more vias made in the first side at the boundary of at least one of the dice, wherein each via is made part way through the structure M(N); and
the blanket process results in the one or more vias becoming exposed on the second side of the structure M(N).
7. A fabrication method comprising:
providing a structure S1 comprising a semiconductor substrate with circuitry adjacent to a first side of the structure;
removing material from a second side of the structure S1 to expose one or more first contact structures, wherein the material is removed at least until the one or more first contact structures protrude from the second side by at least a predetermined amount, and wherein the material removal is a blanket removal process;
depositing flowable material on the second side, wherein the flowable material is dielectric when hardened;
subjecting the flowable material to a blanket material-removal process at least until the one or more first contact structures protrude on the second side by at least a predetermined amount, so that after the removal the hardened flowable material covers the substrate on the second side.
8. The method of claim 7 wherein each first contact structure comprises:
a conductive contact; and
a dielectric covering the conductive contact on the second side; and
wherein the removal process is followed by removing the dielectric to expose the conductive contact in each first contact structure, wherein after the dielectric removal the hardened flowable material still covers the substrate on the second side.
9. A semiconductor fabrication method comprising:
making one or more vias in a first side of a first semiconductor wafer along one or more scribe lines;
bonding the first side of the first wafer to a second semiconductor wafer; and
removing material from a second side of the first wafer until the vias become through holes.
10. The method of claim 9 wherein the vias become through holes during a blanket dry etch of the first wafer.
11. The method of claim 9 wherein the one or more vias form a groove completely surrounding at least one die in the first wafer.
12. The method of claim 4 wherein each of the structures M(1), . . . M(N) comprises a semiconductor integrated circuit.
13. The method of claim 6 wherein each of the structures M(1), . . . M(N) comprises a semiconductor wafer.
14. The method of claim 12 wherein providing the stack of structures comprises manufacturing each of the structures M(1), . . . M(N) and attaching these structures together to form the stack of structures.
15. The method of claim 6 wherein separating the stack comprises dicing the stack.
16. A fabrication method comprising:
forming one or more vias in a first side of a first substrate;
forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;
exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and
bonding at least one contact on the second side of the first substrate to a printed circuit board (PCB) so that the first substrate or a portion thereof becomes directly attached to the PCB.
17. The method of claim 16 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the PCB.
18. The method of claim 16 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.
19. A fabrication method comprising:
forming one or more vias in a first side of a first substrate;
forming a conductive contact in each of the vias so that each contact is not exposed on a second side of the first substrate;
exposing each contact on the second side of the first substrate with a blanket process which includes removing material from the second side of the first substrate, wherein the blanket process causes each contact to protrude from the second side of the first substrate; and
bonding at least one contact on the second side of the first substrate to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate, wherein the wiring substrate is a semiconductor substrate without any active devices.
20. The method of claim 19 wherein the first substrate is a semiconductor wafer, the bonding is preceded by dicing the wafer into one or more dice, and the bonding results in at least one die being directly attached to the wiring substrate.
21. The method of claim 19 wherein the first substrate is a wafer, and the method further comprises, before said bonding, bonding the first side of the first substrate to a second substrate to manufacture a vertical integrated circuit.
22. A fabrication method comprising:
forming one or more first vias in a first side of a first substrate;
forming a first conductive contact in each of the first vias so that each first contact is not exposed on a second side of the first substrate;
forming one or more second vias in a first side of a second substrate;
forming a second conductive contact in each of the second vias so that each second contact is not exposed on a second side of the second substrate;
attaching the first side of the first substrate to the first side of the second substrate;
after the attaching operation, removing material from the second side of the first substrate to expose the one or more first contacts, and bonding the one or more exposed first contacts to one or more conductive contacts on a third substrate; and then
removing material from the second side of the second substrate to expose the one or more second contacts, and bonding the one or more exposed second contacts to one or more conductive contacts on a fourth substrate.
23. The method of claim 22 wherein each of the first and second substrates is a semiconductor substrate, and the method further comprises manufacturing a transistor region in at least one of the first and second substrates before the attaching operation.
24. The method of claim 22 wherein each of the first and second substrates is a semiconductor substrate, and the method further comprises manufacturing a transistor region in each of the first and second substrates before the attaching operation.
25. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in at least one of the first, second and third substrates before bonding a first contact to a contact on the third substrate.
26. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in each of the first, second and third substrates before bonding a first contact to a contact on the third substrate.
27. The method of claim 22 wherein the first, second, third and fourth substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in at least one of the first, second, third and fourth substrates before bonding of the first and second contacts.
28. The method of claim 22 wherein the first, second and third substrates are semiconductor substrates, and the method further comprises manufacturing a transistor region in each of the first, second, third and fourth substrates before bonding of the first and second contacts.
29. The method of claim 22 wherein attaching the first side of the first substrate to the first side of the second substrate comprises bonding one or more contacts on the first side of the first substrate to one or more contacts on the first side of the second substrate.
Beschreibung
BACKGROUND OF THE INVENTION

The present invention relates to semiconductor circuits, and more particularly to integrated circuit packaging and to vertical integrated circuits.

Integrated circuits are typically attached to a wiring substrate, for example, a printed circuit board (PCB), for easy connection to other circuits. Attachment can be done using flip-chip technology. According to this technology, conductive bumps are formed on the contact pads of the chip (die) incorporating the circuit. The bumps can be made by growing solder on the contact pads or by electroplating gold or some other material. Then the chip is bonded with its bumps to the wiring substrate.

Sometimes, the contacts on the wiring substrate cannot be made with the same precision as the contacts on the chip. For example, typical PCB fabrication technology is not as precise as semiconductor fabrication technology used for chip fabrication. Therefore, the chip contacts have to be made larger, and spaced farther from each other, to accommodate PCB fabrication technology.

Another reason why the chip contacts cannot be made as dense as allowed by the semiconductor fabrication technology is large tolerances required by many bumping processes.

This problem is exacerbated by the fact that the chip contacts placement is sometimes restricted by the layout of the chip circuitry. For example, many chips have their contacts restricted to the peripheral area. This makes it more difficult to accommodate larger widely spaced contacts as required by the PCB technology and bumping processes.

Therefore, sometimes a chip is bonded to a molded plastic substrate, which is bonded to the PCB. The plastic substrate can be larger than the chip, or it can have the same size. On the plastic substrate, the position of the contacts bonded to the PCB is not as limited as on the chip. For example, the contacts can be evenly distributed on the plastic substrate's surface bonded to the PCB (so-called “area matched package”).

Alternative packaging techniques are desirable.

SUMMARY

In some embodiments of the present invention, the intermediate substrate between a chip and a wiring substrate is made using techniques common in semiconductor fabrication technology. In particular, the substrate can be made from a semiconductor material (for example, silicon) or insulating polymer. The substrate has contacts both on the side connected to the chip and on the side connected to the PCB. These contacts are made using techniques similar to those used for vertical integration. See, for example, PCT publication WO 98/19337 “Integrated Circuits and Methods for Their Fabrication” (TruSi Technologies, LLC, 1998).

In some embodiments, the intermediate substrate (the “packaging” substrate) includes additional circuitry.

In some embodiments, a fabrication method comprises forming one or more vias in a first side of a first substrate. A conductive contact is formed in each of the vias so that each contact is not exposed on a second side of the first substrate. Then a blanket process exposes each contact on the second side. The blanket process includes removing material from the second side. The blanket process causes each contact to protrude from the second side. At least one contact on the second side is bonded to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate.

According to another aspect of the invention, a method for fabricating a vertical integrated circuit comprises providing a vertically integrated stack of structures M(1), . . . M(N), wherein each structure comprises one or more contacts directly attached to one or more contacts of another one of said structures. The structure M(N) is an end structure in the stack, and the structure M(N) comprises a first side not attached to any other one of said structures. The first side of the structure M(N) is processed with a blanket process comprising blanket removal of material from the first side. The blanket process exposes one or more first contacts protruding from the first side by at least a predetermined amount.

According to another aspect of the invention, a fabrication method comprises providing a structure S1 comprising a semiconductor substrate with circuitry adjacent to a first side of the structure. Material is removed from a second side of the structure S1 to expose one or more first contact structures, wherein the material is removed at least until the one or more first contact structures protrude from the second side by at least a predetermined amount, and wherein the material removal is a blanket removal process. Flowable material is deposited on the second side, wherein the flowable material is dielectric when hardened. The flowable material is subjected to a blanket material-removal process at least until the one or more first contact structures protrude on the second side by at least a predetermined amount, so that after the removal process the hardened flowable material covers the substrate on the second side.

In some embodiments, each first contact structure comprises a conductive contact and a dielectric covering the conductive contact on the second side. The removal process is followed by removing the dielectric to expose the conductive contact in each first contact structure. After the dielectric removal the hardened flowable material still covers the substrate on the second side.

According to another aspect of the invention, one or more vias are made in a first side of a first semiconductor wafer along one or more scribe lines. The first side of the first wafer is bonded to a second wafer. Material is removed from a second side of the first wafer until the vias become through holes. In some embodiments, the one or more vias form a groove completely surrounding at least one die in the first wafer.

According to another aspect of the invention, a structure comprises a first semiconductor wafer bonded to a second semiconductor wafer. The first wafer has one or more through holes on a boundary of at least one die of the first wafer.

According to another aspect of the invention, a first chip or wafer comprises a substrate made of a semiconductor or insulating material. The substrate comprises one or more through holes therein and a first contact in each of the through holes. Each contact comprises at least one conductive layer protruding from the first chip or wafer through at least one hole and also extending inside the substrate laterally away from the hole. The contacts are directly attached to a wiring substrate. The wiring substrate is a non-semiconductor substrate, or the wiring substrate is a semiconductor substrate without any active devices. The wiring substrate has one or more conductive lines for providing electrical connection to the first chip.

Some other features and advantages of the invention are described below. The invention is defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1, 2 and 3 are cross section illustrations of a packaging wafer (packaging substrate) at different stages of fabrication according to the present invention.

FIGS. 4 and 5 are cross section illustrations of a two-wafer structure at different stages of fabrication according to the present invention.

FIGS. 6 and 7 are cross section illustrations of wafers during fabrication according to the present invention,

FIGS. 8-11 are cross section illustrations of a two-wafer structure at different stages of fabrication according to the present invention.

FIG. 12 is a cross section illustration of a wafer during fabrication according to the present invention.

FIG. 13A is a plan view of a wafer according to the present invention.

FIG. 13B is a cross section illustration of the wafer of FIG. 13A.

FIGS. 14-16 are cross section illustrations of a wafer during fabrication according to the present invention.

FIG. 17 is a cross section illustration of a three-wafer structure during fabrication according to the present invention.

FIG. 18 is a cross section illustration of a vertical integrated circuit mounted on a PCB according to the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 shows a cross section of a wafer 110 at a beginning stage of fabrication. Wafer 110 will provide a first level packaging substrate for another wafer 120 (FIG. 11). The “face” side 110F of wafer 110 will be bonded to wafer 120, and the “back” side 110B to a second level wiring substrate, for example, a printed circuit board 130 (FIG. 11). In the embodiment being described, wafer 110 is made of silicon. However, other semiconductor and non-semiconductor materials can be used instead.

The beginning thickness of wafer 110 (of silicon substrate 140) is 600-750 μm, or some other value, chosen to achieve suitable mechanical strength and heat dissipation during manufacturing The final thickness will be smaller.

Back side contacts (conductive bumps) 150B on the wafer back side 110B are formed from metal 150. Before the metal is deposited vias 160 are etched in face side 110F of silicon substrate 140 at the locations at which the back side contacts will be formed. Suitable etching processes include those used to form back side contacts for vertical integration as described in PCT publication WO 98/19337 “Integrated Circuits and Methods for Their Fabrication” (TruSi Technologies, LLC, May 7, 1999) incorporated herein by reference. In one embodiment, the silicon is etched in atmospheric pressure plasma. The etcher is of type Tru-Etch 3000 (Trademark) available from Tru-Si Technologies, Inc., of Sunnyvale, Calif.

The horizontal and vertical dimensions of each via 160 are chosen based on the final thickness of wafer 110 and the dimensions of the corresponding back side contact 150B, as described below. The via sidewalls can be vertical if the etch is perfectly anisotropic, or they can be sloped, and they can be either straight or rounded. Bowl-like vias with rounded corners (see FIG. 7) can be created by an atmospheric pressure plasma etch.

A dielectric layer 170 is deposited over the wafer's face side, as described in the aforementioned publication WO 98/19337. In some embodiments, dielectric 170 is BPSG deposited by chemical vapor deposition at atmospheric pressure. Other processes (e.g., thermal oxidation of silicon or plasma enhanced chemical vapor deposition) and other insulating materials (e.g., undoped silicon dioxide, silicon nitride, or oxynitride) can also be used. See e.g., S. Wolfe et al., “Silicon Processing for the VLSI Era”, Volume 1 (1986).

Then metal 150 is deposited as described in WO 98/19337. In some embodiments, metal 150 is aluminum, gold, nickel vanadium (NiV), titanium tungsten (TiW), or some other metal suitable for bonding to a second level packaging substrate. Metal 150 can be deposited by sputtering or other known techniques. Layer 150 can be a combination of different conductive layers, including possibly non-metal layers.

Then the vias 160 are filled with filling material 180, for example, spin-on glass, a polymer, metal, or some other conductive or non-conductive material (see WO 98/19937). In one embodiment, filler 180 is polyimide. The polyimide is spun on or sprayed on the wafer to provide a planar top surface, then cured, and then etched back until metal 150 is exposed outside the vias.

The filler 180 increases the wafer mechanical strength and provides a planar top surface.

In some embodiments, filler 180 is substantially restricted to the vias. The filler does not cover the metal 150 outside the vias. In other embodiments, filler 180 is conductive, and the filler material is left outside the vias, increasing the thickness of metal 150.

Then contact bumps 210 (FIG. 2) are formed on wafer face side 110F as follows. A polymer layer 220 is deposited and patterned to provide a bump at the location of each contact 210. In some embodiments, layer 220 is polyimide deposited to a thickness of 5 to 50 μm by a spin-on or spraying technique. Other materials, both conductive and non-conductive, and other thicknesses, are used in other embodiments.

A conductive layer 230 is deposited over the face side of the wafer. In some embodiments, layer 230 is aluminum, NiV, or TiW-Cu deposited to a thickness of 1 to 25 μm by sputtering or physical vapor deposition (PVD). Other materials, thicknesses, and deposition processes can also be used, consistent with other fabrication steps. For example, some aluminum deposition processes require heating to about 300° C. to provide good adhesion of aluminum to underlying materials. Such aluminum deposition process can be used if layer 220 is polyimide or some other material capable of withstanding the 300° C. temperature.

Then layers 150 and 230 are patterned (FIG. 3) to provide interconnects between face side contacts 210 and back side contacts 150B. In some embodiments, the same mask (not shown) is used to pattern both layers. If both layers are made of the same material (e.g., aluminum), the same etch can be used for both.

A dielectric passivation layer 410 (FIG. 4) is formed on face side 110F of wafer 110. For example, spin-on-glass, polymer (e.g., polyimide), epoxy, or some other suitable low viscosity material is spun on or sprayed on the wafer so that the material is less thick over the bumps 210 than elsewhere. Then the material is dried or cured at a temperature of 120° C. to 200° C. The temperature depends on the material. After the material has been deposited, an etch-back is performed until the bumps 210 protrude from the top surface of passivation 410 by some amount suitable for bonding the wafer 110 to wafer 120 (5 to 50 μm in some embodiments). The etch can be performed in vacuum plasma or atmospheric-pressure plasma. The etch chemistry depends on the material of layer 410, as known in the art. For example, if layer 410 is polymer, then oxygen plasma is appropriate. If layer 410 is spin-on glass, fluorine containing plasma can be used.

Before the wafers 110 and 120 are aligned and bonded, circuitry (not shown) is manufactured in wafer 120, including possibly transistors or other active devices in or adjacent to the wafer's face side 120F. Contact pads 420 are made on the wafer face side 120F from a material suitable for bonding with metal 230 by whatever bonding process is used. Before or after bonding, wafer 120 can be thinned from the back side if needed.

During bonding (FIG. 5), each contact 210 is bonded to a corresponding contact pad 420 of wafer 120. The bonding can be done by a diffusion process. In this process, the wafers 110 and 120 are pressed together and heated to achieve interdiffusion of materials 230, 420. In some embodiments, layers 230, 420 are aluminum, or include aluminum as the upper (external) layer, and the diffusion bonding is achieved by pressing the two wafers together and heating the structure as described in U.S. Pat. 4,890,784 entitled “Method for Diffusion Bonding Aluminum” (1990).

Alternatively, the wafers can be bonded with conductive or anisotropic adhesive. Solder can also be used (solder bumps can be grown on contact pads 420). See U.S. Pat. No. 5,831,832 (Nov. 3, 1998, Gillette et al.), U.S. Pat. No. 5,786,271 (Jul. 28, 1998, Ohida et al.), and U.S. Pat. No. 5,918,113 (Jun. 29, 1999, Higashi et al.) describing some bonding methods and materials. Other materials and bonding methods are used in other embodiments.

For some bonding processes including diffusion bonding and bonding with conductive adhesive, contact pads 420 need not protrude from the face side 120F of wafer 120. In FIGS. 4 and 5, contacts 420 do not protrude and, on the contrary, are recessed relative to the wafer surface. Passivation 430 (for example, silicon dioxide or silicon nitride) has been deposited and patterned to expose the contacts. The thickness of passivation layer 430 is 0.5 to 2 μm in some embodiments. No bumps are formed on pads 420.

In other embodiments, contact bumps 490 (FIG. 6) similar to bumps 210 are formed on face side 120F of wafer 120 before the wafers are bonded. Bumps 490 consist of bumps 502 covered by conductor 504. Bumps 502 are made of a polymer or another suitable material deposited over the passivation layer 430 and suitably patterned in a process which can be similar to formation of bumps 220 (FIG. 2). Conductor (e.g., metal) 504 is deposited and patterned over the bumps 502 to form conductive lines connecting the bumps to respective contacts 420. The materials and deposition processes for conductor 504 can be similar to those for conductor 230 (FIG. 2). Dielectric passivation layer 506 similar to layer 410 can be formed on face side 120F of wafer 120 to protect the contact pads 420 from unintentional electrical contact Then the bumps 490 are bonded to contacts 210.

In some embodiments, bumps 490 are bonded directly to a PCB. Wafer 110 is omitted.

In FIG. 7, layer 220 on wafer 110 is omitted. Bumps 210 on wafer 110 are made of solder, nickel vanadium, gold, or some other material suitable for bonding, using known techniques (e.g., solder evaporation or electroplating).

In another variation, bumps 210 on wafer 110 are omitted. Bumps are formed on wafer 120 (e.g., by the process of FIG. 6 or using conventional solder, nickel vanadium, or gold technology), but not on wafer 110.

Wafer 120 can be made of silicon or non-silicon material, not necessarily the same material as wafer 10. However, if the same materials are used for the two wafers, their thermal expansion coefficients will advantageously be the same.

Dielectric adhesive 510 (FIG. 5) can be introduced in liquid form between the wafers and then cured to increase the mechanical strength of the structure. Suitable materials include adhesives used in vertical integration processes and as underfill materials in flip chip packaging. See the aforementioned PCT publication WO 98/19337 (TruSi Technologies) and U.S. Pat. No. 5,786,271 (Ohida et al.).

Then silicon is removed from back side 110B of wafer 110. FIG. 8 shows the resulting structure for the face side contacts embodiment of FIGS. 4 and 5. At the end of the removal process, the vias 160 are exposed (they become through holes) and the metal 150 protrudes out of the wafer back side 110B by at least a predetermined amount D1. In some embodiments, D1 is 10 μm or greater. The silicon is removed by a blanket (non-masked) process, which can be a dry etch, erg., an atmospheric pressure plasma etch of the kind described in the aforementioned publication WO 98/19337. The etch can be preceded by mechanical grinding. Other processes can also be used. Advantageously, the circuitry on the face sides 110F, 120F of the two wafers is protected by the wafers and the adhesive 510. Further, because the wafers have been bonded together, the structure is mechanically stronger, and heat dissipation is improved. Also, warpage of wafer 110 is lessened or eliminated (very thin wafers can be warped by stresses caused by the presence of metal or other materials in the wafers).

In some embodiments, the resulting thickness of wafer 110 measured from the top surface of contacts 210 (of metal 230) to the bottom surface of contacts 150B is 30-50 μm. Other thicknesses are also possible.

In FIG. 8, when the dielectric 170 becomes exposed on the back side during the etch, the dielectric is etched slower than the rest of the wafer. In some silicon embodiments, the dielectric is silicon dioxide, and the dielectric is etched 8 to 10 times slower, as described in WO 98/19337. As a result, after the etch, the dielectric protrudes down from the back side surface of silicon 140 around the contacts 150B. The protruding dielectric improves electrical insulation of silicon 140 during subsequent attachment of the wafer to wiring substrate 130 (FIG. 11).

In other embodiments, dielectric 170 is etched at the same speed as silicon 140, so no protrusions are formed.

The structure is turned upside down (FIG. 9), and a passivation layer 710 is deposited. In some embodiments, layer 710 is polyimide, glass, or some other flowable material (e.g., flowable thermosetting polymer) which can be deposited by a spin-on or spraying process and which is dielectric when cured. Low viscosity materials are particularly suitable but low viscosity is not necessary. In some embodiments, the top surface of layer 710 is substantially planar. In one embodiment, the thickness of layer 710 over the metal contacts 150B is 0.5 to 5 μm. Other thicknesses can also be used. In other embodiments, the top surface of layer 710 is not planar, and layer 710 does not necessarily cover the contacts 150B. At any rate, if layer 710 covers the contacts, the layer 710 is thinner over the contacts 150B than between the contacts.

Layer 710 is etched by a blanket etch (FIG. 10) until the contacts 150B protrude by a distance D2, which is 2 to 20 μm in some embodiments. If layer 710 is polyimide, the etch can be performed in atmospheric pressure oxygen plasma in an etcher of type Tru-Etch 3000.

In some embodiments, before layer 710 is deposited, silicon dioxide (not shown) is selectively grown on the back side 110B of silicon substrate 140, but not on metal 150B, by a plasma process described in WO 98/19337, using a Tru-Etch 3000 etcher (even though this is not an etching process). Layer 710 can be omitted.

Then the two-wafer sandwich is diced if needed, to provide separate two-die structures. (In some embodiments, the wafers are not diced.)

Then the two-wafer structure, or each two-die structure, is attached to a wiring substrate such as PCB 130 (FIG. 11). In one embodiment, contacts 150B are attached to the PCB using solder paste 910 deposited on PCB contacts 912 by a known process. Diffusion bonding, conductive or anisotropic adhesive, or other techniques, known or to be invented, can also be used. Underfill 920 is introduced between the PCB and the wafer or die sandwich to increase mechanical strength. Plastic encapsulant (not shown) is deposited over the dies or wafers using known techniques.

The final dimensions of protruding contacts 150B (FIGS. 10, 11) can be chosen to accommodate the technology used for attaching the wafer or die sandwich to the PCB. The dimensions can be controlled by controlling the size of vias 160, the back side etch parameters for the etch of wafer 110, and the thickness of layer 710 or any other insulator grown on the wafer back side In some embodiments, the bottom surface of each contact 150B is a square having a side of 20 μm or greater. Alternatively, the contacts 150B may have a rounded shape and look like a circle in the bottom view, of a radius 20 μm or greater The height of each contact, measured to the bottom surface of layer 710 (in the view of FIG. 11) is 10 to 20 μm. Other dimensions are also possible.

Contacts 150B can be evenly distributed on the back side surface 110F of wafer 110 to provide an area matched package (as shown in FIG. 13A). In some embodiments, the distance between the centers of the adjacent contacts is 75 to 1000 μm. Other distances can be used as needed to accommodate tolerances of the process of attaching the wafers to the PCB.

It is clear from the foregoing that the wafer 110 can be manufactured using processes common in semiconductor fabrication, without using uncommon processes such as electroplating or solder evaporation.

Elimination of solder bumping on wafers 110 and 120 is advantageous because solder bumping tolerances do not have to be accommodated. Contacts 210 on the wafer face side 110F can be made with smaller lateral dimensions, and can be positioned closer together to match high precision semiconductor fabrication technology that can be used to manufacture the wafer 120. Other disadvantages of solder bumping are also eliminated, such as different bumps having different heights or bumps being lost due to solder collapse.

The invention is not limited to such embodiments. Some embodiments use solder bumping.

In some embodiments, wafer 110 is made of a dielectric material, for example, a polymer. Suitable polymers include polyimide. Dielectric layers 170, 710 can be omitted.

Wafer 110 can contain multiple layers of wiring as needed to connect the contacts 210 to back side contacts 150B.

FIG. 11 illustrates certain structural features of the chip or wafer 110. The chip or wafer includes a semiconductor or insulating substrate 140. The substrate has one or more through holes in it. A contact 150B is provided in each of the holes. Each contact 150B includes at least one conductive layer 150 protruding down from the chip or wafer 110 through at least one hole. The conductive layer 150 also goes inside the substrate 140 and extends laterally away form the hole.

In FIG. 12, wafer 110 contains additional circuitry schematically represented by MOS transistor 1010 formed in silicon 140 on the wafer face side 110F. (Transistor 1010 includes source and drain regions 1010S, 1010D, and gate 1010G.) The contact fabrication steps described above in connection with FIGS. 1-4 (before the wafer 110 is bonded to wafer 120) are combined with steps forming the transistor 1010 or other circuitry as suitable for a particular fabrication process. For example, metal 150 may be deposited after formation of the gate oxide (not shown) of transistor 1010 if metal 150 is aluminum or some other low melting point metal and if the gate oxide is formed by high temperature thermal oxidation. The invention is not limited to MOS circuitry or aluminum, however.

In FIG. 12, layer 1020 represents one or more layers formed during the wafer 110 fabrication. Bumps 210 are formed above layer 1020. Metal 230 contacts metal 150 through a via 1024 in layer 1020. Alternatively, the contact can be made through intermediate layers (not shown) using multiple vias. After the bumps 210 are formed, fabrication proceeds as described above in connection with FIGS. 4-11.

In some embodiments, the circuitry in wafer 110 (or individual dies obtained from the wafer) includes ESD (electrostatic discharge) or overvoltage protection circuits, or some other circuits encountered in different types of devices. Hence, the same wafer 110 design can be combined with different kinds of wafers 120. Other examples of such circuits in wafer 110 include voltage regulators and DC converters. In one example, wafer 110 includes a voltage converter that converts a 3.3V power supply voltage available on the PCB to a 1.2V supply voltage. In another example, wafer 110 includes a converter that receives a 5V power supply voltage from the PCB and generates both 3.3V and 1.2V supply voltages for wafer 120. Voltage converters and regulators sometimes occupy large area and consume much power (generate much heat). Removing such circuits from wafer 120 to wafer or die 110 is therefore advantageous.

In some embodiments, wafer 120 is omitted. All the circuitry is in wafer 110. No contacts are formed on the face side of wafer 110. Thus, the layers 220, 230 are omitted. The wafer 110, or individual chips obtained from the wafer, are directly attached to a PCB or another wiring substrate as first level packaging. The attachment is made using back side contacts 150B.

Back side contacts 150B can be used as alignment marks when wafer 110 or the wafer sandwich 110, 120 is diced. Additional alignment marks can be created along the scribe lines as shown in FIGS. 13A and 13B. FIG. 13A shows the wafer 110 back side before dicing. In this example, the wafer includes four chips 110C. Back side contacts 150B are shown on only one of the chips for simplicity. Lines 1110 are scribe lines along which the wafer sandwich will be diced. On one or more lines 1110, vias 1120 (FIG. 13B) are etched in the face side 110F at the same time as vias 160 to form additional alignment marks. Vias 1120 can be made narrow to occupy less wafer area. In some embodiments, vias 1120 form grooves extending along entire scribe lines 1110. In other embodiments, vias 1120 do not extend all the length of the scribe lines, allowing portions of scribe lines 1110 to be used for test circuitry When metal layers 150, 230 (FIG. 2), and possibly other layers, are patterned, they can be etched off one or more vias 1120 to reduce stress on silicon substrate 140 during dicing, as shown in FIG. 13B. In any case, the stress is reduced due to the presence of an interface between the filler 180 in vias 1120 and the silicon substrate 140. Also, the filler is visible on the wafer back side, thus providing alignment marks

In some embodiments, the filler in vias 1120 is different from the filler in vias 160. The filler in vias 1120 can be soft material to reduce the stress on the silicon substrate 140 when the wafer is diced. Further, before dicing, the filler in vias 1120 can be etched away.

In some embodiments, instead of sawing the wafers, dicing is accomplished by simply breaking the wafers along the scribe lines 1110. Wafer 120 has vias (not shown) similar to vias 1120, along the scribe lines. The vias in wafer 120 are filled with soft material. Before dicing, back side 120B (FIG. 5) of wafer 120 is etched to expose the vias. This etch can be done after the wafers 110 and 120 are bonded together, so that the wafer 120 face side is protected.

In some embodiments, the wafer sandwich is sawed part of the way, and then broken.

FIGS. 14-16 show a variation of the wafer 110 back side processing. FIG. 14 shows the stage of FIG. 8, i.e., after the back side silicon etch of wafer 110. Wafer 120 is not shown for simplicity, and only one back side contact 150B is shown. In this variation, the silicon etch does not remove the insulator 170 from metal 150. Suitable silicon etches include an atmospheric pressure fluorine-containing plasma etch in a Tru-Etch 3000 etcher.

Then back side passivation layer 710 (FIG. 15) is deposited and etched as in FIGS. 9 and 10. Dielectric 170 still covers the metal 150 after the etch. In one example, passivation 710 is polyimide, and dielectric 170 is silicon dioxide. Polyimide 710 is etched by oxygen plasma in an etcher Tru-Etch 3000 or some other suitable etcher. During this etch, silicon dioxide 170 protects metal 150 from oxidation The process is particularly suitable if metal 150 is easily oxidizable (e.g., aluminum). Therefore, one does not have to use gold or other expensive metals that are not easily oxidizable.

Then the dielectric 170 is etched off the metal 150 to expose the back side contacts 150B (FIG. 16). In some embodiments, dielectric 170 is silicon dioxide, metal 150 is aluminum, and the etch is performed in a fluorine-containing plasma. Fluorine does not react with aluminum or with polyimide 710.

In FIG. 17, back side 120B of wafer 120 is bonded to a third wafer 1510 before the wafer 110 back side contacts 150B are exposed. Wafer 120 contains back side contacts 150B similar to contacts 150B in wafer 110. Wafer 120 of FIG. 17 also contains a substrate 140, an insulator 170, passivation 710, and intermediate layer or layers 1020, such as described above for wafer 110 (FIG. 12). Other structures for wafer 120 are possible, such as used in vertical integrated circuits. See, for example, the aforementioned PCT publication WO 98/19337 (TruSi Technologies).

The contacts 150B of wafer 120 are exposed after the wafers 110 and 120 have been bonded. The contacts can be exposed using the processes described above for wafer 110 (see FIGS. 8-16 and accompanying text). Wafer 120 can be bonded to wafer 1510 using the bonding processes described above for bonding the wafer 120 to wafer 110 (FIGS. 4 and 5), or other processes used in vertical integration. In FIG. 17, face side contacts 420 and passivation 430 in wafer 1510 are similar to those in wafer 120. Other embodiments use dissimilar contact structures in the two wafers.

In some embodiments, wafer 1510 also has back side contacts (not shown). After the wafers 120 and 1510 have been bonded, these contacts are exposed, and additional wafers are bonded to the back side 1510B of wafer 1510.

Then the wafer 110 back side contacts are exposed, and the wafer stack is attached to the PCB (possibly after dicing), as described above in connection with FIGS. 8-16.

An alternative fabrication sequence is as follows:

1. After wafer 120 has been manufactured but before its contacts 420 have been opened, the wafer 120 back side contacts 150B are exposed, and the wafer is bonded to face side 1510F of wafer 1510. The bonding to wafer 110 has not yet been done.

2. Possibly additional wafers are bonded to the back side 1510B of wafer 1510.

3. Passivation 430 on the face side of wafer 120 is etched to expose the wafer's contacts 420.

4. Wafer 120 is bonded to wafer 110.

5. Possibly additional wafers are bonded to the wafer stack at the end opposite to wafer 110 (i.e., the end faced by the back side 1510B).

6. Wafer 110 back side contacts 150B are exposed and attached to PCB 130.

In FIG. 18, a stack of wafers 120.1 through 120.6 is attached to first level packaging wafer 110, which is attached to PCB 130. The suffix F in numerals such as 120.2F indicates the face side of the corresponding wafer, and the suffix B indicates the back side. The face side may have active circuitry (e.g., transistors). Each of wafers 120.1 through 120.5 has back side contacts attached to another wafer.

The structure of FIG. 18 is manufactured as follows. First, the wafers 120.1 and 120.2 are bonded together, face side 120.1F to face side 120.2F, before any back side contacts on any wafers are exposed. Then one of the wafers 120.1, 120.2 has its back side contacts exposed and bonded to the face side of another wafer. For example, back side 120.1B of wafer 120.1 is bonded to face side 120.4F of wafer 120.4. Then one of the two end wafers (120.2 or 120.4) has its back side contacts exposed and bonded to the face side of another wafer, and so on, until the whole stack of wafers 120.1-120.6 and 110 has been assembled. Then the wafer 110 back side contacts are exposed, dicing is performed if needed, and the wafer stack or each chip stack is bonded to the PCB.

Encapsulant 1610 (e.g., suitable resin) is deposited to encapsulate the wafer stack or each chip stack using known techniques.

In some embodiments, the wafers 110, 120.1-120.6 of FIG. 18 have similar face side contact structures, and the wafers 110, 120.1-120.5 have similar back side contact structures, except possibly that the back side contacts in wafer 110 are larger, and are spaced farther from each other, to accommodate the PCB fabrication and mounting tolerances. In some embodiments, the size and shape of the back side contacts on wafers 120.1-120.5 are as described above for FIG. 13A (20 μm radius or 20 μm square side). The distance between the centers of the adjacent contacts is 150 μm.

The invention is not limited to the embodiments described above. In particular, the invention is not limited to any materials, fabrication steps or sequences of steps, or any particular fabrication equipment. In some embodiments, the PCB 130 is replaced with a semiconductor wafer or some other substrate, known or to be invented. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.

Patentzitate
Zitiertes PatentEingetragen Veröffentlichungsdatum Antragsteller Titel
US381012919. Okt. 19727. Mai 1974IbmMemory system restoration
US381111719. Okt. 197214. Mai 1974IbmTime ordered memory system and operation
US388188412. Okt. 19736. Mai 1975IbmMethod for the formation of corrosion resistant electronic interconnections
US399391729. Mai 197523. Nov. 1976International Business Machines CorporationParameter independent FET sense amplifier
US436810621. Juli 198111. Jan. 1983General Electric CompanyFor high-speed transfer of signals between integrated circuits
US439471218. März 198119. Juli 1983General Electric CompanyAlignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US446333624. Juni 198331. Juli 1984United Technologies CorporationUltra-thin microelectronic pressure sensors
US44675187. Febr. 198328. Aug. 1984Ibm CorporationProcess for fabrication of stacked, complementary MOS field effect transistor circuits
US46033418. Sept. 198329. Juli 1986International Business Machines CorporationStacked double dense read only memory
US461208317. Juli 198516. Sept. 1986Nec CorporationProcess of fabricating three-dimensional semiconductor device
US462817417. Sept. 19849. Dez. 1986General Electric CompanyForming electrical conductors in long microdiameter holes
US472213017. Febr. 19872. Febr. 1988Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device
US47697381. Dez. 19876. Sept. 1988Fuji Electric Co., Ltd.Electrostatic capacitive pressure sensor
US48070215. März 198721. Febr. 1989Kabushiki Kaisha ToshibaSemiconductor device having stacking structure
US484269910. Mai 198827. Juni 1989Avantek, Inc.Method of selective via-hole and heat sink plating using a metal mask
US489078428. März 19832. Jan. 1990Rockwell International CorporationUsing aluminum alloy interface
US489770817. Juli 198630. Jan. 1990Laser Dynamics, Inc.Semiconductor wafer array
US49544584. Apr. 19884. Sept. 1990Texas Instruments IncorporatedMethod of forming a three dimensional integrated circuit structure
US497863910. Jan. 198918. Dez. 1990Avantek, Inc.Exposing the plating by removing a portion of the back surface thus separating individual chips
US499658723. März 199026. Febr. 1991International Business Machines CorporationIntegrated semiconductor chip package
US506477113. Apr. 199012. Nov. 1991Grumman Aerospace CorporationSingle crystals of CDTE intermetallic, ir detectors
US50717925. Nov. 199010. Dez. 1991Harris CorporationPassivation, forming channel patterns, removal material to effect thinning
US516098715. Febr. 19913. Nov. 1992International Business Machines CorporationThree-dimensional semiconductor structures formed from planar layers
US516609726. Nov. 199024. Nov. 1992The Boeing CompanySilicon wafers containing conductive feedthroughs
US519140519. Dez. 19892. März 1993Matsushita Electric Industrial Co., Ltd.Aluminum and tungsten wires
US522577111. Okt. 19916. Juli 1993Dri Technology Corp.Making and testing an integrated circuit using high density probe points
US525833017. Febr. 19932. Nov. 1993Tessera, Inc.Semiconductor chip assemblies with fan-in leads
US527026123. Okt. 199214. Dez. 1993International Business Machines CorporationThree dimensional multichip package methods of fabrication
US530794225. Nov. 19923. Mai 1994Alcatel CitElectronic, especially telecommunication equipment rack
US530931818. Aug. 19933. Mai 1994International Business Machines CorporationThermally enhanced semiconductor chip package
US531309716. Nov. 199217. Mai 1994International Business Machines, Corp.High density memory module
US53148444. März 199224. Mai 1994Kabushiki Kaisha ToshibaForming a groove in parallel to the crystal plane by grinding-cutting, breaking along the scribe line and the groove
US532281619. Jan. 199321. Juni 1994Hughes Aircraft CompanyEtching by undercutting through dielectric, substrate layers, depositing an electrical conductive material through the opening and coupling
US532303513. Okt. 199221. Juni 1994Glenn LeedyInterconnection structure for integrated circuits and method for making same
US534077118. März 199323. Aug. 1994Lsi Logic CorporationTechniques for providing high I/O count connections to semiconductor dies
US538068121. März 199410. Jan. 1995United Microelectronics CorporationThree-dimensional multichip package and methods of fabricating
US539989812. Nov. 199221. März 1995Lsi Logic CorporationMulti-chip semiconductor arrangements using flip chip dies
US541463724. Juni 19929. Mai 1995International Business Machines CorporationIntra-module spare routing for high density electronic packages
US54265664. Jan. 199320. Juni 1995International Business Machines CorporationMultichip integrated circuit packages and systems
US545340424. März 199426. Sept. 1995Leedy; GlennMethod for making an interconnection structure for integrated circuits
US54632463. Mai 199431. Okt. 1995Sharp Kabushiki KaishaLarge scale high density semiconductor apparatus
US546663420. Dez. 199414. Nov. 1995International Business Machines CorporationElectronic modules with interconnected surface metallization layers and fabrication methods therefore
US546730512. März 199214. Nov. 1995International Business Machines CorporationThree-dimensional direct-write EEPROM arrays and fabrication methods
US546866316. März 199521. Nov. 1995International Business Machines CorporationMethod of fabricating three-dimensional direct-write EEPROM arrays
US547878127. Okt. 199426. Dez. 1995International Business Machines CorporationPolyimide-insulated cube package of stacked semiconductor device chips
US54895544. Febr. 19946. Febr. 1996Hughes Aircraft CompanyMethod of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US549483229. März 199427. Febr. 1996Siemens AktiengesellschaftMethod for manufacturing a solar cell from a substrate wafer
US550233330. März 199426. März 1996International Business Machines CorporationSemiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US550266713. Sept. 199326. März 1996International Business Machines CorporationIntegrated multichip memory module structure
US550675326. Sept. 19949. Apr. 1996International Business Machines CorporationMethod and apparatus for a stress relieved electronic module
US551705726. Mai 199514. Mai 1996International Business Machines CorporationElectronic modules with interconnected surface metallization layers
US55177542. Juni 199421. Mai 1996International Business Machines CorporationFabrication processes for monolithic electronic modules
US553251920. Jan. 19952. Juli 1996International Business Machines CorporationCube wireability enhancement with chip-to-chip alignment and thickness control
US55509423. März 199527. Aug. 1996Sheem; Sang K.Micromachined holes for optical fiber connection
US556162213. Sept. 19931. Okt. 1996International Business Machines CorporationIntegrated memory cube structure
US556308617. März 19958. Okt. 1996International Business Machines CorporationIntegrated memory cube, structure and fabrication
US556765314. Sept. 199422. Okt. 1996International Business Machines CorporationProcess for aligning etch masks on an integrated circuit surface using electromagnetic energy
US556765428. Sept. 199422. Okt. 1996International Business Machines CorporationMethod and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
US55717549. Nov. 19955. Nov. 1996International Business Machines CorporationMethod of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack
US55962266. Sept. 199421. Jan. 1997International Business Machines CorporationSemiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module
US5621106 *1. Juni 199515. Apr. 1997Toronto Research Chemicals, Inc.Reacting with dialkyltin oxide; acylation; alkylation
US56541277. Juni 19955. Aug. 1997Elm Technology CorporationMethod of making a tester surface with high density probe points
US568433030. Nov. 19954. Nov. 1997Samsung Electronics Co., Ltd.Chip-sized package having metal circuit substrate
US574210027. März 199521. Apr. 1998Motorola, Inc.Electronic component
US575987317. Okt. 19962. Juni 1998Nec CorporationMethod of manufacturing chip-size package-type semiconductor device
US57862713. Juli 199628. Juli 1998Kabushiki Kaisha ToshibaProduction of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package
US579856721. Aug. 199725. Aug. 1998Hewlett-Packard CompanyBall grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
US581754120. März 19976. Okt. 1998Raytheon CompanyMethods of fabricating an HDMI decal chip scale package
US583183211. Aug. 19973. Nov. 1998Motorola, Inc.Molded plastic ball grid array package
US583483019. Jan. 199610. Nov. 1998Lg Semicon Co., Ltd.LOC (lead on chip) package and fabricating method thereof
US584384424. Jan. 19961. Dez. 1998Matsushita Electric Industrial Co., Ltd.Probe sheet and method of manufacturing the same
US585881511. Dez. 199612. Jan. 1999Anam Semiconductor Inc.Forming light, thin, compact structure having reduced size
US586281619. Aug. 199726. Jan. 1999Lowe Technology ProductsMirror-razor combination and method
US586381219. Sept. 199626. Jan. 1999Vlsi Technology, Inc.Simplified chip size packaging
US58720512. Aug. 199516. Febr. 1999International Business Machines CorporationProcess for transferring material to semiconductor chip conductive pads using a transfer substrate
US587996426. Juni 19989. März 1999Korea Advanced Institute Of Science And TechnologySeveral wafer strips of pretested chips are bonded to a thermoplastic adhesive-coated polymer film so that the upper surface of each chip is attached to the polymer film, which acts as an insulator; reliability, simple, inexpensive
US588639826. Sept. 199723. März 1999Lsi Logic CorporationMolded laminate package with integral mold gate
US588933221. Febr. 199730. März 1999Hewlett-Packard CompanyArea matched package
US58922732. Okt. 19956. Apr. 1999Kabushiki Kaisha ToshibaSemiconductor package integral with semiconductor chip
US589229021. Okt. 19966. Apr. 1999Institute Of MicroelectronicsHighly reliable and planar ball grid array package
US591811316. Juli 199729. Juni 1999Shinko Electric Industries Co., Ltd.Process for producing a semiconductor device using anisotropic conductive adhesive
US599829212. Nov. 19977. Dez. 1999International Business Machines CorporationMethod for making three dimensional circuit integration
US6083773 *16. Sept. 19974. Juli 2000Micron Technology, Inc.Methods of forming flip chip bumps and related flip chip bump constructions
DE19707887A127. Febr. 199710. Sept. 1998Micronas Semiconductor HoldingVerfahren zum Herstellen von elektronischen Elementen
EP0698288B12. Mai 19945. Aug. 1998Siemens AktiengesellschaftProcess for producing vertically connected semiconductor components
EP0757431A215. Juli 19965. Febr. 1997International Business Machines CorporationMachine structures fabricated of multiple microstructure layers
EP0807964A111. Apr. 199519. Nov. 1997Zakrytoe Aktsionernoe Obschestvo Nauchno Proizvodstvennaya Firma "Az"Device for treating planar elements with a plasma jet
WO1992003848A228. Aug. 19915. März 1992Lsi Logic EuropStacking of integrated circuits
WO1994009513A112. Okt. 199328. Apr. 1994Glenn LeedyInterconnection structure for integrated circuits and method for making same
WO1994025981A12. Mai 199410. Nov. 1994Siemens AgProcess for producing vertically connected semiconductor components
WO1996021943A111. Apr. 199518. Juli 1996Aktsionernoe Obschestvo N ProiDevice for treating planar elements with a plasma jet
WO1997045856A128. Mai 19974. Dez. 1997Ipec Precision IncMethod for treating articles with a plasma jet
WO1997045862A121. Mai 19974. Dez. 1997Ipec Precision IncNon-contact holder for wafer-like articles
WO1998019337A127. Okt. 19977. Mai 1998Trusi Technologies LlcIntegrated circuits and methods for their fabrication
Nichtpatentzitate
Referenz
1Agrikov, U. et al "Dynamical Plasma Treatment of HIC (Hybrid Integrated Circuits) Substrates", Electronic Techniques, Ser. 10, Microelectronic Devices 5(71), 1988, pp. 30-32, Russia.
2Anthony, T., "Forming Feedthroughs in Laser-Drilled Holes in Semiconductor Wafers by Double-Sided Sputtering", IEEE Trans. On Comp., Hybrids,& Mfg. Tech, vol. CHMT-5, No. 1, Mar. 1982, pp. 171-180.
3AZ Corporation, "Plasma Jet Etching Technology and Equipment; Silicon Wafer Thinning & Isotropical Etching at Atomspheric Pressure", Semicon/Europe, Apr. 1995, Geneva, Switzerland, 4 pages.
4Christensen, C., et al. "Wafer Through-Hole Interconnections with High Vertical Wiring Densities", IEEE Trans. On Comp., Pkg.& Mfg. Tech, Part A, vol. 19, No. 4, Dec. 1996, pp. 516-521.
5G. Rinne, "Solder Bumping Methods for Flip Chip Packaging", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 241-247.
6IPEC Precision brochure for PACEJET II ((C) 1996 ), 2 pages.
7IPEC Precision brochure for PACEJET II (© 1996 ), 2 pages.
8J. Kloeser et al. "Fine Pitch Stencil Printing of Sn/Pb and Lead Free Solders for Flip Chip Technology", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 254-263.
9K. Shimokawa, et al, "Micro-ball Bump for Flip Interconnections", 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 1472-1476.
10L. Levine, "Ball Bumping and Coining Operations for Tab and Flip Chip", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 265-273.
11L. Li, et al., "Stencil Printing Process Developing for Low Cost Flip Chip Interconnect", 1998 Electronic Components and Technology Conference, 1998 IEEE, pp. 421-426.
12M. Amagai, et al., "Development of Chip Scale Packages (CSP) for Center Pad Devices", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp 343-352.
13P. Elenius, "Flex on Cap -Solder Paste Bumping", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 248-252.
14P. Elenius, "Flex on Cap —Solder Paste Bumping", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 248-252.
15R. Fillion, et al., "Chip Scale Packaging Using Chip-on-Flex Technology", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 638-641.
16Sara M. Chen, "Electroplated Hermetic Fiber", 1998 Electronic Conference, 1998 IEEE, p. 418.
17Siniaguine, Oleg, "Plasma Jet Etching at Atomspheric Pressure for Semiconductor Production", First Int'l Symposium on Plasma Process-Induced Damage, May 13-14, 1996, Santa Clara, CA, pp 151-153.
18Y. Yamaji, et al., "Development of Highly Reliable CSP", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 1022-1027.
19Y.C. Teo, "Low Cost Chip-Scale Package", 1997 Electronic Components and Technology Conference, 1997 IEEE, pp. 358-363.
Referenziert von
Zitiert von PatentEingetragen Veröffentlichungsdatum Antragsteller Titel
US6483736 *24. Aug. 200119. Nov. 2002Matrix Semiconductor, Inc.Vertically stacked field programmable nonvolatile memory and method of fabrication
US649838122. Febr. 200124. Dez. 2002Tru-Si Technologies, Inc.Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6525415 *26. Dez. 200025. Febr. 2003Fuji Xerox Co., Ltd.Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor
US6620649 *20. Sept. 200116. Sept. 2003Oki Electric Industry Co., Ltd.Method for selectively providing adhesive on a semiconductor device
US6635548 *26. Okt. 200121. Okt. 2003International Business Machines CorporationCapacitor and method for forming same
US6717254 *22. Febr. 20016. Apr. 2004Tru-Si Technologies, Inc.Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US673054018. Apr. 20024. Mai 2004Tru-Si Technologies, Inc.Clock distribution networks and conductive lines in semiconductor integrated circuits
US6753205 *27. Jan. 200322. Juni 2004Tru-Si Technologies, Inc.Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity
US6777312 *2. Nov. 200117. Aug. 2004California Institute Of TechnologyWafer-level transfer of membranes in semiconductor processing
US679427218. März 200321. Sept. 2004Ifire Technologies, Inc.Wafer thinning using magnetic mirror plasma
US680093031. Juli 20025. Okt. 2004Micron Technology, Inc.Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US681847411. Dez. 200216. Nov. 2004Hynix Semiconductor Inc.Method for manufacturing stacked chip package
US684342113. Aug. 200118. Jan. 2005Matrix Semiconductor, Inc.Molded memory module and method of making the module absent a substrate support
US6844241 *28. Aug. 200118. Jan. 2005Tru-Si Technologies, Inc.Fabrication of semiconductor structures having multiple conductive layers in an opening
US68971489. Apr. 200324. Mai 2005Tru-Si Technologies, Inc.Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US6916725 *15. Jan. 200412. Juli 2005Seiko Epson CorporationMethod for manufacturing semiconductor device, and method for manufacturing semiconductor module
US6958285 *27. März 200225. Okt. 2005Tru-Si Technologies, Inc.Methods of manufacturing devices having substrates with opening passing through the substrates and conductors in the openings
US696286710. Dez. 20038. Nov. 2005Microntechnology, Inc.Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof
US700182516. Dez. 200421. Febr. 2006Tru-Si Technologies, Inc.Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US70120173. März 200414. März 20063M Innovative Properties CompanyPartially etched dielectric film with conductive features
US70233476. Mai 20034. Apr. 2006Symbol Technologies, Inc.Method and system for forming a die frame and for transferring dies therewith
US7026223 *28. März 200211. Apr. 2006M/A-Com, IncHermetic electric component package
US7029937 *10. Nov. 200318. Apr. 2006Seiko Epson CorporationSemiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US7034401 *5. Mai 200525. Apr. 2006Tru-Si Technologies, Inc.Packaging substrates for integrated circuits and soldering methods
US704153225. Febr. 20049. Mai 2006Micron Technology, Inc.Methods for fabricating interposers including upwardly protruding dams
US704917017. Dez. 200323. Mai 2006Tru-Si Technologies, Inc.Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US706060117. Dez. 200313. Juni 2006Tru-Si Technologies, Inc.Packaging substrates for integrated circuits and soldering methods
US7064002 *21. Nov. 200220. Juni 2006Micron Technology, Inc.Method for fabricating interposers including upwardly protruding dams, semiconductor device assemblies including the interposers
US7064005 *10. Mai 200220. Juni 2006Sony CorporationSemiconductor apparatus and method of manufacturing same
US709851827. Aug. 200329. Aug. 2006National Semiconductor CorporationDie-level opto-electronic device and method of making same
US7102524 *19. Dez. 20025. Sept. 2006Symbol Technologies, Inc.Die frame apparatus and method of transferring dies therewith
US71159817. Okt. 20033. Okt. 2006Micron Technology, Inc.Semiconductor device assemblies including interposers with dams protruding therefrom
US711758119. Dez. 200210. Okt. 2006Symbol Technologies, Inc.Method for high volume assembly of radio frequency identification tags
US717332718. Mai 20056. Febr. 2007Tru-Si Technologies, Inc.Clock distribution networks and conductive lines in semiconductor integrated circuits
US718658619. Okt. 20056. März 2007Tru-Si Technologies, Inc.Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US718729317. Aug. 20056. März 2007Symbol Technologies, Inc.Singulation of radio frequency identification (RFID) tags for testing and/or programming
US719329520. Aug. 200420. März 2007Semitool, Inc.Process and apparatus for thinning a semiconductor workpiece
US7208343 *22. Dez. 200424. Apr. 2007Samsung Electronics Co., Ltd.Semiconductor chip, chip stack package and manufacturing method
US722332014. Juni 200429. Mai 2007Symbol Technologies, Inc.Method and apparatus for expanding a semiconductor wafer
US722363426. Juli 200429. Mai 2007Seiko Epson CorporationSemiconductor device, method for manufacturing the same, circuit board, and electronic apparatus
US7241641 *19. Okt. 200510. Juli 2007Tru-Si Technologies, Inc.Attachment of integrated circuit structures and other substrates to substrates with vias
US724167510. März 200410. Juli 2007Tru-Si Technologies, Inc.Attachment of integrated circuit structures and other substrates to substrates with vias
US72680812. Okt. 200311. Sept. 2007California Institute Of TechnologyWafer-level transfer of membranes with gas-phase etching and wet etching methods
US727638814. Juni 20042. Okt. 2007Symbol Technologies, Inc.Method, system, and apparatus for authenticating devices during assembly
US728848920. Aug. 200430. Okt. 2007Semitool, Inc.Process for thinning a semiconductor workpiece
US7348261 *15. Mai 200325. März 2008International Business Machines CorporationWafer scale thin film package
US735219920. Febr. 20011. Apr. 2008Sandisk CorporationMemory card with enhanced testability and methods of making and using the same
US735464920. Aug. 20048. Apr. 2008Semitool, Inc.Semiconductor workpiece
US735527320. Apr. 20058. Apr. 2008Micron Technology, Inc.Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods
US7358152 *22. Nov. 200515. Apr. 2008The United States Of America As Represented By The Secretary Of The NavyWafer bonding of thinned electronic materials and circuits to high performance substrate
US737080830. Nov. 200413. Mai 2008Symbol Technologies, Inc.Method and system for manufacturing radio frequency identification tag antennas
US740419914. Juni 200422. Juli 2008Symbol Technologies, Inc.Method, system, and apparatus for high volume assembly of compact discs and digital video discs incorporating radio frequency identification tag technology
US741985213. Mai 20052. Sept. 2008Micron Technology, Inc.Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US743562013. Juli 200714. Okt. 2008Micron Technology, Inc.Low temperature methods of forming back side redistribution layers in association with through wafer interconnects
US7465651 *30. Juni 200516. Dez. 2008Intel CorporationIntegrated circuit packages with reduced stress on die and associated methods
US74682885. Juli 200623. Dez. 2008National Semiconductor CorporationDie-level opto-electronic device and method of making same
US7473589 *13. Okt. 20066. Jan. 2009Macronix International Co., Ltd.Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US747961412. Jan. 200520. Jan. 2009Symbol TechnologiesRadio frequency identification tag inlay sortation and assembly
US75109285. Mai 200631. März 2009Tru-Si Technologies, Inc.Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US752136010. Okt. 200621. Apr. 2009Tru-Si Technologies, Inc.Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US75641182. Mai 200821. Juli 2009International Business Machines CorporationChip and wafer integration process using vertical connections
US762582126. Mai 20061. Dez. 2009Semitool, Inc.Process and apparatus for thinning a semiconductor workpiece
US770933422. Juni 20064. Mai 2010Macronix International Co., Ltd.Stacked non-volatile memory device and methods for fabricating the same
US7719079 *18. Jan. 200718. Mai 2010International Business Machines CorporationChip carrier substrate capacitor and method for fabrication thereof
US773748827. Aug. 200715. Juni 2010Macronix International Co., Ltd.Blocking dielectric engineered charge trapping memory cell with high speed erase
US779507614. Juni 200414. Sept. 2010Symbol Technologies, Inc.Method, system, and apparatus for transfer of dies using a die plate having die cavities
US781189011. Okt. 200612. Okt. 2010Macronix International Co., Ltd.Vertical channel transistor structure and manufacturing method thereof
US790745013. Okt. 200615. März 2011Macronix International Co., Ltd.Methods and apparatus for implementing bit-by-bit erase of a flash memory device
US796450821. Aug. 200821. Juni 2011Allvia, Inc.Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US79777353. März 201012. Juli 2011Macronix International Co., Ltd.Stacked non-volatile memory device and methods for fabricating the same
US799454723. Juli 20089. Aug. 2011Micron Technology, Inc.Semiconductor devices and assemblies including back side redistribution layers in association with through wafer interconnects
US799929517. Dez. 200816. Aug. 2011Macronix International Co., Ltd.Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US8017999 *5. Sept. 200713. Sept. 2011Renesas Electronics CorporationSemiconductor device
US8026592 *20. März 200927. Sept. 2011Samsung Electronics Co., Ltd.Through-silicon via structures including conductive protective layers
US81020392. Aug. 200724. Jan. 2012Sanyo Semiconductor Co., Ltd.Semiconductor device and manufacturing method thereof
US8137995 *11. Dez. 200820. März 2012Stats Chippac, Ltd.Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures
US81584565. Dez. 200817. Apr. 2012Taiwan Semiconductor Manufacturing Co., Ltd.Method of forming stacked dies
US815848931. März 201017. Apr. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Formation of TSV backside interconnects by modifying carrier wafers
US816358113. Okt. 201024. Apr. 2012Monolith IC 3DSemiconductor and optoelectronic devices
US8168470 *8. Dez. 20081. Mai 2012Stats Chippac, Ltd.Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
US816852913. Nov. 20091. Mai 2012Taiwan Semiconductor Manufacturing Company, Ltd.Forming seal ring in an integrated circuit die
US81741248. Apr. 20108. Mai 2012Taiwan Semiconductor Manufacturing Co., Ltd.Dummy pattern in wafer backside routing
US820280020. Mai 201119. Juni 2012Taiwan Semiconductor Manufacturing Company, Ltd.Method of forming through silicon via with dummy structure
US822213930. März 201017. Juli 2012Taiwan Semiconductor Manufacturing Company, Ltd.Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously
US82278993. Sept. 200924. Juli 2012Taiwan Semiconductor Manufacturing Company, Ltd.Alignment for backside illumination sensor
US822790226. Nov. 200724. Juli 2012Taiwan Semiconductor Manufacturing Company, Ltd.Structures for preventing cross-talk between through-silicon vias and integrated circuits
US823214025. März 201031. Juli 2012Taiwan Semiconductor Manufacturing Company, Ltd.Method for ultra thin wafer handling and processing
US823658411. Febr. 20117. Aug. 2012Tsmc Solid State Lighting Ltd.Method of forming a light emitting diode emitter substrate with highly reflective metal bonding
US823727216. Febr. 20107. Aug. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Conductive pillar structure for semiconductor substrate and method of manufacture
US824790628. Apr. 201021. Aug. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Supplying power to integrated circuits using a grid matrix formed of through-silicon vias
US825266529. Apr. 201028. Aug. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Protection layer for adhesive material at wafer edge
US825268212. Febr. 201028. Aug. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Method for thinning a wafer
US825881030. Sept. 20104. Sept. 2012Monolithic 3D Inc.3D semiconductor device
US8263492 *29. Apr. 200911. Sept. 2012International Business Machines CorporationThrough substrate vias
US826406613. Nov. 200911. Sept. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Liner formation in 3DIC structures
US826406716. Juli 201011. Sept. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Through silicon via (TSV) wire bond architecture
US826407729. Dez. 200811. Sept. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US827815225. Nov. 20092. Okt. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Bonding process for CMOS image sensor
US828321513. Okt. 20109. Okt. 2012Monolithic 3D Inc.Semiconductor and optoelectronic devices
US82837456. Nov. 20099. Okt. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Method of fabricating backside-illuminated image sensor
US82988756. März 201130. Okt. 2012Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US831448312. Nov. 200920. Nov. 2012Taiwan Semiconductor Manufacturing Company, Ltd.On-chip heat spreader
US83193368. Juli 201027. Nov. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of etch microloading for through silicon vias
US832468116. Juni 20114. Dez. 2012Macronix International Co., Ltd.Stacked non-volatile memory device and methods for fabricating the same
US832473825. Mai 20104. Dez. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Self-aligned protection layer for copper post structure
US832957812. März 201011. Dez. 2012Taiwan Semiconductor Manufacturing Company, Ltd.Via structure and via etching process of forming the same
US833893912. Juli 201025. Dez. 2012Taiwan Semiconductor Manufacturing Company, Ltd.TSV formation processes using TSV-last approach
US834384019. Apr. 20101. Jan. 2013Macronix International Co., Ltd.Blocking dielectric engineered charge trapping memory cell with high speed erase
US83445134. Dez. 20091. Jan. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Barrier for through-silicon via
US83625918. Juni 201029. Jan. 2013Taiwan Semiconductor Manufacturing Co., Ltd.Integrated circuits and methods of forming the same
US837781627. Apr. 201019. Febr. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Method of forming electrical connections
US839000916. Febr. 20105. März 2013Taiwan Semiconductor Manufacturing Company, Ltd.Light-emitting diode (LED) package systems
US839012521. März 20115. März 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon via formed with a post passivation interconnect structure
US839927312. Aug. 200919. März 2013Tsmc Solid State Lighting Ltd.Light-emitting diode with current-spreading region
US839935412. Nov. 200919. März 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon via with low-K dielectric liner
US840520115. Juli 201026. März 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon via structure
US841145913. Juli 20102. Apr. 2013Taiwan Semiconductor Manufacturing Company, LtdInterposer-on-glass package structures
US843142130. März 200930. Apr. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Test patterns for detecting misalignment of through-wafer vias
US843203820. Mai 201030. Apr. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon via structure and a process for forming the same
US843644816. Febr. 20117. Mai 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon via with air gap
US844112429. Apr. 201014. Mai 2013Taiwan Semiconductor Manufacturing Company, Ltd.Cu pillar bump with non-metal sidewall protection structure
US844113627. Juli 201214. Mai 2013Taiwan Semiconductor Manufacturing Company, Ltd.Protection layer for adhesive material at wafer edge
US844529622. Juli 201121. Mai 2013Taiwan Semiconductor Manufacturing Company, Ltd.Apparatus and methods for end point determination in reactive ion etching
US845599516. Apr. 20104. Juni 2013Taiwan Semiconductor Manufacturing Company, Ltd.TSVs with different sizes in interposers for bonding dies
US845600815. Sept. 20114. Juni 2013Taiwan Semiconductor Manufacturing Company, Ltd.Structure and process for the formation of TSVs
US846104517. März 201111. Juni 2013Taiwan Semiconductor Manufacturing Company, Ltd.Bond pad connection to redistribution lines having tapered profiles
US846605930. März 201018. Juni 2013Taiwan Semiconductor Manufacturing Company, Ltd.Multi-layer interconnect structure for stacked dies
US84713581. Juni 201025. Juni 2013Taiwan Semiconductor Manufacturing Company, Ltd.3D inductor and transformer
US847611631. Okt. 20122. Juli 2013Taiwan Semiconductor Manufacturing Company, Ltd.Reduction of etch microloading for through silicon vias
US847673529. Mai 20072. Juli 2013Taiwan Semiconductor Manufacturing Company, Ltd.Programmable semiconductor interposer for electronic package and method of forming
US847676917. Okt. 20072. Juli 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon vias and methods for forming the same
US848741013. Apr. 201116. Juli 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon vias for semicondcutor substrate and method of manufacture
US84874444. Dez. 200916. Juli 2013Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional system-in-package architecture
US850018217. Juni 20106. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Vacuum wafer carriers for strengthening thin wafers
US85015875. Nov. 20096. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Stacked integrated chips and methods of fabrication thereof
US850161625. Okt. 20126. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Self-aligned protection layer for copper post structure
US85023389. Sept. 20106. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-substrate via waveguides
US850735827. Aug. 201013. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Composite wafer semiconductor
US850794010. Sept. 201013. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Heat dissipation by through silicon plugs
US851311910. Dez. 200820. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Method of forming bump structure having tapered sidewalls for stacked dies
US851940915. Nov. 201027. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Light emitting diode components integrated with thermoelectric devices
US851953828. Apr. 201027. Aug. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Laser etch via formation
US852527819. Aug. 20113. Sept. 2013Taiwan Semiconductor Manufacturing Company, Ltd.MEMS device having chip scale packaging
US852534328. Sept. 20103. Sept. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Device with through-silicon via (TSV) and method of forming the same
US853103531. Aug. 201110. Sept. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Interconnect barrier structure and method
US853156523. Febr. 201010. Sept. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Front side implanted guard ring structure for backside illuminated image sensor
US85462355. Mai 20111. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuits including metal-insulator-metal capacitors and methods of forming the same
US854625419. Aug. 20101. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming copper pillar bumps using patterned anodes
US854688624. Aug. 20111. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Controlling the device performance by forming a stressed backside dielectric layer
US854695313. Dez. 20111. Okt. 2013Taiwan Semiconductor Manufacturing Co., Ltd.Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
US855248515. Juni 20118. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor structure having metal-insulator-metal capacitor structure
US85525636. Jan. 20108. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional semiconductor architecture
US855835116. Juli 201215. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Alignment for backside illumination sensor
US856783724. Nov. 201029. Okt. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Reconfigurable guide pin design for centering wafers having different sizes
US857572513. März 20135. Nov. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through-silicon vias for semicondcutor substrate and method of manufacture
US858064719. Dez. 201112. Nov. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Inductors with through VIAS
US858068230. Sept. 201012. Nov. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Cost-effective TSV formation
US85814016. Juli 201212. Nov. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming copper pillar bumps using patterned anodes
US858712715. Juni 201119. Nov. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor structures and methods of forming the same
US859869523. Juli 20103. Dez. 2013Tessera, Inc.Active chip on carrier or laminated chip having microelectronic element embedded therein
US860449121. Juli 201110. Dez. 2013Tsmc Solid State Lighting Ltd.Wafer level photonic device die structure and method of making the same
US860459410. Jan. 201210. Dez. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Structures for preventing cross-talk between through-silicon vias and integrated circuits
US860461922. Nov. 201110. Dez. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Through silicon via keep out zone formation along different crystal orientations
US860950619. Nov. 201217. Dez. 2013Taiwan Semiconductor Manufacturing Company, Ltd.On-chip heat spreader
US861024730. Dez. 201117. Dez. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Structure and method for a transformer with magnetic features
US86102709. Febr. 201017. Dez. 2013Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor device and semiconductor assembly with lead-free solder
US861863114. Febr. 201231. Dez. 2013Taiwan Semiconductor Manufacturing Co., Ltd.On-chip ferrite bead inductor
US862375515. Juli 20137. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Self-aligned protection layer for copper post structure
US862436011. Nov. 20097. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Cooling channels in 3DIC stacks
US862898415. Febr. 201314. Jan. 2014Tsmc Solid State Lighting Ltd.Light-emitting diode (LED) package systems
US862904223. Jan. 201314. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method for stacking semiconductor dies
US862906630. Juli 201214. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Liner formation in 3DIC structures
US86295638. Febr. 201214. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method for packaging semiconductor dies having through-silicon vias
US862956513. März 201214. Jan. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Thin wafer protection device
US86335892. Okt. 200721. Jan. 2014Invensas CorporationDielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US86431497. Jan. 20104. Febr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Stress barrier structures for semiconductor chips
US86479253. Juni 201011. Febr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Surface modification for handling wafer thinning process
US86536483. Okt. 200818. Febr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Zigzag pattern for TSV copper adhesion
US86591267. Dez. 201125. Febr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Integrated circuit ground shielding structure
US865915529. Juli 201025. Febr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Mechanisms for forming copper pillar bumps
US867377530. Mai 201318. März 2014Taiwan Semiconductor Manufacturing Company, Ltd.Methods of forming semiconductor structures
US867451029. Juli 201018. März 2014Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional integrated circuit structure having improved power and thermal management
US867488324. Mai 201118. März 2014Taiwan Semiconductor Manufacturing Company, Ltd.Antenna using through-silicon via
US868068228. Dez. 201225. März 2014Taiwan Semiconductor Manufacturing Company, Ltd.Barrier for through-silicon via
US868652619. Nov. 20071. Apr. 2014Semiconductor Components Industries, LlcSemiconductor device and method of manufacturing the same
US869166411. Jan. 20108. Apr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Backside process for a substrate
US86931631. Sept. 20108. Apr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Cylindrical embedded capacitors
US87036091. Juli 201122. Apr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Through-substrate via for semiconductor device
US87043755. Nov. 200922. Apr. 2014Taiwan Semiconductor Manufacturing Company, Ltd.Barrier structures and methods for through substrate vias
US871612814. Apr. 20116. Mai 2014Tsmc Solid State Lighting Ltd.Methods of forming through silicon via openings
US871613116. Okt. 20126. Mai 2014Taiwan Semiconductor Manufacturing Company, Ltd.Through silicon via layout
US872254022. Juli 201013. Mai 2014Taiwan Semiconductor Manufacturing Company, Ltd.Controlling defects in thin wafer handling
US87360507. Juli 201027. Mai 2014Taiwan Semiconductor Manufacturing Company, Ltd.Front side copper post joint structure for temporary bond in TSV application
US874258316. Jan. 20123. Juni 2014Taiwan Semiconductor Manufacturing Company, Ltd.Seal ring in an integrated circuit die
US874828412. Aug. 201110. Juni 2014Taiwan Semiconductor Manufacturing Company, Ltd.Method of manufacturing decoupling MIM capacitor designs for interposers
US87490277. Jan. 200910. Juni 2014Taiwan Semiconductor Manufacturing Company, Ltd.Robust TSV structure
US87539392. Aug. 201317. Juni 2014Taiwan Semiconductor Manufacturing Company, Ltd.Three-dimensional semiconductor architecture
US875994918. Febr. 201024. Juni 2014Taiwan Semiconductor Manufacturing Company, Ltd.Wafer backside structures having copper pillars
US8766408 *7. März 20071. Juli 2014Semiconductor Components Industries, LlcSemiconductor device and manufacturing method thereof
US876640924. Juni 20111. Juli 2014Taiwan Semiconductor Manufacturing Co., Ltd.Method and structure for through-silicon via (TSV) with diffused isolation well
US20100291735 *27. Juli 201018. Nov. 2010Volkan OzguzStackable semiconductor chip layer comprising prefabricated trench interconnect vias
US20110217812 *17. Mai 20118. Sept. 2011Harry HedlerIntegrated circuit device and method for fabricating same with an interposer substrate
US20120074585 *15. Juli 201129. März 2012Stats Chippac, Ltd.Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer
CN100438022C30. Juli 200426. Nov. 2008精工爱普生株式会社Semiconductor device and its making method, circuit substrate and electronic machine
DE10346581B4 *7. Okt. 200327. Dez. 2007Renesas Technology Corp.Verfahren zum Herstellen einer Halbleitervorrichtung
EP1391923A1 *19. März 200325. Febr. 2004Seiko Epson CorporationSemiconductor device and its manufacturing method, circuit board and electronic apparatus
EP1391924A1 *19. März 200325. Febr. 2004Seiko Epson CorporationSemiconductor device and its manufacturing method, circuit board, and electric apparatus
EP1470583A1 *26. Nov. 200227. Okt. 2004International Business Machines CorporationChip and wafer integration process using vertical connections
EP1763079A1 *7. Sept. 200514. März 2007Irvine Sensors CorporationStackable semiconductor chip layer comprising prefabricated trench interconnect vias
WO2003065450A2 *18. Dez. 20027. Aug. 2003Tru Si Technologies IncIntegrated circuits with backside contacts and methods for their fabrication
WO2003079430A119. März 200325. Sept. 2003Seiko Epson CorpSemiconductor device and its manufacturing method, circuit board and electronic apparatus
WO2005059993A2 *15. Dez. 200430. Juni 2005Tru Si Technologies IncPackaging substrates for integrated circuits and soldering methods
WO2005059998A1 *16. Dez. 200430. Juni 2005Tru Si Technologies IncIntegrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
WO2005074339A1 *13. Jan. 200511. Aug. 20053M Innovative Properties CoPartially etched dielectric film with conductive features
WO2012015550A228. Juni 20112. Febr. 2012Monolithic 3D, Inc.Semiconductor device and structure
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