US6552423B2 - Higher-density memory card - Google Patents

Higher-density memory card Download PDF

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Publication number
US6552423B2
US6552423B2 US09/785,810 US78581001A US6552423B2 US 6552423 B2 US6552423 B2 US 6552423B2 US 78581001 A US78581001 A US 78581001A US 6552423 B2 US6552423 B2 US 6552423B2
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United States
Prior art keywords
memory
card
memory card
chip
package
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Expired - Fee Related, expires
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US09/785,810
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US20010015485A1 (en
Inventor
Young-Jae Song
Young-Shin Kwon
Kun-Dae Youm
Young-soo Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YOUNG-SOO, YUN, YOUNG-JAE, KWON, YOUNG-SHIN, YOUM, KUN-DAE
Publication of US20010015485A1 publication Critical patent/US20010015485A1/en
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
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Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor memory card.
  • a very small and light memory card used for storing and retrieving data for digital products such as a MP3 player or a digital camera is called “smart media card”.
  • the memory card contains non-volatile memory chips such as NAND-type or NOR-type flash memory chips and, if necessary, a controller chip.
  • Memory density, i.e., memory storage capacity, of the current memory card is several tens or hundreds of mega-bits.
  • an increase of the memory density has been constantly required to keep up with rapid developments in modem digital technology.
  • the rate of the increase of the memory density has not been sufficient.
  • new and useful approaches to increase the memory density of the memory card are also required in addition to relying on the increase of the memory density of the memory chips.
  • One such approach to increasing the memory density of the memory card is to use a plurality of identical memory chips. For example, as shown in FIG. 1, two memory chips 13 are stacked, or as shown in FIG. 2, two memory chips 23 are mounted side by side.
  • conventional memory card 10 or 20 has a structure where memory chips 13 or 23 are mounted within a package 11 or 21 , and the packages 11 or 21 are positioned on a card body 12 or 22 , i.e., “a base card.”
  • a printed circuit board 14 or 24 is used in the package 11 or 21 , and the memory chips 13 or 23 are mounted on one of the surfaces of the printed circuit board 14 or 24 and a plurality of contact pads 15 or 25 are formed on the other surface of the printed circuit board 14 or 24 .
  • the memory chips 13 or 23 are electrically interconnected to the printed circuit board 14 or 24 by wire bonding or flip chip bonding and to the contact pads 15 or 25 through the wiring patterns and the via holes (not shown) of the printed circuit boards 14 or 24 .
  • the memory chips 13 or 23 are encapsulated with a molding resin 16 , 26 .
  • a controller chip 17 may be additionally used.
  • the upper chip 13 a should be off-set from an edge of the underlying lower chip 13 b so as to expose the chip pads 18 b of the lower chip 13 b for electrical interconnection.
  • the chip pads 18 a or 18 b should be formed on the upper surface of each chip 13 a or 13 b along only one of the edges.
  • the chip pads 18 a , 18 b of the upper and the lower chips 13 a , 13 b respectively, perform the same function and are connected to pads 14 a formed on the substrate via wire bonding. Therefore, the size of the pads 14 a should be sufficiently large so that both the upper and lower bonding wires 19 can be electrically connected in common thereto.
  • longer bonding wires should be used.
  • the longer bonding wires may result in undesirable electrical shorts between adjacent wires by, for example, wire sweeping, a problem that is well known in the art.
  • the warpage of the printed circuit board becomes serious due to the difference in the coefficient of thermal expansion between the chips and the board.
  • Several problems such as delamination on interface, poor adhesion, difficulty in stacking of chips, are caused by the warpage.
  • a package containing multiple chips may sometimes fail electrical or burn-in test steps due to one defective chip therein although the other chips are good. This causes great losses in yield, and therefore a so-called known good die (KGD) which is an unpackaged die that has been tested to a quality and reliability level equal to the packaged product before packaging are required for the multi-chip package.
  • KGD known good die
  • FIG. 2 Another conventional memory card as shown in FIG. 2 has been proposed to provide a solution to some of the problems described above, since chips are mounted side-by-side on the board without stacking.
  • this memory card structure still has the above-mentioned problems, e.g., poor yield, because a single package includes multiple chips.
  • the size of the memory chip 23 is reduced, there still remains a drawback in that that the number of the memory chips mounted side-by-side within the package 21 that can be loaded is limited.
  • the present invention increases memory density of a memory card by improving the structure of the memory card. Particularly, the number of the memory chips within the memory card can be increased even without reducing the size of the memory chip or increasing the density of the memory chip.
  • the present invention further prevents several problems in the manufacturing process or the test process caused by using a plurality of the memory chips.
  • a memory card comprises a base card and two packages connected to the base card.
  • the two packages are attached to the base card and face each other.
  • a first package comprises a first substrate and at least one memory chip
  • a second package comprises a second substrate and at least one memory chip.
  • a first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card.
  • a second surface of the first substrate has first connection pads formed thereon and connected to the base card.
  • the memory chips are mounted on the second surface and electrically connected to each other.
  • a third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon and connected to the base card.
  • the memory chips are mounted on the fourth surface and electrically connected to each other.
  • the base card includes internal connection means, and the first and the second connection pads are electrically connected to the internal connection means.
  • the external connection pads provide electrical connection between said internal connection means to an external system.
  • the memory card of the present invention can increase the memory density of the smart cart four times or more. Also, the problems encountered in the conventional smart card manufacturing process or the test process can be prevented.
  • FIG. 1 is a cross-sectional view of a conventional memory card
  • FIG. 2 is a cross-sectional view of another conventional memory card
  • FIG. 3 is a cross-sectional view of a memory card in accordance with an embodiment of the present invention.
  • FIG. 4 is an exploded isometric view of the memory card of FIG. 3;
  • FIG. 5 is an isometric view showing a connection method between the chip pads of the upper and the lower packages of the memory card in the present invention
  • FIG. 6 is an isometric view showing another connection method between the chip pads of the upper and the lower packages of the memory in the present invention.
  • FIG. 7 is a cross-sectional view of a memory card in accordance with another embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a memory card in accordance with still another embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a memory card 100 in accordance with an embodiment of the present invention.
  • the memory card 100 includes two packages 110 , 140 .
  • Each package preferably includes two memory chips 130 a , 130 b or 160 a , 160 b .
  • the memory card 100 has four-fold density. (Thus, the density of the memory card 100 is increased at least two times more than the density of a conventional memory card.)
  • each package 110 or 140 contains only two memory chips 130 a , 130 b or 160 a , 160 b therein, the problems shown in conventional memory card structure can be avoided.
  • FIG. 4 is an exploded isometric view of the memory card 100 of FIG. 3 .
  • the base card 170 has an opening in the center portion thereof.
  • upper and lower packages 110 , 140 are inserted into the opening of the base card 170 from the top and the bottom thereof, respectively.
  • two packages 110 , 140 are face each other.
  • the packages 110 , 140 are physically attached to the base card 170 by an adhesion sheet 172 .
  • a liquid adhesive may be used, as shown in FIG. 7 .
  • Each package 110 or 140 comprises a corresponding substrate 120 or 150 .
  • the memory chips 130 a , 130 b or 160 a , 160 b are mounted on inner surface 121 b or 151 b of the substrate 120 or 150 .
  • the substrate 120 or 150 is placed on the base card 170 , and an encapsulant 133 , 163 is used to protect the mounted chips.
  • Printed circuit boards or wiring films are used as the substrates 120 , 150 .
  • a polymer material such as an epoxy-molding compound is used as the encapsulant 133 , 163 .
  • the printed circuit board is made by forming copper wirings on an insulating plate such as BT resin (Bismaleimide Triazine Resin), FR-4, or FR-5, and the wiring film is made by forming copper wirings on the polyimide film.
  • BT resin Bismaleimide Triazine Resin
  • FR-4 Bismaleimide Triazine Resin
  • FR-5 Bismaleimide Triazine Resin
  • the wiring film is made by forming copper wirings on the polyimide film.
  • other conventional methods or material to form the printed circuit board or the wiring film can be utilized for the purpose of the present invention.
  • the copper wirings form substrate pads 123 , 153 , wiring patterns 124 , 154 , and connection pads 125 , 155 on the inner surface 121 b , 151 b of the upper and the lower packages 110 , 140 , and external connection pads 122 on an outer surface 121 a near an edge of the upper package 110 .
  • the connection pads 125 of the upper package 110 are electrically connected to the external connection pads 122 through via holes 126 formed through the substrate 120 .
  • the substrate pads 123 , 153 , the connection pads 125 , 155 , and the external connection pads 122 preferably are plated with nickel or gold. Further, the inner walls of the via holes 126 preferably are plated with copper.
  • the external connection pads 122 provide electrical connection to an external system (not shown), when the memory card is inserted to the external system such as the MP3 player or the digital camera.
  • the external connection pads 122 are formed on only one surface of the memory card 100 , that is, the upper package 110 .
  • FIG. 4 describes nine (9) external connection pads 122 aligned in a row.
  • the present invention allows many variations and modifications in the number and the arrangement shape of the external connection pads.
  • FIG. 5 shows three (3) connection pads 125 , 155 , three (3) substrate pads 123 , 153 and three (3) chip pads 131 , 161 .
  • actual number of each group of pads is the same as the number of the external connection pads 122 , e.g., nine (9) and is reduced in the drawings for simplicity.
  • Two identical memory chips 130 a , 130 b , or 160 a , 160 b are mounted on the corresponding substrate 120 , or 150 .
  • the lower chips 130 a , 160 a are attached to the inner surfaces 121 b , 151 b by an adhesive (not shown), and the upper chips 130 b , 160 b are stacked on the lower chips 130 a , 160 a .
  • the chip pads 131 , 161 of the memory chips 130 a , 130 b , and 160 a , 160 b are formed on one edge of the upper surface of each chip.
  • the upper chips 130 b , 160 b are stacked on the lower chips 130 a , 160 a , and are off-set from an edge of the lower chips to expose the chip pads 131 , 161 of the lower chips 130 a , 160 a .
  • memory chips 130 a , 130 b and 160 a , 160 b non-volatile memory chips such as NAND-type or NOR-type flash memory chips are preferably used.
  • a controller chip 132 (not shown in FIG. 5) can be additionally used. If the controller chip is installed on the external system (not shown), the controller chip needs not be mounted on the memory card 100 .
  • the chip pads 131 , 161 are electrically connected to the corresponding substrate pads 123 , 153 with bonding wires 134 , 164 .
  • Two bonding wires 134 or 164 which interconnect the upper chip 130 b or 160 b to the lower chip 130 a or 160 a , are connected in common to a single substrate pad 123 or 153 .
  • the substrate pads 123 or 153 are connected to the connection pads 125 or 155 through the wiring patterns 124 or 154 . Accordingly, each of the connection pads 125 , 155 is electrically connected to two chip pads 131 , 161 .
  • connection pads 125 , 155 of each package 110 , 140 are connected to internal connection means 171 on the base card 170 . Therefore, the connection pads 125 , 155 are connected to each other through the internal connection means 171 , and thereby electrically connected to the external connection pads 122 . Since one external connection pad 122 is electrically connected to four (4) chip pads 131 , 161 through two (2) connection pads 125 , 155 , the memory card 100 has a fourfold (extended) density, compared to the density of any one memory chip 130 a , 130 b , 160 a , or 160 b.
  • the internal connection means 171 formed on the base card 170 are metal patterns, preferably made of copper.
  • the metal patterns 171 can be formed with the similar method of forming the copper wirings on the substrates 120 , 150 .
  • portions of the metal patterns 171 i.e., the portions contacting the connection pads 125 , 155 of the substrate 120 , 150 , are plated with solder.
  • the packages 110 , 140 are mechanically connected to the base card 170 through the adhesion sheet 172 , and this process is carried out at 200° C. temperature.
  • connection pads 125 , 155 can be connected to the metal patterns 171 without any additional process steps.
  • the chip pads 131 , 161 having the same function are connected in common to the same substrate pad 123 , 153 , respectively, and eventually to the same external connection pad 122 . Because the upper and the lower packages 110 , 140 are connected to the base card 170 , the upper and the lower packages 110 , 140 being positioned opposite to each other, the chip pads 131 of the upper package 110 and the chip pads 161 of the lower package 140 face each other. Therefore, in order to connect the chip pads 131 to the corresponding chip pads 161 having the same function as the chip pads 131 , the present invention preferably employs two methods described in detail below.
  • one method is to use the substrates 120 , 160 , each having the connection pads 125 or 155 , which face each other.
  • the four memory chips 130 a , 130 b and 160 a , 160 b mounted on the upper and the lower packages 110 and 140 , respectively, are all the same devices.
  • the chip pad 131 (A1) of the upper package 110 corresponds with the chip pad 161 (A1) of the lower package 140 .
  • the connection pads 125 , 155 would not correspond with each other. Instead the substrates must be mirror images of one another. Therefore, the wiring patterns 124 on one of the substrates (the substrate 120 of the upper package 120 in FIG.
  • connection pads 125 , 155 of the substrates 120 , 150 face each other. Further, the connection pads 125 , 155 , respectively connected to two corresponding chip pads 131 , 161 , can be connected to the same external connection pads 122 shown in FIG. 4 .
  • memory chips 130 ′, 160 ′ having dummy pads 135 , 165 formed thereon can be used to implement the present invention.
  • the dummy pads 135 , 165 correspond with the chip pads 131 , 161 .
  • the dummy pads 135 , 165 are formed on the other edge being opposite to the edge provided with the chip pads 131 , 161 , respectively.
  • the dummy pads 135 (C1), 165 (C1) correspond with chip pads 131 (A1), 161 (A1), respectively.
  • two packages 110 , 160 can employ the same substrates 120 , 150 , i.e., substrates having identical wiring or printed circuit patterns.
  • the chips 130 ′ or 160 ′ of either package are stacked turned around 180° degrees. That is, the chip pads 161 (A1) of the lower package 140 ′ and the dummy pads 135 (C1) of the upper package 110 ′ are respectively connected to the corresponding connection pads 125 (B1), 155 (B1) to be connected to the same external connection pads 122 shown in FIG. 4 .
  • FIG. 7 Another embodiment of the present invention uses via holes as the internal connection means between the base card and the packages and is described with reference to FIG. 7 .
  • Two packages 210 , 240 are fixedly mounted within the base card 270 .
  • the space between two packages 210 , 240 and the base card 270 is filled with the liquid adhesive 272 .
  • via holes 271 formed through the base card 270 are used as the electrical internal connection means.
  • An epoxy-resin compound with a predetermined viscosity can be used as the liquid adhesive 272 .
  • the via holes 271 of the base card 270 are plated or filled with a conductive material such as copper or solder.
  • two memory chips 230 , 260 are mounted side-by-side on each substrate 220 or 250 within the memory card 200 .
  • the chip pads need not be formed on only one edge of the chips, and the two same functional chip pads need not wire-bonded in common to one substrate pad.
  • the same functional chip pads are connected to different substrate pads, eventually the chip pads can be connected to the same connection pad through the wiring patterns.
  • other conventional techniques such as flip chip bonding using the metal bumps 234 , 264 can used rather than wire bonding.
  • FIG. 8 This embodiment uses an anisotropic conductive film (ACF) to electrically interconnect the base card and the packages.
  • ACF anisotropic conductive film
  • the anisotropic conductive film 380 is interposed between the internal connection means 371 of the base card 370 and the substrate 320 of the package 310 .
  • the connection pads 325 of the substrate 320 are electrically connected to the internal connection means 371 of the base card 370 through conductive particles 382 within the anisotropic conductive film 380 .
  • the anisotropic conductive film 380 comprises the conductive particles 382 within a resin 384 .
  • the conductive particles 382 are fixed between the connection pads 325 and the internal connection means 371 , thereby providing an electrical path. Therefore, the anisotropic conductive film 380 physically connects the substrate 320 to the base card 370 .
  • two memory chips are mounted on each package. If the memory chip is miniaturized and more than two memory chips are mounted on each package, this will still fall within the spirit and scope of the present invention.
  • a plurality of chips or a plurality of two-chip stacks may be mounted side by side. Therefore, it is possible to increase the density of the memory card four times or more.
  • a trade-off between the memory density extension and loss caused by the test failure, and the increase of the production cost due to the use of the KGD should be considered.
  • the present invention has advantages in that the density of the memory card can be increased without increasing the number of the memory chip mounted in a package by connecting two substrates in one memory card. That is, the present invention prevents the problems encountered in the conventional smart card manufacturing process or the test process due to use of plural memory chips, and increase the density of the memory card.

Abstract

A high-density memory card comprises a base card and two packages fixedly mounted within the base card. The two packages are attached to the base card and face each other. In one embodiment, a first package comprises a first substrate and at least one memory chip, and a second package comprises a second substrate and at least one memory chip. A first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card. A second surface of the first substrate has first connection pads formed thereon. The memory chips are mounted on the second surface and electrically connected to each other. A third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon. The memory chips are mounted on the fourth surface and electrically connected to each other. The base card further includes internal connection means, and the first and the second connection pads are electrically connected to the internal connection means. The external connection pads provide electrical connection between said internal connection means to an external system. By connecting two packages to the base card, the memory card of the present invention can increase the memory density of the smart cart four times or more. Also, the problems encountered in the conventional smart card manufacturing process or the test process due to the use of plural memory chips can be prevented.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor memory card.
2. Description of the Related Arts
A very small and light memory card used for storing and retrieving data for digital products such as a MP3 player or a digital camera is called “smart media card”. Generally, the memory card contains non-volatile memory chips such as NAND-type or NOR-type flash memory chips and, if necessary, a controller chip.
Memory density, i.e., memory storage capacity, of the current memory card is several tens or hundreds of mega-bits. However, an increase of the memory density has been constantly required to keep up with rapid developments in modem digital technology. However, the rate of the increase of the memory density has not been sufficient. Thus, new and useful approaches to increase the memory density of the memory card are also required in addition to relying on the increase of the memory density of the memory chips.
One such approach to increasing the memory density of the memory card is to use a plurality of identical memory chips. For example, as shown in FIG. 1, two memory chips 13 are stacked, or as shown in FIG. 2, two memory chips 23 are mounted side by side.
With reference to FIGS. 1 and 2, conventional memory card 10 or 20 has a structure where memory chips 13 or 23 are mounted within a package 11 or 21, and the packages 11 or 21 are positioned on a card body 12 or 22, i.e., “a base card.” Herein, a printed circuit board 14 or 24 is used in the package 11 or 21, and the memory chips 13 or 23 are mounted on one of the surfaces of the printed circuit board 14 or 24 and a plurality of contact pads 15 or 25 are formed on the other surface of the printed circuit board 14 or 24. The memory chips 13 or 23 are electrically interconnected to the printed circuit board 14 or 24 by wire bonding or flip chip bonding and to the contact pads 15 or 25 through the wiring patterns and the via holes (not shown) of the printed circuit boards 14 or 24. The memory chips 13 or 23 are encapsulated with a molding resin 16, 26. As shown in FIG. 1, a controller chip 17 may be additionally used.
In the above-described conventional memory cards 10 or 20 it is difficult to mount more than two memory chips, unless the sizes of the memory chips 13 or 23 are reduced. Therefore, the density of the memory card as a whole cannot exceed twice the density of one memory chip.
Particularly, as shown in FIG. 1, the upper chip 13 a should be off-set from an edge of the underlying lower chip 13 b so as to expose the chip pads 18 b of the lower chip 13 b for electrical interconnection. Moreover, the chip pads 18 a or 18 b should be formed on the upper surface of each chip 13 a or 13 b along only one of the edges. In addition, the chip pads 18 a, 18 b of the upper and the lower chips 13 a, 13 b, respectively, perform the same function and are connected to pads 14 a formed on the substrate via wire bonding. Therefore, the size of the pads 14 a should be sufficiently large so that both the upper and lower bonding wires 19 can be electrically connected in common thereto. In the structure shown in above-described memory card 10, it is difficult to stack more than two memory chips 13 due to the following problems.
First, when the chips are stacked as shown in FIG. 1, more side space within the package is required if more chips are being stacked. However, in a standard memory card, the available space is very limited. Thus, the number of chips that can be stacked is restricted.
Second, if more chips are stacked, longer bonding wires should be used. However, the longer bonding wires may result in undesirable electrical shorts between adjacent wires by, for example, wire sweeping, a problem that is well known in the art.
Third, the warpage of the printed circuit board becomes serious due to the difference in the coefficient of thermal expansion between the chips and the board. Several problems such as delamination on interface, poor adhesion, difficulty in stacking of chips, are caused by the warpage.
Fourth, a package containing multiple chips may sometimes fail electrical or burn-in test steps due to one defective chip therein although the other chips are good. This causes great losses in yield, and therefore a so-called known good die (KGD) which is an unpackaged die that has been tested to a quality and reliability level equal to the packaged product before packaging are required for the multi-chip package.
Another conventional memory card as shown in FIG. 2 has been proposed to provide a solution to some of the problems described above, since chips are mounted side-by-side on the board without stacking. However, this memory card structure still has the above-mentioned problems, e.g., poor yield, because a single package includes multiple chips. Further, unless the size of the memory chip 23 is reduced, there still remains a drawback in that that the number of the memory chips mounted side-by-side within the package 21 that can be loaded is limited.
SUMMARY OF THE INVENTION
The present invention increases memory density of a memory card by improving the structure of the memory card. Particularly, the number of the memory chips within the memory card can be increased even without reducing the size of the memory chip or increasing the density of the memory chip.
The present invention further prevents several problems in the manufacturing process or the test process caused by using a plurality of the memory chips.
According to one embodiment of the present invention, a memory card comprises a base card and two packages connected to the base card. The two packages are attached to the base card and face each other. With reference to the two packages, a first package comprises a first substrate and at least one memory chip, and a second package comprises a second substrate and at least one memory chip. A first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card. A second surface of the first substrate has first connection pads formed thereon and connected to the base card. The memory chips are mounted on the second surface and electrically connected to each other. A third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon and connected to the base card. The memory chips are mounted on the fourth surface and electrically connected to each other. The base card includes internal connection means, and the first and the second connection pads are electrically connected to the internal connection means. The external connection pads provide electrical connection between said internal connection means to an external system.
By connecting two packages to the base card, the memory card of the present invention can increase the memory density of the smart cart four times or more. Also, the problems encountered in the conventional smart card manufacturing process or the test process can be prevented.
BRIEF DESCRIPTION OF THE DRAWINGS
The various features and advantages of the present invention will be readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which:
FIG. 1 is a cross-sectional view of a conventional memory card;
FIG. 2 is a cross-sectional view of another conventional memory card;
FIG. 3 is a cross-sectional view of a memory card in accordance with an embodiment of the present invention;
FIG. 4 is an exploded isometric view of the memory card of FIG. 3;
FIG. 5 is an isometric view showing a connection method between the chip pads of the upper and the lower packages of the memory card in the present invention;
FIG. 6 is an isometric view showing another connection method between the chip pads of the upper and the lower packages of the memory in the present invention;
FIG. 7 is a cross-sectional view of a memory card in accordance with another embodiment of the present invention; and
FIG. 8 is a cross-sectional view of a memory card in accordance with still another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 3 is a cross-sectional view of a memory card 100 in accordance with an embodiment of the present invention. As shown in FIG. 3, the memory card 100 includes two packages 110, 140. Each package preferably includes two memory chips 130 a, 130 b or 160 a, 160 b. Thus, the memory card 100 has four-fold density. (Thus, the density of the memory card 100 is increased at least two times more than the density of a conventional memory card.) On the other hand, since each package 110 or 140 contains only two memory chips 130 a, 130 b or 160 a, 160 b therein, the problems shown in conventional memory card structure can be avoided.
In order to place two packages 110, 140 within a single memory card 100, the base card 170 has a different structure from the conventional base card. FIG. 4 is an exploded isometric view of the memory card 100 of FIG. 3. With reference to FIGS. 3 and 4, the base card 170 has an opening in the center portion thereof. And upper and lower packages 110, 140 are inserted into the opening of the base card 170 from the top and the bottom thereof, respectively. Thus, two packages 110, 140 are face each other. The packages 110, 140 are physically attached to the base card 170 by an adhesion sheet 172. Alternatively, a liquid adhesive may be used, as shown in FIG. 7.
Each package 110 or 140 comprises a corresponding substrate 120 or 150. With reference to FIGS. 3, 4 and 5, the structure of each package 110, 140 is described below. The memory chips 130 a, 130 b or 160 a, 160 b are mounted on inner surface 121 b or 151 b of the substrate 120 or 150. The substrate 120 or 150 is placed on the base card 170, and an encapsulant 133, 163 is used to protect the mounted chips. Printed circuit boards or wiring films are used as the substrates 120, 150. A polymer material such as an epoxy-molding compound is used as the encapsulant 133, 163. As well known, the printed circuit board is made by forming copper wirings on an insulating plate such as BT resin (Bismaleimide Triazine Resin), FR-4, or FR-5, and the wiring film is made by forming copper wirings on the polyimide film. Alternatively, other conventional methods or material to form the printed circuit board or the wiring film can be utilized for the purpose of the present invention.
The copper wirings form substrate pads 123, 153, wiring patterns 124, 154, and connection pads 125, 155 on the inner surface 121 b, 151 b of the upper and the lower packages 110, 140, and external connection pads 122 on an outer surface 121 a near an edge of the upper package 110. The connection pads 125 of the upper package 110 are electrically connected to the external connection pads 122 through via holes 126 formed through the substrate 120. The substrate pads 123, 153, the connection pads 125, 155, and the external connection pads 122 preferably are plated with nickel or gold. Further, the inner walls of the via holes 126 preferably are plated with copper. The external connection pads 122 provide electrical connection to an external system (not shown), when the memory card is inserted to the external system such as the MP3 player or the digital camera. The external connection pads 122 are formed on only one surface of the memory card 100, that is, the upper package 110. FIG. 4 describes nine (9) external connection pads 122 aligned in a row. However, the present invention allows many variations and modifications in the number and the arrangement shape of the external connection pads. FIG. 5 shows three (3) connection pads 125, 155, three (3) substrate pads 123, 153 and three (3) chip pads 131, 161. However, actual number of each group of pads is the same as the number of the external connection pads 122, e.g., nine (9) and is reduced in the drawings for simplicity.
Two identical memory chips 130 a, 130 b, or 160 a, 160 b are mounted on the corresponding substrate 120, or 150. The lower chips 130 a, 160 a are attached to the inner surfaces 121 b, 151 b by an adhesive (not shown), and the upper chips 130 b, 160 b are stacked on the lower chips 130 a, 160 a. Herein, the chip pads 131, 161 of the memory chips 130 a, 130 b, and 160 a, 160 b are formed on one edge of the upper surface of each chip. The upper chips 130 b, 160 b are stacked on the lower chips 130 a, 160 a, and are off-set from an edge of the lower chips to expose the chip pads 131, 161 of the lower chips 130 a, 160 a. As for memory chips 130 a, 130 b and 160 a, 160 b, non-volatile memory chips such as NAND-type or NOR-type flash memory chips are preferably used. Further, a controller chip 132 (not shown in FIG. 5) can be additionally used. If the controller chip is installed on the external system (not shown), the controller chip needs not be mounted on the memory card 100.
The chip pads 131, 161 are electrically connected to the corresponding substrate pads 123, 153 with bonding wires 134, 164. Two bonding wires 134 or 164, which interconnect the upper chip 130 b or 160 b to the lower chip 130 a or 160 a, are connected in common to a single substrate pad 123 or 153. The substrate pads 123 or 153 are connected to the connection pads 125 or 155 through the wiring patterns 124 or 154. Accordingly, each of the connection pads 125, 155 is electrically connected to two chip pads 131, 161.
When the upper and the lower packages 110, 140 are mechanically connected to the base card 170, the connection pads 125, 155 of each package 110, 140 are connected to internal connection means 171 on the base card 170. Therefore, the connection pads 125, 155 are connected to each other through the internal connection means 171, and thereby electrically connected to the external connection pads 122. Since one external connection pad 122 is electrically connected to four (4) chip pads 131, 161 through two (2) connection pads 125, 155, the memory card 100 has a fourfold (extended) density, compared to the density of any one memory chip 130 a, 130 b, 160 a, or 160 b.
The internal connection means 171 formed on the base card 170 are metal patterns, preferably made of copper. The metal patterns 171 can be formed with the similar method of forming the copper wirings on the substrates 120, 150. Preferably, portions of the metal patterns 171, i.e., the portions contacting the connection pads 125, 155 of the substrate 120, 150, are plated with solder. As above-described, the packages 110, 140 are mechanically connected to the base card 170 through the adhesion sheet 172, and this process is carried out at 200° C. temperature. Therefore, if the metal patterns 171 are plated with solder comprising lead and tin in a ratio of 4:6 having a melting point around 200° C., the connection pads 125, 155 can be connected to the metal patterns 171 without any additional process steps.
The chip pads 131, 161 having the same function are connected in common to the same substrate pad 123, 153, respectively, and eventually to the same external connection pad 122. Because the upper and the lower packages 110, 140 are connected to the base card 170, the upper and the lower packages 110, 140 being positioned opposite to each other, the chip pads 131 of the upper package 110 and the chip pads 161 of the lower package 140 face each other. Therefore, in order to connect the chip pads 131 to the corresponding chip pads 161 having the same function as the chip pads 131, the present invention preferably employs two methods described in detail below.
As shown in FIG. 5, one method is to use the substrates 120, 160, each having the connection pads 125 or 155, which face each other. The four memory chips 130 a, 130 b and 160 a, 160 b mounted on the upper and the lower packages 110 and 140, respectively, are all the same devices. For example, the chip pad 131 (A1) of the upper package 110 corresponds with the chip pad 161 (A1) of the lower package 140. Because the upper and the lower packages 110, 140 oppose each other, if the same substrates were used, the connection pads 125, 155 would not correspond with each other. Instead the substrates must be mirror images of one another. Therefore, the wiring patterns 124 on one of the substrates (the substrate 120 of the upper package 120 in FIG. 5) are formed in a manner that the chip pad 131 (A1) corresponds to the connection pad 125 (B3). Thus, the connection pads 125, 155 of the substrates 120, 150 face each other. Further, the connection pads 125, 155, respectively connected to two corresponding chip pads 131, 161, can be connected to the same external connection pads 122 shown in FIG. 4.
Alternatively, as shown in FIG. 6, memory chips 130′, 160′ having dummy pads 135, 165 formed thereon can be used to implement the present invention. The dummy pads 135, 165 correspond with the chip pads 131, 161. The dummy pads 135, 165 are formed on the other edge being opposite to the edge provided with the chip pads 131, 161, respectively. For example, in FIG. 6, the dummy pads 135 (C1), 165 (C1) correspond with chip pads 131 (A1), 161 (A1), respectively. By using the memory chip 130, 160 having the dummy pads 135, 165, two packages 110, 160 can employ the same substrates 120, 150, i.e., substrates having identical wiring or printed circuit patterns. In this embodiment, the chips 130′ or 160′ of either package are stacked turned around 180° degrees. That is, the chip pads 161 (A1) of the lower package 140′ and the dummy pads 135 (C1) of the upper package 110′ are respectively connected to the corresponding connection pads 125 (B1), 155 (B1) to be connected to the same external connection pads 122 shown in FIG. 4.
Another embodiment of the present invention uses via holes as the internal connection means between the base card and the packages and is described with reference to FIG. 7. Two packages 210, 240 are fixedly mounted within the base card 270. And the space between two packages 210, 240 and the base card 270 is filled with the liquid adhesive 272. Herein, via holes 271 formed through the base card 270 are used as the electrical internal connection means. An epoxy-resin compound with a predetermined viscosity can be used as the liquid adhesive 272. The via holes 271 of the base card 270 are plated or filled with a conductive material such as copper or solder.
As shown in FIG. 7, two memory chips 230, 260 are mounted side-by-side on each substrate 220 or 250 within the memory card 200. Herein, the chip pads need not be formed on only one edge of the chips, and the two same functional chip pads need not wire-bonded in common to one substrate pad. Although the same functional chip pads are connected to different substrate pads, eventually the chip pads can be connected to the same connection pad through the wiring patterns. Further, to electrically connect the memory chips 230, 260 to the substrates 220, 250, other conventional techniques such as flip chip bonding using the metal bumps 234, 264 can used rather than wire bonding.
Hereinafter, still another embodiment of the present invention is described with reference to FIG. 8. This embodiment uses an anisotropic conductive film (ACF) to electrically interconnect the base card and the packages. As shown in FIG. 8, the anisotropic conductive film 380 is interposed between the internal connection means 371 of the base card 370 and the substrate 320 of the package 310. The connection pads 325 of the substrate 320 are electrically connected to the internal connection means 371 of the base card 370 through conductive particles 382 within the anisotropic conductive film 380. The anisotropic conductive film 380 comprises the conductive particles 382 within a resin 384. When the package 310 is pressed to the base card 370 by the thermocompression, the conductive particles 382 are fixed between the connection pads 325 and the internal connection means 371, thereby providing an electrical path. Therefore, the anisotropic conductive film 380 physically connects the substrate 320 to the base card 370.
In all the above-described embodiments, two memory chips are mounted on each package. If the memory chip is miniaturized and more than two memory chips are mounted on each package, this will still fall within the spirit and scope of the present invention. For example, a plurality of chips or a plurality of two-chip stacks may be mounted side by side. Therefore, it is possible to increase the density of the memory card four times or more. However, in case of mounting several chips on one package, a trade-off between the memory density extension and loss caused by the test failure, and the increase of the production cost due to the use of the KGD should be considered.
As described above, the present invention has advantages in that the density of the memory card can be increased without increasing the number of the memory chip mounted in a package by connecting two substrates in one memory card. That is, the present invention prevents the problems encountered in the conventional smart card manufacturing process or the test process due to use of plural memory chips, and increase the density of the memory card.
Although preferred embodiments of the present invention have been described in detail hereinabove, it should be understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the art will still fall within the spirit and scope of the present invention as defined in the appended claims.

Claims (29)

What is claimed is:
1. A memory card comprising:
a base card having an opening extending therethrough in a center portion thereof; and
first and second packages fixedly mounted within the opening of the base card and facing each other,
said first package including:
a first substrate having a first surface and a second surface, said first surface having a plurality of external connection pads formed thereon and exposed from the memory card, and said second surface having first connection pads formed thereon; and
a first memory chip mounted on the second surface, the first memory chip electrically connected to the first connection pads; and said second package including:
a second substrate having a third surface and a fourth surface, said third surface exposed from the memory card, and said fourth surface having second connection pads formed thereon; and
a second memory chip mounted on the fourth surface, the second memory chip electrically connected to the second connection pads;
wherein the base card includes internal connection means, and the first and the second connection pads are electrically connected to the internal connection means, and
wherein the external connection pads provide electrical connection between said internal connection means and an external system.
2. The memory card of claim 1, wherein the second surface of the first package and the fourth surface of the second package are encapsulated with a molding compound to protect the memory chips therein.
3. The memory card of claim 1, further comprising one or more additional chips electrically interconnected to the first chip and one or more additional chips are electrically interconnected to the second chip.
4. The memory card of claim 1, wherein the internal connection means of the base card are metal patterns formed along a surface of the base card.
5. The memory card of claim 2, wherein the internal connection means of the base card are metal patterns formed along a surface of the base card.
6. The memory card of claim 1, wherein the internal connection means of the base card includes via holes formed through the base card, said via holes having therein a conductive material.
7. The memory card of claim 2, wherein the internal connection means of the base card are via holes formed through the base card, said via holes having therein a conductive material.
8. The memory card of claim 1, further comprising an adhesive sheet or a liquid adhesive interposed between each package and the base card to connect each package to the base card.
9. The memory card of claim 2, further comprising an adhesion sheet or a liquid adhesive interposed between each package and the base card to connect each package to the base card.
10. The memory card of claim 1, further comprising an anisotropic conductive film interposed between the internal connection means of the base card and the package to connect each package to the base card physically and electrically.
11. The memory card of claim 2, further comprising an anisotropic conductive film interposed between the internal connection means of the base card and the package to connect each package to the base card physically and electrically.
12. The memory card of claim 1, wherein the memory chips are stacked on each substrate, the chip stacked on top being off-set from an edge of an underlying chip.
13. The memory card of claim 2, wherein the memory chips are stacked with lateral off-set on each substrate.
14. The memory card of claim 1, wherein the memory chips are mounted side-by-side on each substrate.
15. The memory card of claim 2, wherein the memory chips are mounted side-by-side on each substrate.
16. The memory card of claim 1, wherein the memory chips are a non-volatile memory chip.
17. The memory card of claim 2, wherein the memory chips are a non-volatile memory chip.
18. The memory card of claim 1, wherein the first package further includes a controller chip.
19. The memory card of claim 2, wherein the first package further includes a controller chip.
20. The memory card of claim 1, wherein the first and the second substrates are a printed circuit board.
21. The memory card of claim 2, wherein the first and the second substrates are a printed circuit board.
22. The memory card of claim 1, wherein the first and the second substrates are wiring films.
23. The memory card of claim 2, wherein the first and the second substrates are wiring films.
24. The memory card of claim 1, wherein the first and the second connection pads face each other.
25. The memory card of claim 2, wherein the first and the second connection pads face each other.
26. The memory card of claim 1, wherein the memory chip comprises dummy pads facing chip pads.
27. The memory card of claim 2, wherein the memory chip includes dummy pads facing chip pads.
28. The memory card of claim 1, wherein the base card has first and second ledges to support the first and second substrates, respectively, within the opening.
29. The memory card of claim 1, wherein the opening is sized to receive the first and second packages from a top and bottom of the base card, respectively.
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Cited By (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030034552A1 (en) * 2001-04-02 2003-02-20 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20040041271A1 (en) * 2002-08-29 2004-03-04 Storli Farrah J. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20040084538A1 (en) * 2000-01-25 2004-05-06 Hitachi, Ltd. IC card
US20040145063A1 (en) * 2003-01-29 2004-07-29 Sutherland Ivan E. Integrated circuit assembly module that supports capacitive communication between semiconductor dies
US20040195667A1 (en) * 2003-04-04 2004-10-07 Chippac, Inc Semiconductor multipackage module including processor and memory package assemblies
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US20050280164A1 (en) * 2003-10-15 2005-12-22 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20060014317A1 (en) * 2002-04-19 2006-01-19 Farnworth Warren M Integrated circuit package having reduced interconnects
US20060012018A1 (en) * 2004-07-13 2006-01-19 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20060133058A1 (en) * 2004-12-22 2006-06-22 Soon-Yong Hur Memory module and connection interface between the memory module and circuit board
US20060172463A1 (en) * 2002-09-17 2006-08-03 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20060170091A1 (en) * 2002-09-17 2006-08-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20060176673A1 (en) * 2005-01-31 2006-08-10 Stmicroelectronics S.R.L Removable data storage device and related assembling method
US20060220210A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20060244117A1 (en) * 2005-04-29 2006-11-02 Stats Chippac, Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US20060249851A1 (en) * 2005-05-05 2006-11-09 Stats Chippac Ltd. Multiple Chip Package Module Including Die Stacked Over Encapsulated Package
US20060261489A1 (en) * 2005-05-23 2006-11-23 Yasuo Takemoto Semiconductor memory card and method of fabricating the same
US20060284299A1 (en) * 2005-06-20 2006-12-21 Stats Chippac Ltd. Module Having Stacked Chip Scale Semiconductor Packages
US20070015314A1 (en) * 2004-05-24 2007-01-18 Chippac, Inc Adhesive/Spacer Island Structure for Multiple Die Package
US20070018296A1 (en) * 2004-05-24 2007-01-25 Chippac, Inc Stacked Semiconductor Package having Adhesive/Spacer Structure and Insulation
US20070065987A1 (en) * 2001-06-21 2007-03-22 Mess Leonard E Stacked mass storage flash memory package
US20070295982A1 (en) * 2006-06-27 2007-12-27 Hana Micron Co., Ltd. Micro universal serial bus memory package and manufacturing method the same
US20080150158A1 (en) * 2006-12-20 2008-06-26 Chee Keong Chin Integrated circuit package system with offset stacked die
US20080179729A1 (en) * 2005-03-31 2008-07-31 Il Kwon Shim Encapsulant cavity integrated circuit package system
US20090209064A1 (en) * 2006-04-28 2009-08-20 Somchai Nonahasitthichai Lead frame land grid array
US7652376B2 (en) 2006-01-04 2010-01-26 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7687315B2 (en) 2005-04-29 2010-03-30 Stats Chippac Ltd. Stacked integrated circuit package system and method of manufacture therefor
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US20100233854A1 (en) * 2009-03-12 2010-09-16 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20100311208A1 (en) * 2008-05-22 2010-12-09 Utac Thai Limited Method and apparatus for no lead semiconductor package
US20100327432A1 (en) * 2006-09-26 2010-12-30 Utac Thai Limited Package with heat transfer
US20110013353A1 (en) * 2009-07-14 2011-01-20 Samsung Electronics Co., Ltd. Multi-chip package structure suitable for multi-processor system having memory link architecture
US20110018111A1 (en) * 2009-07-23 2011-01-27 Utac Thai Limited Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US20110039371A1 (en) * 2008-09-04 2011-02-17 Utac Thai Limited Flip chip cavity package
US20110133319A1 (en) * 2009-12-04 2011-06-09 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US20110147931A1 (en) * 2006-04-28 2011-06-23 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US20110157858A1 (en) * 2009-12-24 2011-06-30 Samsung Electronics Co., Ltd. System-in-package having embedded circuit boards
US20110198752A1 (en) * 2006-04-28 2011-08-18 Utac Thai Limited Lead frame ball grid array with traces under die
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US20110221051A1 (en) * 2010-03-11 2011-09-15 Utac Thai Limited Leadframe based multi terminal ic package
US20110272798A1 (en) * 2010-05-06 2011-11-10 Hynix Semiconductor Inc. Chip unit and stack package having the same
US8338922B1 (en) 2007-11-06 2012-12-25 Utac Thai Limited Molded leadframe substrate semiconductor package
US20130015570A1 (en) * 2011-07-13 2013-01-17 Kabushiki Kaisha Toshiba Stacked semiconductor package and manufacturing method thereof
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487420B1 (en) * 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8552551B2 (en) 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US9000590B2 (en) 2012-05-10 2015-04-07 Utac Thai Limited Protruding terminals with internal routing interconnections semiconductor device
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9805955B1 (en) 2015-11-10 2017-10-31 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG100635A1 (en) 2001-03-09 2003-12-26 Micron Technology Inc Die support structure
US6798055B2 (en) 2001-03-12 2004-09-28 Micron Technology Die support structure
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
SG95637A1 (en) * 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme
EP1576589A4 (en) * 2002-11-18 2006-06-07 Storcard Inc Secure transaction card with a large storage volume
US7217597B2 (en) 2004-06-22 2007-05-15 Micron Technology, Inc. Die stacking scheme
TW200612345A (en) * 2004-10-07 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof
TWI239698B (en) * 2004-10-07 2005-09-11 Advanced Flash Memory Card Tec Structure of memory card and producing method thereof
US20060289500A1 (en) * 2005-05-11 2006-12-28 Naohisa Okumura Semiconductor memory card comprising semiconductor memory chip
US7323968B2 (en) * 2005-12-09 2008-01-29 Sony Corporation Cross-phase adapter for powerline communications (PLC) network
KR100725458B1 (en) * 2005-12-23 2007-06-07 삼성전자주식회사 Multi-chip package of common temperature compensated self refresh signal
US7622333B2 (en) * 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US8432026B2 (en) * 2006-08-04 2013-04-30 Stats Chippac Ltd. Stackable multi-chip package system
US7645638B2 (en) * 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
TW200814249A (en) * 2006-09-12 2008-03-16 Chipmos Technologies Inc Stacked chip package structure with lead-frame having bus bar
US7683467B2 (en) * 2006-12-07 2010-03-23 Stats Chippac Ltd. Integrated circuit package system employing structural support
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
KR100849182B1 (en) 2007-01-22 2008-07-30 삼성전자주식회사 Semiconductor card package and method of forming the same
KR101344021B1 (en) 2007-12-24 2014-01-15 삼성전자주식회사 Memory card and memory storage device using the same
US8014166B2 (en) * 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
KR101498676B1 (en) 2008-09-30 2015-03-09 삼성전자주식회사 3-Dimensional Semiconductor Device
US8472199B2 (en) * 2008-11-13 2013-06-25 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
JP2010141098A (en) * 2008-12-11 2010-06-24 Shinko Electric Ind Co Ltd Substrate with built-in electronic components and method of manufacturing the same
US8644030B2 (en) 2009-01-14 2014-02-04 Micron Technology, Inc. Computer modules with small thicknesses and associated methods of manufacturing
KR102178829B1 (en) * 2013-11-20 2020-11-13 삼성전자 주식회사 Semiconductor memory device
US10276541B2 (en) 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
WO2017023060A1 (en) * 2015-07-31 2017-02-09 송영희 Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same
US11133261B2 (en) * 2017-09-29 2021-09-28 Intel Corporation Electronic device packaging
JP2019153658A (en) * 2018-03-02 2019-09-12 富士通株式会社 Board module and board module manufacturing method
US11373936B2 (en) * 2019-11-14 2022-06-28 Rohde & Schwarz Gmbh & Co. Kg Flat no-leads package, packaged electronic component, printed circuit board and measurement device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508565A (en) * 1992-12-18 1996-04-16 Fujitsu Limited Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips
US5583748A (en) * 1993-09-30 1996-12-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor module having multiple circuit boards
US5910685A (en) * 1987-06-24 1999-06-08 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5939779A (en) * 1996-05-17 1999-08-17 Lg Semicon Co., Ltd. Bottom lead semiconductor chip stack package
US6222265B1 (en) * 1997-03-10 2001-04-24 Micron Technology, Inc. Method of constructing stacked packages
US6239496B1 (en) * 1999-01-18 2001-05-29 Kabushiki Kaisha Toshiba Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
US6297960B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6383845B2 (en) * 1997-09-29 2002-05-07 Hitachi, Ltd. Stacked semiconductor device including improved lead frame arrangement

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0679990A (en) * 1992-09-04 1994-03-22 Mitsubishi Electric Corp Ic memory card
JPH0730009A (en) * 1993-07-15 1995-01-31 Toshiba Corp Semiconductor device and manufacture thereof
JPH10250275A (en) * 1997-03-18 1998-09-22 Hitachi Ltd Memory card and its manufacture
KR19990069509A (en) * 1998-02-10 1999-09-06 구본준 Stacked memory module device and method of manufacturing memory module using same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910685A (en) * 1987-06-24 1999-06-08 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6262488B1 (en) * 1987-06-24 2001-07-17 Hitachi Ltd. Semiconductor memory module having double-sided memory chip layout
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips
US5508565A (en) * 1992-12-18 1996-04-16 Fujitsu Limited Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package
US5583748A (en) * 1993-09-30 1996-12-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor module having multiple circuit boards
US5939779A (en) * 1996-05-17 1999-08-17 Lg Semicon Co., Ltd. Bottom lead semiconductor chip stack package
US6222265B1 (en) * 1997-03-10 2001-04-24 Micron Technology, Inc. Method of constructing stacked packages
US6383845B2 (en) * 1997-09-29 2002-05-07 Hitachi, Ltd. Stacked semiconductor device including improved lead frame arrangement
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6297960B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US6239496B1 (en) * 1999-01-18 2001-05-29 Kabushiki Kaisha Toshiba Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same

Cited By (219)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090129A1 (en) * 2000-01-25 2005-04-28 Hitachi, Ltd. IC card
US20060157572A1 (en) * 2000-01-25 2006-07-20 Renesas Technology Corp. IC card
US20060157573A1 (en) * 2000-01-25 2006-07-20 Renesas Technology Corp. IC card
US7234644B2 (en) 2000-01-25 2007-06-26 Renesas Technology Corp. IC card
US7055757B2 (en) 2000-01-25 2006-06-06 Renesas Technology Corp. IC card
US7048197B2 (en) 2000-01-25 2006-05-23 Renesas Technology Corp. IC card
US20040084538A1 (en) * 2000-01-25 2004-05-06 Hitachi, Ltd. IC card
US7303138B2 (en) 2000-01-25 2007-12-04 Renesas Technology Corp. Integrated circuit card having staggered sequences of connector terminals
US20080257968A1 (en) * 2000-01-25 2008-10-23 Hirotaka Nishizawa Ic card
US7552876B2 (en) 2000-01-25 2009-06-30 Renesas Technology Corp. IC card
US20050090128A1 (en) * 2000-01-25 2005-04-28 Hitachi, Ltd. IC card
US7053471B2 (en) * 2001-04-02 2006-05-30 Renesas Technologies Corp. Memory card
US20060033191A1 (en) * 2001-04-02 2006-02-16 Renesas Technology Corp. Memory card
US20060220203A1 (en) * 2001-04-02 2006-10-05 Renesas Technology Corp. Memory card
US20030117785A1 (en) * 2001-04-02 2003-06-26 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US7233058B2 (en) 2001-04-02 2007-06-19 Renesas Technology Corp. Memory card with an adaptor
US20090283885A1 (en) * 2001-04-02 2009-11-19 Renesas Technology Corp. Semiconductor Device and a Method of Manufacturing the Same
US6858925B2 (en) 2001-04-02 2005-02-22 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US7239011B2 (en) 2001-04-02 2007-07-03 Renesas Technology Corp. Memory card with a cap having indented portions
US7271475B2 (en) 2001-04-02 2007-09-18 Renesas Technology Corp. Memory card with connecting portions for connection to an adapter
US20060220204A1 (en) * 2001-04-02 2006-10-05 Renesas Technology Corp. Memory card
US7294918B2 (en) 2001-04-02 2007-11-13 Renesas Technology Corp. Memory card with connecting portions for connection to an adapter
US20030034552A1 (en) * 2001-04-02 2003-02-20 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20050280131A1 (en) * 2001-04-02 2005-12-22 Renesas Technology Corp. Memory card
US7998792B2 (en) 2001-06-21 2011-08-16 Round Rock Research, Llc Semiconductor device assemblies, electronic devices including the same and assembly methods
US20100148331A1 (en) * 2001-06-21 2010-06-17 Round Rock Research, Llc Semiconductor devices including semiconductor dice in laterally offset stacked arrangement
US20100078793A1 (en) * 2001-06-21 2010-04-01 Micron Technology, Inc. Semiconductor device assemblies, electronic devices including the same and assembly methods
US8049342B2 (en) 2001-06-21 2011-11-01 Round Rock Research, Llc Semiconductor device and method of fabrication thereof
US20070065987A1 (en) * 2001-06-21 2007-03-22 Mess Leonard E Stacked mass storage flash memory package
US7704794B2 (en) 2001-06-21 2010-04-27 Micron Technology, Inc. Method of forming a semiconductor device
US20090286356A1 (en) * 2001-06-21 2009-11-19 Micron Technology, Inc. Stacked mass storage flash memory package
US7999378B2 (en) 2001-06-21 2011-08-16 Round Rock Research, Llc Semiconductor devices including semiconductor dice in laterally offset stacked arrangement
US20100148372A1 (en) * 2002-04-19 2010-06-17 Micron Technology, Inc. Integrated circuit package having reduced interconnects
US8115269B2 (en) 2002-04-19 2012-02-14 Round Rock Research, Llc Integrated circuit package having reduced interconnects
US20060014317A1 (en) * 2002-04-19 2006-01-19 Farnworth Warren M Integrated circuit package having reduced interconnects
US7674652B2 (en) 2002-04-19 2010-03-09 Micron Technology, Inc. Methods of forming an integrated circuit package
US7218003B2 (en) * 2002-08-29 2007-05-15 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7572725B2 (en) 2002-08-29 2009-08-11 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20050167822A1 (en) * 2002-08-29 2005-08-04 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20070040273A1 (en) * 2002-08-29 2007-02-22 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20040041271A1 (en) * 2002-08-29 2004-03-04 Storli Farrah J. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US6885101B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7018869B2 (en) 2002-08-29 2006-03-28 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20070292990A1 (en) * 2002-09-17 2007-12-20 Marcos Karnezos Semiconductor multi-package module having wire bond interconnect between stacked packages
US20100200966A1 (en) * 2002-09-17 2010-08-12 Marcos Karnezos Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US7205647B2 (en) 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7682873B2 (en) 2002-09-17 2010-03-23 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US8143100B2 (en) 2002-09-17 2012-03-27 Chippac, Inc. Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages
US20060172463A1 (en) * 2002-09-17 2006-08-03 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20060170091A1 (en) * 2002-09-17 2006-08-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US7279361B2 (en) 2002-09-17 2007-10-09 Chippac, Inc. Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages
US7935572B2 (en) 2002-09-17 2011-05-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US7169642B2 (en) 2002-10-08 2007-01-30 Chippac, Inc Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US20060138649A1 (en) * 2002-10-08 2006-06-29 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20040113254A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
US20080171402A1 (en) * 2002-10-08 2008-07-17 Marcos Karnezos Method of fabricating a semiconductor multi-package module having inverted land grid array (lga) package stacked over ball grid array (bga) package
US20040113253A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20040113275A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20040113255A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US20040119152A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US7163842B2 (en) 2002-10-08 2007-01-16 Chip Pac, Inc. Method of fabricating a semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA)
US20040119153A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US7166494B2 (en) 2002-10-08 2007-01-23 Chippac, Inc. Method of fabricating a semiconductor stacked multi-package module having inverted second package
US20040124518A1 (en) * 2002-10-08 2004-07-01 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package and electrically shielded first package
US7687313B2 (en) 2002-10-08 2010-03-30 Stats Chippac Ltd. Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package
US20060172459A1 (en) * 2002-10-08 2006-08-03 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20060172461A1 (en) * 2002-10-08 2006-08-03 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20060158295A1 (en) * 2002-10-08 2006-07-20 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US7101731B2 (en) 2002-10-08 2006-09-05 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20070111388A1 (en) * 2002-10-08 2007-05-17 Chippac, Inc. Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (BGA) Package
US20070114648A1 (en) * 2002-10-08 2007-05-24 Chippac, Inc. Semiconductor Stacked Multi-Package Module Having Inverted Second Package
US20070117267A1 (en) * 2002-10-08 2007-05-24 Chippac, Inc. Semiconductor Multi-Package Module Having Inverted Land Grid Array (LGA) Package Stacked Over Ball Grid Array (BGA) Package
US6933598B2 (en) 2002-10-08 2005-08-23 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package and electrically shielded first package
US20060141668A1 (en) * 2002-10-08 2006-06-29 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US20050148113A1 (en) * 2002-10-08 2005-07-07 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US7247519B2 (en) 2002-10-08 2007-07-24 Chippac, Inc. Method for making a semiconductor multi-package module having inverted bump chip carrier second package
WO2004034433A3 (en) * 2002-10-08 2004-08-26 Chippac Inc Semiconductor stacked multi-package module having inverted second package
US7364946B2 (en) 2002-10-08 2008-04-29 Chippac, Inc. Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US7061088B2 (en) 2002-10-08 2006-06-13 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US7057269B2 (en) 2002-10-08 2006-06-06 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US7288434B2 (en) 2002-10-08 2007-10-30 Chippac, Inc. Method for making semiconductor multi-package module having inverted second package and including additional die or package stacked on second package
US7053477B2 (en) * 2002-10-08 2006-05-30 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US7045887B2 (en) 2002-10-08 2006-05-16 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US7358115B2 (en) 2002-10-08 2008-04-15 Chippac, Inc. Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides
US7351610B2 (en) 2002-10-08 2008-04-01 Chippac, Inc. Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate
US6906416B2 (en) 2002-10-08 2005-06-14 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US6870271B2 (en) * 2003-01-29 2005-03-22 Sun Microsystems, Inc. Integrated circuit assembly module that supports capacitive communication between semiconductor dies
US20040145063A1 (en) * 2003-01-29 2004-07-29 Sutherland Ivan E. Integrated circuit assembly module that supports capacitive communication between semiconductor dies
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
US7306973B2 (en) 2003-04-04 2007-12-11 Chippac, Inc. Method for making a semiconductor multipackage module including a processor and memory package assemblies
US20040195667A1 (en) * 2003-04-04 2004-10-07 Chippac, Inc Semiconductor multipackage module including processor and memory package assemblies
US20060151867A1 (en) * 2003-04-04 2006-07-13 Chippac, Inc Semiconductor multipackage module including processor and memory package assemblies
US20090027863A1 (en) * 2003-04-04 2009-01-29 Marcos Karnezos Method for making a semiconductor multipackage module including a processor and memory package assemblies
US7749807B2 (en) 2003-04-04 2010-07-06 Chippac, Inc. Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies
US8154126B2 (en) 2003-10-15 2012-04-10 Round Rock Research, Llc Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20050280164A1 (en) * 2003-10-15 2005-12-22 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7772707B2 (en) 2003-10-15 2010-08-10 Round Rock Research, Llc Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20110163443A1 (en) * 2003-10-15 2011-07-07 Round Rock Research, Llc Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US7256074B2 (en) 2003-10-15 2007-08-14 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
WO2005059967A3 (en) * 2003-12-17 2009-06-04 Chippac Inc Multiple chip package module having inverted package stacked over die
WO2005059967A2 (en) * 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die
US8970049B2 (en) * 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
US8552551B2 (en) 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
US20070015314A1 (en) * 2004-05-24 2007-01-18 Chippac, Inc Adhesive/Spacer Island Structure for Multiple Die Package
US8030134B2 (en) 2004-05-24 2011-10-04 Chippac, Inc. Stacked semiconductor package having adhesive/spacer structure and insulation
US20070018296A1 (en) * 2004-05-24 2007-01-25 Chippac, Inc Stacked Semiconductor Package having Adhesive/Spacer Structure and Insulation
US8623704B2 (en) 2004-05-24 2014-01-07 Chippac, Inc. Adhesive/spacer island structure for multiple die package
US7253511B2 (en) 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20060012018A1 (en) * 2004-07-13 2006-01-19 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20100136744A1 (en) * 2004-07-13 2010-06-03 Marcos Karnezos Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20070278658A1 (en) * 2004-07-13 2007-12-06 Stats Chippac Ltd. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7692279B2 (en) 2004-07-13 2010-04-06 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7829382B2 (en) 2004-07-13 2010-11-09 Chippac, Inc. Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20060133058A1 (en) * 2004-12-22 2006-06-22 Soon-Yong Hur Memory module and connection interface between the memory module and circuit board
US7573724B2 (en) * 2004-12-22 2009-08-11 Samsung Electronics Co., Ltd. Memory module and connection interface between the memory module and circuit board
US7656676B2 (en) * 2005-01-31 2010-02-02 Marco Roveda Removable data storage device and related assembling method
US20060176673A1 (en) * 2005-01-31 2006-08-10 Stmicroelectronics S.R.L Removable data storage device and related assembling method
US8309397B2 (en) 2005-03-31 2012-11-13 Stats Chippac Ltd. Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof
US7372141B2 (en) 2005-03-31 2008-05-13 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US8021924B2 (en) 2005-03-31 2011-09-20 Stats Chippac Ltd. Encapsulant cavity integrated circuit package system and method of fabrication thereof
US20080179729A1 (en) * 2005-03-31 2008-07-31 Il Kwon Shim Encapsulant cavity integrated circuit package system
US20060220209A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20060220210A1 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides
US7429787B2 (en) 2005-03-31 2008-09-30 Stats Chippac Ltd. Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
US7855100B2 (en) 2005-03-31 2010-12-21 Stats Chippac Ltd. Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
US7687315B2 (en) 2005-04-29 2010-03-30 Stats Chippac Ltd. Stacked integrated circuit package system and method of manufacture therefor
US20060244117A1 (en) * 2005-04-29 2006-11-02 Stats Chippac, Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7429786B2 (en) 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7582960B2 (en) 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
US20060249851A1 (en) * 2005-05-05 2006-11-09 Stats Chippac Ltd. Multiple Chip Package Module Including Die Stacked Over Encapsulated Package
US20060261489A1 (en) * 2005-05-23 2006-11-23 Yasuo Takemoto Semiconductor memory card and method of fabricating the same
US7394148B2 (en) 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US20080220563A1 (en) * 2005-06-20 2008-09-11 Marcos Karnezos Module having stacked chip scale semiconductor packages
US20060284299A1 (en) * 2005-06-20 2006-12-21 Stats Chippac Ltd. Module Having Stacked Chip Scale Semiconductor Packages
US7645634B2 (en) 2005-06-20 2010-01-12 Stats Chippac Ltd. Method of fabricating module having stacked chip scale semiconductor packages
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7652376B2 (en) 2006-01-04 2010-01-26 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US20110198752A1 (en) * 2006-04-28 2011-08-18 Utac Thai Limited Lead frame ball grid array with traces under die
US8685794B2 (en) 2006-04-28 2014-04-01 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US20100127363A1 (en) * 2006-04-28 2010-05-27 Utac Thai Limited Very extremely thin semiconductor package
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8575762B2 (en) * 2006-04-28 2013-11-05 Utac Thai Limited Very extremely thin semiconductor package
US8652879B2 (en) 2006-04-28 2014-02-18 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US20110147931A1 (en) * 2006-04-28 2011-06-23 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US9099317B2 (en) 2006-04-28 2015-08-04 Utac Thai Limited Method for forming lead frame land grid array
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US20090209064A1 (en) * 2006-04-28 2009-08-20 Somchai Nonahasitthichai Lead frame land grid array
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8704381B2 (en) 2006-04-28 2014-04-22 Utac Thai Limited Very extremely thin semiconductor package
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US20070295982A1 (en) * 2006-06-27 2007-12-27 Hana Micron Co., Ltd. Micro universal serial bus memory package and manufacturing method the same
US7709946B2 (en) * 2006-06-27 2010-05-04 Hana Micron Co., Ltd. Micro universal serial bus (USB) memory package
US20100327432A1 (en) * 2006-09-26 2010-12-30 Utac Thai Limited Package with heat transfer
US8125077B2 (en) 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9899208B2 (en) 2006-12-14 2018-02-20 Utac Thai Limited Molded leadframe substrate semiconductor package
US9093486B2 (en) 2006-12-14 2015-07-28 Utac Thai Limited Molded leadframe substrate semiconductor package
US9711343B1 (en) 2006-12-14 2017-07-18 Utac Thai Limited Molded leadframe substrate semiconductor package
US9196470B1 (en) 2006-12-14 2015-11-24 Utac Thai Limited Molded leadframe substrate semiconductor package
US9099294B1 (en) 2006-12-14 2015-08-04 Utac Thai Limited Molded leadframe substrate semiconductor package
TWI499028B (en) * 2006-12-20 2015-09-01 Stats Chippac Ltd Integrated circuit package system with offset stacked die
US20080150158A1 (en) * 2006-12-20 2008-06-26 Chee Keong Chin Integrated circuit package system with offset stacked die
US8242607B2 (en) * 2006-12-20 2012-08-14 Stats Chippac Ltd. Integrated circuit package system with offset stacked die and method of manufacture thereof
US8338922B1 (en) 2007-11-06 2012-12-25 Utac Thai Limited Molded leadframe substrate semiconductor package
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US8071426B2 (en) 2008-05-22 2011-12-06 Utac Thai Limited Method and apparatus for no lead semiconductor package
US20100311208A1 (en) * 2008-05-22 2010-12-09 Utac Thai Limited Method and apparatus for no lead semiconductor package
US20110039371A1 (en) * 2008-09-04 2011-02-17 Utac Thai Limited Flip chip cavity package
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US8487420B1 (en) * 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8569877B2 (en) 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20110232693A1 (en) * 2009-03-12 2011-09-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20100230802A1 (en) * 2009-03-12 2010-09-16 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8431443B2 (en) 2009-03-12 2013-04-30 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20100233854A1 (en) * 2009-03-12 2010-09-16 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8367476B2 (en) 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20110013353A1 (en) * 2009-07-14 2011-01-20 Samsung Electronics Co., Ltd. Multi-chip package structure suitable for multi-processor system having memory link architecture
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US20110018111A1 (en) * 2009-07-23 2011-01-27 Utac Thai Limited Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US20110133319A1 (en) * 2009-12-04 2011-06-09 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US20110157858A1 (en) * 2009-12-24 2011-06-30 Samsung Electronics Co., Ltd. System-in-package having embedded circuit boards
US8722461B2 (en) 2010-03-11 2014-05-13 Utac Thai Limited Leadframe based multi terminal IC package
US20110221051A1 (en) * 2010-03-11 2011-09-15 Utac Thai Limited Leadframe based multi terminal ic package
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US20110272798A1 (en) * 2010-05-06 2011-11-10 Hynix Semiconductor Inc. Chip unit and stack package having the same
US8564141B2 (en) * 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US20130015570A1 (en) * 2011-07-13 2013-01-17 Kabushiki Kaisha Toshiba Stacked semiconductor package and manufacturing method thereof
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9922914B2 (en) 2012-05-10 2018-03-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9922913B2 (en) 2012-05-10 2018-03-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9000590B2 (en) 2012-05-10 2015-04-07 Utac Thai Limited Protruding terminals with internal routing interconnections semiconductor device
US9972563B2 (en) 2012-05-10 2018-05-15 UTAC Headquarters Pte. Ltd. Plated terminals with routing interconnections semiconductor device
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US9397031B2 (en) 2012-06-11 2016-07-19 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10096490B2 (en) 2015-11-10 2018-10-09 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10163658B2 (en) 2015-11-10 2018-12-25 UTAC Headquarters PTE, LTD. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10032645B1 (en) 2015-11-10 2018-07-24 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9922843B1 (en) 2015-11-10 2018-03-20 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9805955B1 (en) 2015-11-10 2017-10-31 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10325782B2 (en) 2015-11-10 2019-06-18 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10734247B2 (en) 2015-11-10 2020-08-04 Utac Headquarters PTE. Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same

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