US6706624B1 - Method for making multichip module substrates by encapsulating electrical conductors - Google Patents

Method for making multichip module substrates by encapsulating electrical conductors Download PDF

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US6706624B1
US6706624B1 US10/100,658 US10065802A US6706624B1 US 6706624 B1 US6706624 B1 US 6706624B1 US 10065802 A US10065802 A US 10065802A US 6706624 B1 US6706624 B1 US 6706624B1
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chips
apertures
dielectric
dielectric sheet
sheet
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Christopher James Kapusta
Thomas Bert Gorczyca
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General Electric Co
Lockheed Martin Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to fabrication of high density interconnect (HDI) modules, and more particularly to methods for making multichip modules by using a substrate made by encapsulating electrical conductors.
  • HDI high density interconnect
  • a dielectric substrate such as alumina has a planar surface and one or more wells or depressions. Each well or depression extends below the planar surface by the dimension of a component which is to become part of the HDI assemblage.
  • the component is typically an integrated circuit, having its electrical connections or contacts on an upper surface.
  • Each component is mounted in a well dimensioned to accommodate the component with its contacts in substantially the same plane as the planar surface of the substrate.
  • the components are typically held in place in their wells or depressions by an epoxy adhesive.
  • a layer of dielectric material such as Kapton polyimide film, manufactured by DuPont of Wilmington, Del., is laminated to the devices using ULTEM polyetherimide thermoplastic adhesive, manufactured by General Electric Plastic, Pittsfield, Mass., which is then heat-cured at about 260° to 300° C. in order to set the adhesive.
  • the polyetherimide adhesive is advantageous in that it bonds effectively to a number of metallurgies, and can be applied in a layer as thin as 12 micrometers ( ⁇ m) without formation of voids. Further, it is a thermoplastic material, so that later removal of the polyimide film from the components is possible for purposes of repair by heating the structure to the glass transition temperature of the polyetherimide while putting tension on the polyimide film.
  • HDI modules Another known method for making HDI modules includes applying the chips, electrode-side-down, onto an adhesive-faced dielectric layer.
  • the chips are then encapsulated in a rigid material, which in one embodiment is Plaskon, an epoxy material, to form a rigid molded-chip-plus-dielectric-sheet piece.
  • the electrical interconnections are made by means of laser-drilled vias through the dielectric sheet, followed by patterned deposition of electrically conductive metallization.
  • a method for generating a multi-chip module.
  • the method comprises the steps of procuring a dielectric sheet defining a surface, and tensioning the dielectric sheet to provide a measure of rigidity to the surface.
  • One or more electrical conductors is applied to the surface of the dielectric sheet in a predetermined pattern.
  • the electrical conductors have a predetermined thickness. In one embodiment of the invention, the thickness is 40 thousandths of an inch (0.040′′), and the surface of the dielectric sheet is coated with adhesive to retain the conductors.
  • Encapsulating material is applied to the surface of the dielectric sheet in a thickness sufficient to encapsulate the electrical conductors, to thereby generate a rigid substrate element.
  • Apertures which may be through apertures, are fabricated, formed or defined in the rigid substrate element at predetermined locations at which semiconductor or solid-state chips are to be placed in or on the multi-chip module.
  • the semiconductor chips are placed on a second dielectric substrate at locations registered with the apertures or through apertures, with electrical interconnects of the chips facing in a particular direction.
  • the second dielectric sheet has adhesive on one of its surfaces, and that side of the semiconductor or solid-state chips having electrical connection pads or electrodes of the semiconductor or solid-state chips are placed on the adhesive of the second sheet.
  • the rigid substrate element is affixed to the second dielectric sheet with the semiconductor or solid-state chips extending into or through the apertures.
  • a flexible multilayer dielectric interconnection sheet carrying interconnection conductor patterns is applied over at least the electrical connection pads or electrodes of some of the semiconductor or solid-state chips, for making connections between at least some of the interconnection conductor patterns of the interconnection sheet and some of the electrical connection pads.
  • the connections are made with the aid of plated-through vias.
  • a layer of encapsulant material is removed or shaved from at least one surface of the rigid substrate element before the step of affixing the rigid substrate element to the second dielectric sheet.
  • the step of applying to the surface of the dielectric sheet, in a predetermined pattern, one or more electrical conductors having a predetermined thickness includes the step of applying adhesive to the surface of the dielectric sheet, and applying the one or more electrical conductors to the adhesive.
  • an electrically or thermally conductive plate is affixed to the rigid substrate element on that side of the multichip module remote from the flexible multilayer dielectric interconnection sheet.
  • FIG. 1 a is a simplified perspective or isometric view of a tensioned dielectric sheet onto which conductive slug material has been affixed
  • FIG. 1 b is a cross-section of the structure of FIG. 1 a looking in the direction 1 b — 1 b;
  • FIG. 2 is a simplified cross-section of the structure of FIGS. 1 a and 1 b after encapsulation;
  • FIG. 3 is a simplified cross-section of the structure of FIG. 2 after removal of excess encapsulation and dielectric sheet;
  • FIG. 4 a is a simplified cross-sectional view
  • FIG. 4 b a simplified perspective or isometric view, of the structure of FIG. 3 after the defining of apertures for placement of chips;
  • FIG. 5 is a simplified perspective or isometric view of another dielectric sheet with semiconductor or solid-state chips mounted thereon in a pattern registered with the apertures of the structure of FIGS. 4 a and 4 b;
  • FIG. 6 is a simplified cross-sectional view of the structure of FIGS. 4 a and 4 b juxtaposed with that of FIG. 5;
  • FIG. 7 is a simplified cross-sectional view of the structure of FIG. 6, with the addition of through vias and circuit metallizations or depositions;
  • FIG. 8 is a simplified cross-sectional view of a completed multi-chip module according to an aspect of the invention, including a ground/thermal coupling plate.
  • a tensioned dielectric sheet 10 defines an upper surface 10 us .
  • the tensioning may be applied by way of a frame, as known in the art, to produce a radial outward force indicated by arrows f.
  • the upper surface 10 us may be coated with adhesive.
  • a layer of electrically conductive material 12 is affixed to the upper surface 10 us of dielectric sheet 10 , as for example by application of a layer 14 of adhesive to the upper surface 10 us .
  • Conductive layer 12 may have any thickness T, but in one embodiment of the invention, has a thickness of 0.040 inch. Such a thickness of material may possibly be better fabricated by stamping rather than by deposition, but any method will do, including machining from a block of conductive metal.
  • the conductive pattern is in the form of an open rectangle or surrounding wall. Such a pattern can be useful in the context of electrically shielding components lying within the enclosed portion. Such a shape may also be useful for grounding electrical circuits, especially if the electrically conductive piece 12 is itself connected to an external ground.
  • the structure of FIG. 1 b has been covered with a layer of encapsulating or fill material 210 .
  • the encapsulating material is the abovementioned Plaskon material. Once the encapsulating material is hardened, the layer becomes rigid to thereby define a rigid substrate element 200 , although the thickness of the element is such that it may be somewhat flexible overall. As illustrated in FIG. 2, the encapsulating material 210 fills the region between the exposed portions of the electrically conductive material 12 . As illustrated in FIG. 2, the layer 210 of encapsulant material may be thick enough to extend over the electrically conductive portions 12 .
  • FIG. 3 is a simplified cross-sectional view of the structure of FIG. 2 after the step of grinding or lapping both upper and lower surfaces of the structure to thereby expose the electrically conductive portions 12 at both surfaces.
  • FIGS. 4 a and 4 b illustrate the result of forming apertures 410 a and 410 b within the region which is electrically shielded by the presence of electrically conductive slug 12 .
  • the apertures are dimensioned to accommodate the various semiconductor or solid-state chips (chips) which are intended for mounting therein.
  • FIG. 5 illustrates a structure 500 including a sheet 510 of dielectric material on which a plurality of semiconductor or solid-state chips, two of which are designated 512 a and 512 b , are mounted.
  • the mounting may be accomplished by applying adhesive to either the electrical connection sides of the chips or to the dielectric sheet 510 , and bringing the chips into contact with the dielectric sheet 510 .
  • the locations of the chips are selected to be registered with each other and with the apertures 410 a and 410 b in structure 400 of FIGS. 4 a and 4 b.
  • FIG. 6 is a cross-sectional view of the combined structures 400 of FIG. 4 with 500 of FIG. 5 .
  • the semiconductor or solid-state chip 512 a lies within aperture 410 a
  • chip 512 b lies within aperture 410 b .
  • the resulting structure is designated 600 .
  • FIG. 7 illustrates the structure 600 of FIG. 6, turned over for convenience in understanding, with layer 510 of dielectric material lying above the remaining structure.
  • through vias 712 a , 712 b , and 712 c are made in the conventional manner through dielectric material 510 at the locations of the conductive slugs 12 and at the location of a contact pad 512 ap of semiconductor or solid-state chip 512 a .
  • Metallizations 714 a and 714 b overlie the locations of electrically conductive slugs 12
  • metallization 714 c overlies one of the electrical contacts or pads of semiconductor or solid-state chip 512 a.
  • FIG. 8 is a cross-sectional view of a structure 800 built up from structure 700 of FIG. 7 .
  • Structure 800 includes a further heat-sink layer 810 affixed to the bottom of structure 700 , and thermally coupled at least to the lower surfaces of semiconductor or solid-state chips 512 a and 512 b , for aiding in carrying away heat therefrom.
  • the heat sink layer 810 can be electrically conductive, and be in galvanic contact with the electrically conductive slugs 12 .
  • a further dielectric interconnect layer 812 is affixed to the upper surface of layer 510 . Interconnect layer 812 includes further through vias and metallizations, for making other connections.
  • dielectric interconnect layer 812 has through vias and metallizations 814 a , 814 b , and 814 c made therethrough at locations of an intermediate-level connection pad 816 , and at the locations of contact pads 512 bp and 512 ap 2 .
  • the pattern of the conductor in the described example is a simple open rectangle, any planar shape, however complex, may be used. There is no need for the various portions of the conductor to be contiguous (that is to say, in direct or galvanic electrical contact).
  • the pattern may also be exposed, in some or all areas, to the edge of the molded substrate.
  • other components such as resistors, capacitors, or other passive or active components which can be completely encapsulated without detrimental effect, may be added to the original dielectric sheet and encapsulated into the structure together with the metal pattern. Such items or components might be thinner that the final substrate thickness so as not to interfere with grinding, if used.
  • one aperture could accommodate more than one component . . . that is, the structure formed may have only one aperture which fits over a plurality, or all the active and passive components applied to the second dielectric sheet. Open space left in the aperture is optionally filled with a suitable material after placement of the structure over the components. Removal of the dielectric sheet used to form the substrate or removal of excess molding material, if present, is optional. A metal interconnect may be optionally placed onto the substrate to form an interconnect structure between the metal pattern and added components and provide pads for further interconnect integration with the second dielectric sheet onto which it is placed. After placement of the structure over the semiconductor chips and components on flex, the remaining open space within the apertures formed to accommodate the components may be optionally filled with a suitable material.
  • a method for generating a multi-chip module ( 800 ).
  • the method comprises the steps of procuring a dielectric sheet ( 10 ) defining a surface ( 10 us ) and tensioning (f) the dielectric sheet, as by use of a frame, to provide a measure of rigidity to the surface ( 10 us ).
  • One or more electrical conductors ( 12 ) is applied to the surface ( 10 us ) of the dielectric sheet ( 10 ) in a predetermined pattern.
  • the electrical conductors ( 12 ) have a predetermined thickness. In one embodiment of the invention, the thickness is 40 thousandths of an inch, and the surface of the dielectric sheet is coated with adhesive ( 14 ) to retain the conductors ( 12 ).
  • Encapsulating material ( 210 ) is applied to the surface of the dielectric sheet in a thickness sufficient to encapsulate the electrical conductors ( 12 ), to thereby generate a rigid substrate element ( 200 ).
  • Apertures which may be through apertures ( 410 a , 410 b ), are fabricated, formed or defined in the rigid substrate element 200 at predetermined locations at which semiconductor or solid-state chips ( 512 a , 512 b ) are to be placed in or on the multi-chip module ( 800 ).
  • the semiconductor or solid-state chips ( 410 a , 410 b ) are placed on a second dielectric sheet or substrate ( 510 ) at locations registered with the apertures or through apertures ( 410 a , 410 b ), with electrical pads, electrodes, or interconnects ( 512 ap , 512 ap 2 , 512 bp ) of the chips ( 410 a , 410 b ) facing in a particular direction.
  • the second dielectric sheet ( 510 ) has adhesive ( 510 a ) on one of its surfaces, and that side of the semiconductor or solid-state chips ( 410 a , 410 b ) having electrical connection pads or electrodes ( 512 ap , 512 ap 2 , 512 bp ) of the semiconductor or solid-state chips ( 410 a , 410 b ) are placed on the adhesive ( 510 a ) of the second sheet. ( 510 ).
  • the rigid substrate element with apertures ( 400 ) is affixed to the second dielectric sheet ( 510 ) with the semiconductor or solid-state chips ( 410 a , 410 b ) extending into or through the apertures ( 410 a , 410 b ).
  • a flexible multilayer dielectric interconnection sheet carrying interconnection conductor patterns ( 510 , 812 ) is formed on, andor applied over, at least the electrical connection pads or electrodes ( 512 ap , 512 ap 2 , 512 bp ) of some of the semiconductor or solid-state chips ( 410 a , 410 b ), for making connections between at least some of the interconnection conductor patterns ( 714 a , 714 b , 714 c , 814 a , 814 b , 814 c ) of the interconnection sheet ( 510 , 812 ) and some of the electrical connection pads ( 512 ap , 512 ap 2 , 512 bp ).
  • the connections are made with the aid of plated-through vias ( 712 a , 712 b , 712 c , 814 a , 814 b , 814 c ).
  • a layer of encapsulant material is removed, shaved or ground from at least one surface of the rigid substrate element ( 200 ) before the step of affixing the rigid substrate element to the second dielectric sheet.
  • the step of applying to the surface ( 10 us ) of the dielectric sheet 910 ), in a predetermined pattern, one or more electrical conductors ( 12 ) having a predetermined thickness includes the step of applying adhesive ( 14 ) to the surface ( 10 us ) of the dielectric sheet ( 10 ), and applying the one or more electrical conductors ( 12 ) to the adhesive ( 14 ).
  • an electrically conductive plate ( 810 ) is affixed to the rigid substrate element ( 300 ) on that side of the multichip module ( 800 ) remote from the flexible multilayer dielectric interconnection sheet ( 510 , 812 ).

Abstract

A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet at locations at which the chips are to be located. The chips are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

Description

CROSS REFERENCE TO RELATED APPLICATION
This application relates to and claims the benefit of the earlier filing date under 35 U.S.C. 119, of U.S. Provisional Patent Application, Serial Number 5 60/339,969 entitled “Method for Making Multichip Module Substrates by Encapsulating Electrical Conductors,” filed on Oct. 31, 2001.
FIELD OF THE INVENTION
This invention relates to fabrication of high density interconnect (HDI) modules, and more particularly to methods for making multichip modules by using a substrate made by encapsulating electrical conductors.
BACKGROUND OF THE INVENTION
High density interconnect assemblages such as those described in U.S. Pat. No. 4,783,695, issued Nov. 8, 1988 in the name of Eichelberger et al., and in numerous other patents, are finding increased usage. In one form of HDI assemblage, a dielectric substrate such as alumina has a planar surface and one or more wells or depressions. Each well or depression extends below the planar surface by the dimension of a component which is to become part of the HDI assemblage. The component is typically an integrated circuit, having its electrical connections or contacts on an upper surface. Each component is mounted in a well dimensioned to accommodate the component with its contacts in substantially the same plane as the planar surface of the substrate. The components are typically held in place in their wells or depressions by an epoxy adhesive. A layer of dielectric material such as Kapton polyimide film, manufactured by DuPont of Wilmington, Del., is laminated to the devices using ULTEM polyetherimide thermoplastic adhesive, manufactured by General Electric Plastic, Pittsfield, Mass., which is then heat-cured at about 260° to 300° C. in order to set the adhesive.
The polyetherimide adhesive is advantageous in that it bonds effectively to a number of metallurgies, and can be applied in a layer as thin as 12 micrometers (μm) without formation of voids. Further, it is a thermoplastic material, so that later removal of the polyimide film from the components is possible for purposes of repair by heating the structure to the glass transition temperature of the polyetherimide while putting tension on the polyimide film.
Another known method for making HDI modules includes applying the chips, electrode-side-down, onto an adhesive-faced dielectric layer. The chips are then encapsulated in a rigid material, which in one embodiment is Plaskon, an epoxy material, to form a rigid molded-chip-plus-dielectric-sheet piece. The electrical interconnections are made by means of laser-drilled vias through the dielectric sheet, followed by patterned deposition of electrically conductive metallization.
SUMMARY OF THE INVENTION
A method according to one aspect of the invention is for generating a multi-chip module. The method comprises the steps of procuring a dielectric sheet defining a surface, and tensioning the dielectric sheet to provide a measure of rigidity to the surface. One or more electrical conductors is applied to the surface of the dielectric sheet in a predetermined pattern. The electrical conductors have a predetermined thickness. In one embodiment of the invention, the thickness is 40 thousandths of an inch (0.040″), and the surface of the dielectric sheet is coated with adhesive to retain the conductors. Encapsulating material is applied to the surface of the dielectric sheet in a thickness sufficient to encapsulate the electrical conductors, to thereby generate a rigid substrate element. Apertures, which may be through apertures, are fabricated, formed or defined in the rigid substrate element at predetermined locations at which semiconductor or solid-state chips are to be placed in or on the multi-chip module. The semiconductor chips are placed on a second dielectric substrate at locations registered with the apertures or through apertures, with electrical interconnects of the chips facing in a particular direction. In a particular embodiment of the invention, the second dielectric sheet has adhesive on one of its surfaces, and that side of the semiconductor or solid-state chips having electrical connection pads or electrodes of the semiconductor or solid-state chips are placed on the adhesive of the second sheet. The rigid substrate element is affixed to the second dielectric sheet with the semiconductor or solid-state chips extending into or through the apertures. A flexible multilayer dielectric interconnection sheet carrying interconnection conductor patterns is applied over at least the electrical connection pads or electrodes of some of the semiconductor or solid-state chips, for making connections between at least some of the interconnection conductor patterns of the interconnection sheet and some of the electrical connection pads. In a particular embodiment of the invention, the connections are made with the aid of plated-through vias.
In one variant of the method, a layer of encapsulant material is removed or shaved from at least one surface of the rigid substrate element before the step of affixing the rigid substrate element to the second dielectric sheet. In another variant, the step of applying to the surface of the dielectric sheet, in a predetermined pattern, one or more electrical conductors having a predetermined thickness includes the step of applying adhesive to the surface of the dielectric sheet, and applying the one or more electrical conductors to the adhesive. In another mode of the method of the invention, an electrically or thermally conductive plate is affixed to the rigid substrate element on that side of the multichip module remote from the flexible multilayer dielectric interconnection sheet.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1a is a simplified perspective or isometric view of a tensioned dielectric sheet onto which conductive slug material has been affixed, and FIG. 1b is a cross-section of the structure of FIG. 1a looking in the direction 1 b—1 b;
FIG. 2 is a simplified cross-section of the structure of FIGS. 1a and 1 b after encapsulation;
FIG. 3 is a simplified cross-section of the structure of FIG. 2 after removal of excess encapsulation and dielectric sheet;
FIG. 4a is a simplified cross-sectional view, and FIG. 4b a simplified perspective or isometric view, of the structure of FIG. 3 after the defining of apertures for placement of chips;
FIG. 5 is a simplified perspective or isometric view of another dielectric sheet with semiconductor or solid-state chips mounted thereon in a pattern registered with the apertures of the structure of FIGS. 4a and 4 b;
FIG. 6 is a simplified cross-sectional view of the structure of FIGS. 4a and 4 b juxtaposed with that of FIG. 5;
FIG. 7 is a simplified cross-sectional view of the structure of FIG. 6, with the addition of through vias and circuit metallizations or depositions; and
FIG. 8 is a simplified cross-sectional view of a completed multi-chip module according to an aspect of the invention, including a ground/thermal coupling plate.
DESCRIPTION OF THE INVENTION
In FIGS. 1a and 1 b, a tensioned dielectric sheet 10 defines an upper surface 10 us. The tensioning may be applied by way of a frame, as known in the art, to produce a radial outward force indicated by arrows f. The upper surface 10 us may be coated with adhesive. A layer of electrically conductive material 12 is affixed to the upper surface 10 us of dielectric sheet 10, as for example by application of a layer 14 of adhesive to the upper surface 10 us. Conductive layer 12 may have any thickness T, but in one embodiment of the invention, has a thickness of 0.040 inch. Such a thickness of material may possibly be better fabricated by stamping rather than by deposition, but any method will do, including machining from a block of conductive metal. As illustrated, the conductive pattern is in the form of an open rectangle or surrounding wall. Such a pattern can be useful in the context of electrically shielding components lying within the enclosed portion. Such a shape may also be useful for grounding electrical circuits, especially if the electrically conductive piece 12 is itself connected to an external ground.
In FIG. 2, the structure of FIG. 1b has been covered with a layer of encapsulating or fill material 210. In one embodiment, the encapsulating material is the abovementioned Plaskon material. Once the encapsulating material is hardened, the layer becomes rigid to thereby define a rigid substrate element 200, although the thickness of the element is such that it may be somewhat flexible overall. As illustrated in FIG. 2, the encapsulating material 210 fills the region between the exposed portions of the electrically conductive material 12. As illustrated in FIG. 2, the layer 210 of encapsulant material may be thick enough to extend over the electrically conductive portions 12.
FIG. 3 is a simplified cross-sectional view of the structure of FIG. 2 after the step of grinding or lapping both upper and lower surfaces of the structure to thereby expose the electrically conductive portions 12 at both surfaces.
FIGS. 4a and 4 b illustrate the result of forming apertures 410 a and 410 b within the region which is electrically shielded by the presence of electrically conductive slug 12. The apertures are dimensioned to accommodate the various semiconductor or solid-state chips (chips) which are intended for mounting therein.
FIG. 5 illustrates a structure 500 including a sheet 510 of dielectric material on which a plurality of semiconductor or solid-state chips, two of which are designated 512 a and 512 b, are mounted. The mounting may be accomplished by applying adhesive to either the electrical connection sides of the chips or to the dielectric sheet 510, and bringing the chips into contact with the dielectric sheet 510. The locations of the chips are selected to be registered with each other and with the apertures 410 a and 410 b in structure 400 of FIGS. 4a and 4 b.
FIG. 6 is a cross-sectional view of the combined structures 400 of FIG. 4 with 500 of FIG. 5. In FIG. 6, the semiconductor or solid-state chip 512 a lies within aperture 410 a, and chip 512 b lies within aperture 410 b. The resulting structure is designated 600.
FIG. 7 illustrates the structure 600 of FIG. 6, turned over for convenience in understanding, with layer 510 of dielectric material lying above the remaining structure. As illustrated in FIG. 7, through vias 712 a, 712 b, and 712 c are made in the conventional manner through dielectric material 510 at the locations of the conductive slugs 12 and at the location of a contact pad 512 ap of semiconductor or solid-state chip 512 a. Metallizations 714 a and 714 b overlie the locations of electrically conductive slugs 12, while metallization 714 c overlies one of the electrical contacts or pads of semiconductor or solid-state chip 512 a.
FIG. 8 is a cross-sectional view of a structure 800 built up from structure 700 of FIG. 7. Structure 800 includes a further heat-sink layer 810 affixed to the bottom of structure 700, and thermally coupled at least to the lower surfaces of semiconductor or solid- state chips 512 a and 512 b, for aiding in carrying away heat therefrom. Alternatively, or in addition, the heat sink layer 810 can be electrically conductive, and be in galvanic contact with the electrically conductive slugs 12. In addition, a further dielectric interconnect layer 812 is affixed to the upper surface of layer 510. Interconnect layer 812 includes further through vias and metallizations, for making other connections. More particularly, dielectric interconnect layer 812 has through vias and metallizations 814 a, 814 b, and 814 c made therethrough at locations of an intermediate-level connection pad 816, and at the locations of contact pads 512 bp and 512 ap 2.
Other embodiments of the invention will be apparent to those skilled in the art. For example, while the pattern of the conductor in the described example is a simple open rectangle, any planar shape, however complex, may be used. There is no need for the various portions of the conductor to be contiguous (that is to say, in direct or galvanic electrical contact). The pattern may also be exposed, in some or all areas, to the edge of the molded substrate. In addition to the pattern, other components, such as resistors, capacitors, or other passive or active components which can be completely encapsulated without detrimental effect, may be added to the original dielectric sheet and encapsulated into the structure together with the metal pattern. Such items or components might be thinner that the final substrate thickness so as not to interfere with grinding, if used. It would probably be easier to have the passive parts added during the substrate structure formation, thus eliminating the need to open up apertures for them later; on the other hand, one aperture could accommodate more than one component . . . that is, the structure formed may have only one aperture which fits over a plurality, or all the active and passive components applied to the second dielectric sheet. Open space left in the aperture is optionally filled with a suitable material after placement of the structure over the components. Removal of the dielectric sheet used to form the substrate or removal of excess molding material, if present, is optional. A metal interconnect may be optionally placed onto the substrate to form an interconnect structure between the metal pattern and added components and provide pads for further interconnect integration with the second dielectric sheet onto which it is placed. After placement of the structure over the semiconductor chips and components on flex, the remaining open space within the apertures formed to accommodate the components may be optionally filled with a suitable material.
Thus, a method according to an aspect of the invention is for generating a multi-chip module (800). The method comprises the steps of procuring a dielectric sheet (10) defining a surface (10 us) and tensioning (f) the dielectric sheet, as by use of a frame, to provide a measure of rigidity to the surface (10 us). One or more electrical conductors (12) is applied to the surface (10 us) of the dielectric sheet (10) in a predetermined pattern. The electrical conductors (12) have a predetermined thickness. In one embodiment of the invention, the thickness is 40 thousandths of an inch, and the surface of the dielectric sheet is coated with adhesive (14) to retain the conductors (12). Encapsulating material (210) is applied to the surface of the dielectric sheet in a thickness sufficient to encapsulate the electrical conductors (12), to thereby generate a rigid substrate element (200). Apertures, which may be through apertures (410 a, 410 b), are fabricated, formed or defined in the rigid substrate element 200 at predetermined locations at which semiconductor or solid-state chips (512 a, 512 b) are to be placed in or on the multi-chip module (800). The semiconductor or solid-state chips (410 a, 410 b) are placed on a second dielectric sheet or substrate (510) at locations registered with the apertures or through apertures (410 a, 410 b), with electrical pads, electrodes, or interconnects (512 ap, 512 ap 2, 512 bp) of the chips (410 a, 410 b) facing in a particular direction. In a particular embodiment of the invention, the second dielectric sheet (510) has adhesive (510 a) on one of its surfaces, and that side of the semiconductor or solid-state chips (410 a, 410 b) having electrical connection pads or electrodes (512 ap, 512 ap 2, 512 bp) of the semiconductor or solid-state chips (410 a, 410 b) are placed on the adhesive (510 a) of the second sheet. (510). The rigid substrate element with apertures (400) is affixed to the second dielectric sheet (510) with the semiconductor or solid-state chips (410 a, 410 b) extending into or through the apertures (410 a, 410 b). A flexible multilayer dielectric interconnection sheet carrying interconnection conductor patterns (510, 812) is formed on, andor applied over, at least the electrical connection pads or electrodes (512 ap, 512 ap 2, 512 bp) of some of the semiconductor or solid-state chips (410 a, 410 b), for making connections between at least some of the interconnection conductor patterns (714 a, 714 b, 714 c, 814 a, 814 b, 814 c) of the interconnection sheet (510, 812) and some of the electrical connection pads (512 ap, 512 ap 2, 512 bp). In a particular embodiment of the invention, the connections are made with the aid of plated-through vias (712 a, 712 b, 712 c, 814 a, 814 b, 814 c).
In one variant of the method, a layer of encapsulant material is removed, shaved or ground from at least one surface of the rigid substrate element (200) before the step of affixing the rigid substrate element to the second dielectric sheet. In another variant, the step of applying to the surface (10 us) of the dielectric sheet 910), in a predetermined pattern, one or more electrical conductors (12) having a predetermined thickness includes the step of applying adhesive (14) to the surface (10 us) of the dielectric sheet (10), and applying the one or more electrical conductors (12) to the adhesive (14). In another mode of the method of the invention, an electrically conductive plate (810) is affixed to the rigid substrate element (300) on that side of the multichip module (800) remote from the flexible multilayer dielectric interconnection sheet (510, 812).

Claims (6)

What is claimed is:
1. A method for generating a multi-chip module, said method comprising the steps of:
procuring a dielectric sheet defining a surface;
tensioning said dielectric sheet to provide a measure of rigidity to said surface thereof;
applying to said surface of said dielectric sheet, in a predetermined pattern, one or more electrical conductors having a predetermined thickness;
applying encapsulating material to said surface of said dielectric sheet in a thickness sufficient to encapsulate said electrical conductors to thereby generate a rigid substrate element;
fabricating apertures in said rigid substrate element at predetermined locations at which chips are to be placed on said multi-chip module;
placing chips on a second dielectric substrate at locations registered with said apertures, with electrical interconnects of said chips facing in a particular direction;
affixing said rigid substrate element to said second dielectric sheet with said chips extending into said apertures; and
applying a flexible multilayer dielectric interconnection sheet over at least said electrical interconnects of said chips, and making connections between at least some of the interconnects of said interconnection layer and some of said electrical interconnects of said chips.
2. A method according to claim 1, further including the step of removing encapsulating material from at least one surface of said rigid substrate element before said step of affixing said rigid substrate element to said second dielectric sheet.
3. A method according to claim 1, wherein said step of applying to said surface of said dielectric sheet, in a predetermined pattern, one or more electrical conductors having a predetermined thickness includes the step of applying adhesive to said surface of said dielectric sheet and applying said one or more electrical conductors to said adhesive.
4. A method according to claim 1, further comprising the step of affixing an electrically conductive plate to that side of said rigid substrate element remote from said flexible multilayer dielectric interconnection sheet, with said plate in at least one of (a) electrical contact with one of said electrical conductors and (b) in thermal contact with at least one of said semiconductor or solid-state chips.
5. A method according to claim 1, wherein said step of forming apertures comprises the step of forming through apertures.
6. A method according to claim 1, wherein said step of fabricating apertures in said rigid substrate element is additionally performed at predetermined locations at which passive components are to be placed on said multi-chip module; and comprising the additional step of
placing at least one passive component on said second dielectric substrate at a location registered with, or at least within, one of said apertures.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113250A1 (en) * 2002-12-12 2004-06-17 Khandros Igor Y. Integrated circuit assembly
US20040229400A1 (en) * 2002-08-27 2004-11-18 Chua Swee Kwang Multichip wafer level system packages and methods of forming same
US20120119390A1 (en) * 2008-05-28 2012-05-17 Navas Khan Oratti Kalandar Semiconductor structure and a method of manufacturing a semiconductor structure
US20140376201A1 (en) * 2013-06-19 2014-12-25 Keithley Instruments, Inc. Guarded printed circuit board islands
US9089052B2 (en) 2013-06-27 2015-07-21 International Business Machines Corporation Multichip module with stiffening frame and associated covers

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5048179A (en) * 1986-05-23 1991-09-17 Ricoh Company, Ltd. IC chip mounting method
US5049980A (en) * 1987-04-15 1991-09-17 Kabushiki Kaisha Toshiba Electronic circuit device and method of manufacturing same
US5073814A (en) * 1990-07-02 1991-12-17 General Electric Company Multi-sublayer dielectric layers
EP0488574A2 (en) * 1990-11-30 1992-06-03 AT&T Corp. Personal data card construction
US5144747A (en) * 1991-03-27 1992-09-08 Integrated System Assemblies Corporation Apparatus and method for positioning an integrated circuit chip within a multichip module
US5338975A (en) * 1990-07-02 1994-08-16 General Electric Company High density interconnect structure including a spacer structure and a gap
US5359496A (en) * 1989-12-21 1994-10-25 General Electric Company Hermetic high density interconnected electronic system
US5373627A (en) * 1993-11-23 1994-12-20 Grebe; Kurt R. Method of forming multi-chip module with high density interconnections
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
US5739585A (en) * 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US5757072A (en) * 1994-12-19 1998-05-26 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US5808878A (en) * 1995-03-16 1998-09-15 Kabushiki Kaisha Toshiba Circuit substrate shielding device
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048179A (en) * 1986-05-23 1991-09-17 Ricoh Company, Ltd. IC chip mounting method
US4783695A (en) 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5049980A (en) * 1987-04-15 1991-09-17 Kabushiki Kaisha Toshiba Electronic circuit device and method of manufacturing same
US5359496A (en) * 1989-12-21 1994-10-25 General Electric Company Hermetic high density interconnected electronic system
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
US5073814A (en) * 1990-07-02 1991-12-17 General Electric Company Multi-sublayer dielectric layers
US5338975A (en) * 1990-07-02 1994-08-16 General Electric Company High density interconnect structure including a spacer structure and a gap
EP0488574A2 (en) * 1990-11-30 1992-06-03 AT&T Corp. Personal data card construction
US5144747A (en) * 1991-03-27 1992-09-08 Integrated System Assemblies Corporation Apparatus and method for positioning an integrated circuit chip within a multichip module
US6274391B1 (en) * 1992-10-26 2001-08-14 Texas Instruments Incorporated HDI land grid array packaged device having electrical and optical interconnects
US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5373627A (en) * 1993-11-23 1994-12-20 Grebe; Kurt R. Method of forming multi-chip module with high density interconnections
US5757072A (en) * 1994-12-19 1998-05-26 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US5808878A (en) * 1995-03-16 1998-09-15 Kabushiki Kaisha Toshiba Circuit substrate shielding device
US5739585A (en) * 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040229400A1 (en) * 2002-08-27 2004-11-18 Chua Swee Kwang Multichip wafer level system packages and methods of forming same
US20050116337A1 (en) * 2002-08-27 2005-06-02 Swee Kwang Chua Method of making multichip wafer level packages and computing systems incorporating same
US20040113250A1 (en) * 2002-12-12 2004-06-17 Khandros Igor Y. Integrated circuit assembly
US7550842B2 (en) * 2002-12-12 2009-06-23 Formfactor, Inc. Integrated circuit assembly
US20120119390A1 (en) * 2008-05-28 2012-05-17 Navas Khan Oratti Kalandar Semiconductor structure and a method of manufacturing a semiconductor structure
US8466550B2 (en) * 2008-05-28 2013-06-18 Agency For Science, Technology And Research Semiconductor structure and a method of manufacturing a semiconductor structure
US20140376201A1 (en) * 2013-06-19 2014-12-25 Keithley Instruments, Inc. Guarded printed circuit board islands
US9326369B2 (en) * 2013-06-19 2016-04-26 Keithley Instruments, Inc. Guarded printed circuit board islands
US9089052B2 (en) 2013-06-27 2015-07-21 International Business Machines Corporation Multichip module with stiffening frame and associated covers
US9089051B2 (en) 2013-06-27 2015-07-21 International Business Machines Corporation Multichip module with stiffening frame and associated covers

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