US6845495B2 - Multidirectional router - Google Patents
Multidirectional router Download PDFInfo
- Publication number
- US6845495B2 US6845495B2 US10/027,642 US2764201A US6845495B2 US 6845495 B2 US6845495 B2 US 6845495B2 US 2764201 A US2764201 A US 2764201A US 6845495 B2 US6845495 B2 US 6845495B2
- Authority
- US
- United States
- Prior art keywords
- routing
- net
- pins
- tile
- nets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
Definitions
- the present invention generally relates to the field of integrated circuit design, and particularly to a system and method of providing multidirectional routing.
- An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate.
- the IC may include a large number of cells and require complex connections between the cells.
- a cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function.
- Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires.
- the wires connecting the pins of the IC are also formed on the surface of the chip.
- a net is a set of two or more pins that must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins that must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected.
- a netlist is a list of nets for a chip.
- Microelectronic integrated circuits include a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer.
- the design of an integrated circuit transforms a circuit description into a geometric description, which is known as a layout.
- a layout includes a set of planar geometric shapes in several layers.
- Routing between the components of the chip is typically done utilizing Manhattan routing, in which X and Y Cartesian coordinates are used when laying out lines on silicon.
- Manhattan routing in which X and Y Cartesian coordinates are used when laying out lines on silicon.
- routing method may limit the chip density, and thus the speed of the chip.
- the present invention is directed to a system and method for providing multidirectional routing.
- the present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.
- a method for routing a multi-layered integrated circuit wherein arbitrary routing directions may be supported on an arbitrary number of layers of the integrated circuit includes receiving parameters for an integrated circuit having n layers, wherein n is at least two.
- a routing graph is constructed for layers of the integrated circuit, the levels partitioned into tiles, wherein at least one edge is provided to join a first tile and a second tile in the routing graph, the tiles positioned generally corresponding to a layer grid line of the level. Routing is then performed based on the routing graph.
- a method for routing a multi-layered integrated circuit includes receiving parameters for an integrated circuit having n layers, wherein n is at least two.
- a routing graph is constructed for a level k of the n layers of the integrated circuit.
- the k level is partitioned into k-level tiles, wherein at least one edge is provided to join a first tile and a second tile in the k level routing graph.
- Capacities of the at least one edge joining the first tile and the second tile are calculated, the edge at least one of regular and normal. Occupancies are added based on previous level net routing (k+1) and penalties of edges calculated. Nets are then routed based on the routing graph, calculated capacities and added occupancies.
- FIG. 1 is a flow diagram of an exemplary method of the present invention wherein a procedure for routing an integrated circuit having multiple layers is shown suitable utilizing any arbitrary angle;
- FIG. 2 is a flow diagram of an exemplary method of the present invention wherein a procedure for routing an integrated circuit having multiple layers is shown suitable utilizing any arbitrary angle, the procedure routing nets in both a net routing area and open nets outside the net routing area;
- FIG. 3A is an illustration of an embodiment of the present invention wherein a regular edge of previous level routing of a net is shown;
- FIGS. 4A and 4B are a depictions of an embodiment of the present invention wherein normal edges connecting vertices from neighbor layers are shown.
- FIG. 5 is an illustration of an embodiment of the present invention wherein a net including four pins, A, B, C and D and grid line directions of 4 layers of the chip are presented by lines OX, OY, OZ and OU as utilized to define a bounding box is shown.
- k>zero 110 the constructing 104 , adding/calculating 106 , and routing 108 operational steps are repeated after one is subtracted from k 112 . If k is equal to zero 114 , the adding/calculating 106 , and routing 110 operational steps are repeated after one is subtracted from k 116 . If k is less than zero 118 , legal net routing is obtained.
- a k-level routing graph is constructed.
- a capacity may be calculated as follows: For each regular edge, the capacity is the height of the corresponding tile expressed in grids, which may be equal to 2 k grids, minus the number of grids covered by routing blockages; for each normal edge, the capacity is the half of the number of vias contained in these tiles. The number of vias is divided by 2, because real vias in the chip should not be placed in neighbor 0-level tiles in an embodiment of the present invention.
- occupancies are added based on previous level ((k+1)-level) net routing and penalties of edges are calculated. For instance, for the first time, i.e. an initial k, this step may be fictitious and occupancies are set of all edges of k-level routing graph to zero. Beginning with the second time when there is (k+1)-level net routing, for each edge of k-level routing graph, occupancy may be calculated as follows. All routed nets of netlist and all edges of (k+1)-level routing of these nets are considered.
- FIG. 3A an example of such a regular edge of previous level routing of a net is shown.
- the tiles are presented by dashed lines and the edge is shown by a solid line.
- vertices A and B are provided on the previous level.
- FIG. 3B four vertices, denoted with subscripts 1, 2, 3 and 4, correspond to each of the previous level vertices.
- C is the capacity of the edge connecting the vertices A and B
- the edge may be denoted by (A B).
- C 1 is the capacity of the edge (A 2 B 1 )
- C 2 is the capacity of the edge (A 4 B 3 ).
- C C 1 +C 2 , and therefore (C 1 /C), (C 1 /2C), (C 2 /C), (C 2 /2C) and (C 2 /2C) is added to occupancy of edges (A 2 B 1 ), (A 1 A 2 ), (B 1 B 2 ), (A 4 B 3 ), (A 3 A 4 ) and (B 3 B 4 ) accordingly.
- FIGS. 4A and 4B The normal edges connecting vertices from neighbor layers are shown on FIGS. 4A and 4B . For instance, let m and m+1 be numbers of these neighbor layers. The tiles of layer m are presented by dashed lines and the tiles of layer m+1 by solid lines. On the previous level, vertices A (belonging to layer m) and B (belonging to layer m+1) are provided. On the current level, which is shown in FIG. 4B , four vertices, denoted with subscripts 1, 2, 3 and 4, correspond to each of the previous level vertices.
- the penalty for passing through an edge may be a function of the quotient occupancy/capacity and of the length of the edge.
- the penalty may be 5(occupancy/capacity)length+length.
- This penalty function may vary although it is preferred that the penalty increase as a function of occupancy/capacity and that the penalty further increases as a function of length.
- the penalty may also be calculated as follows: length•e occupancy/capacity +length.
- the third operational step 206 ( FIG. 2 ) is to route the nets in the net routing area.
- a net routing area is an area based on the net such that the routing of this net, which will be constructed, must be located into this area.
- There are many ways in which to construct the net routing area One way is to construct a bounding box based on x and y coordinates and then expand it in all four direction by r times hp, where r is the input parameter and is usually 1 ⁇ 3, hp is half-perimeter of the bounding box.
- a generalized bounding box of the net may also be constructed based on the grid line directions of all the chip layers.
- FIG. 5 depicts a net including four pins, A, B, C and D.
- a routing of a net is a set E of edges of routing graph such that any two different pins of the net are connected by the set E.
- the net may be partitioned into 2 subnets.
- the method described in U.S. Pat. No. 6,175,950 may be applied, which is herein incorporated by reference in its entirety.
- the center of gravity may be calculated, and then the pins sorted in ascending order of abscissae of the center of gravity.
- ⁇ x 1 , . . . , x n ⁇ be the ordering set of abscissae.
- the point x m divides net into 2 subnets.
- the first subnet includes from m first pins and the second subnet contains another pins. Analogical actions relative to ordinates may also be performed.
- V be the set of vertices of the routing graph and
- VertexNumber.
- the vertices of the routing graph are numerated from 1 to VertexNumber and N(a) is the number of a vertex a.
- An edge connecting vertices a and b is denoted by (a,b).
- Vertices a and b are referred to as a neighbor if there is edge (a, b) in the routing graph.
- (a n ⁇ 1 , a n ), (a n ,b) is called a path connecting vertices a and b.
- the penalty of a path P is the sum of penalties of all edges of the path, and is denoted by Pen(P).
- the input of Procedure to Grow neighborhoods is the set Sour of vertices of the routing graph, which may be referred to as a source set, and a set DestV, referred to as a destination set.
- the procedure to grow neighborhoods may include the following steps.
- d is set equal to d+1. If d ⁇ d max , then the procedure returns to step 2. If d>d max , it means that there is not a path connecting the sets Sour and Dest, and therefore the procedure is exited.
- the methods disclosed may be implemented as sets of instructions or software readable by a device. Further, it is understood that the specific order or hierarchy of steps in the methods disclosed are examples of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the method can be rearranged while remaining within the scope of the present invention.
- the accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
- the instructions may be transmitted over a network in the form of an applet that is interpreted or compiled after transmission to the computer system rather than prior to transmission.
- an applet that is interpreted or compiled after transmission to the computer system rather than prior to transmission.
- the physical storage of the sets of instructions or applets physically changes the medium upon which it is stored electrically, magnetically, chemically, physically, optically or holographically so that the medium carries computer readable information.
Abstract
Description
-
- m
- ∪P1
- i=1
and may be grown until a vertex from the following set is reached: - n
- ∪P1
- i=m+1
Then, going backward, the least-penalty path from one set to another is chosen and this path is included in the routing of the net. Then, the Procedure to Route Net is recursively applied to the nets {P1, . . . , Pm} and {Pm+1, . . . , Pn}.
Procedure to Grow Neighborhoods
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/027,642 US6845495B2 (en) | 2001-12-20 | 2001-12-20 | Multidirectional router |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/027,642 US6845495B2 (en) | 2001-12-20 | 2001-12-20 | Multidirectional router |
Publications (2)
Publication Number | Publication Date |
---|---|
US20030121017A1 US20030121017A1 (en) | 2003-06-26 |
US6845495B2 true US6845495B2 (en) | 2005-01-18 |
Family
ID=21838928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/027,642 Expired - Fee Related US6845495B2 (en) | 2001-12-20 | 2001-12-20 | Multidirectional router |
Country Status (1)
Country | Link |
---|---|
US (1) | US6845495B2 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040098694A1 (en) * | 2002-11-18 | 2004-05-20 | Steven Teig | Method and apparatus for routing |
US20040225983A1 (en) * | 2003-05-07 | 2004-11-11 | Cadence Design Systems, Inc. | Method and apparatus for representing items in a design layout |
US20050240893A1 (en) * | 2000-12-07 | 2005-10-27 | Cadence Design Systems, Inc. | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring |
US6983440B1 (en) | 2003-01-14 | 2006-01-03 | Cadence Design Systems, Inc. | Shape abstraction mechanism |
US7089526B1 (en) * | 2003-01-14 | 2006-08-08 | Cadence Design Systems, Inc. | Maximum flow analysis for electronic circuit design |
US7096445B1 (en) | 2003-01-14 | 2006-08-22 | Cadence Design Systems, Inc. | Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit |
US7222322B1 (en) | 2003-01-14 | 2007-05-22 | Cadence Design Systems, Inc. | Method and mechanism for implementing tessellation-based routing |
US7506295B1 (en) * | 2002-12-31 | 2009-03-17 | Cadence Design Systems, Inc. | Non manhattan floor plan architecture for integrated circuits |
US8201128B2 (en) | 2006-06-16 | 2012-06-12 | Cadence Design Systems, Inc. | Method and apparatus for approximating diagonal lines in placement |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6898773B1 (en) | 2002-01-22 | 2005-05-24 | Cadence Design Systems, Inc. | Method and apparatus for producing multi-layer topological routes |
US6889372B1 (en) | 2000-07-15 | 2005-05-03 | Cadence Design Systems Inc. | Method and apparatus for routing |
US7003754B2 (en) * | 2000-12-07 | 2006-02-21 | Cadence Design Systems, Inc. | Routing method and apparatus that use of diagonal routes |
US7073150B2 (en) * | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
US6738960B2 (en) * | 2001-01-19 | 2004-05-18 | Cadence Design Systems, Inc. | Method and apparatus for producing sub-optimal routes for a net by generating fake configurations |
US7310793B1 (en) | 2001-06-03 | 2007-12-18 | Cadence Design Systems, Inc. | Interconnect lines with non-rectilinear terminations |
US6895569B1 (en) | 2001-06-03 | 2005-05-17 | Candence Design Systems, Inc. | IC layout with non-quadrilateral Steiner points |
US6951005B1 (en) | 2001-06-03 | 2005-09-27 | Cadence Design Systems, Inc. | Method and apparatus for selecting a route for a net based on the impact on other nets |
US6976238B1 (en) | 2001-06-03 | 2005-12-13 | Cadence Design Systems, Inc. | Circular vias and interconnect-line ends |
US6829757B1 (en) | 2001-06-03 | 2004-12-07 | Cadence Design Systems, Inc. | Method and apparatus for generating multi-layer routes |
US6859916B1 (en) | 2001-06-03 | 2005-02-22 | Cadence Design Systems, Inc. | Polygonal vias |
US6882055B1 (en) | 2001-06-03 | 2005-04-19 | Cadence Design Systems, Inc. | Non-rectilinear polygonal vias |
US6877149B2 (en) * | 2001-08-23 | 2005-04-05 | Cadence Design Systems, Inc. | Method and apparatus for pre-computing routes |
US6973634B1 (en) * | 2002-01-22 | 2005-12-06 | Cadence Design Systems, Inc. | IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout |
US7089524B1 (en) | 2002-01-22 | 2006-08-08 | Cadence Design Systems, Inc. | Topological vias route wherein the topological via does not have a coordinate within the region |
US6892371B1 (en) | 2002-01-22 | 2005-05-10 | Cadence Design Systems, Inc. | Method and apparatus for performing geometric routing |
US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
US7117468B1 (en) | 2002-01-22 | 2006-10-03 | Cadence Design Systems, Inc. | Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts |
US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
US7069531B1 (en) | 2002-07-15 | 2006-06-27 | Cadence Design Systems, Inc. | Method and apparatus for identifying a path between source and target states in a space with more than two dimensions |
US7047512B1 (en) | 2002-06-04 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space |
US7073151B1 (en) | 2002-06-04 | 2006-07-04 | Cadence Design Systems, Inc. | Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space |
US7051298B1 (en) | 2002-06-04 | 2006-05-23 | Cadence Design Systems, Inc. | Method and apparatus for specifying a distance between an external state and a set of states in space |
US7002572B1 (en) | 2002-06-19 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for constructing a convex polygon that encloses a set of points in a region |
US6976237B1 (en) | 2002-06-19 | 2005-12-13 | Cadence Design Systems, Inc. | Method and apparatus for estimating distances in a region |
US6879934B1 (en) | 2002-06-19 | 2005-04-12 | Cadence Design Systems, Inc. | Method and apparatus for estimating distances in a region |
US7624367B2 (en) * | 2002-11-18 | 2009-11-24 | Cadence Design Systems, Inc. | Method and system for routing |
US7047513B2 (en) | 2002-11-18 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for searching for a three-dimensional global path |
US6988257B2 (en) * | 2002-11-18 | 2006-01-17 | Cadence Design Systems, Inc. | Method and apparatus for routing |
US7003752B2 (en) | 2002-11-18 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for routing |
US7480885B2 (en) * | 2002-11-18 | 2009-01-20 | Cadence Design Systems, Inc. | Method and apparatus for routing with independent goals on different layers |
US6936898B2 (en) * | 2002-12-31 | 2005-08-30 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
US7065731B2 (en) * | 2003-05-07 | 2006-06-20 | Cadence Design Systems, Inc. | Removal of acute angles in a design layout |
US7080339B2 (en) | 2003-05-07 | 2006-07-18 | Cadence Design Systems, Inc. | Plane representation of wiring in a design layout |
US7306977B1 (en) | 2003-08-29 | 2007-12-11 | Xilinx, Inc. | Method and apparatus for facilitating signal routing within a programmable logic device |
US7174528B1 (en) | 2003-10-10 | 2007-02-06 | Transmeta Corporation | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure |
US7645673B1 (en) * | 2004-02-03 | 2010-01-12 | Michael Pelham | Method for generating a deep N-well pattern for an integrated circuit design |
US7388260B1 (en) | 2004-03-31 | 2008-06-17 | Transmeta Corporation | Structure for spanning gap in body-bias voltage routing structure |
US7571408B1 (en) | 2005-03-09 | 2009-08-04 | Cadence Design Systems, Inc. | Methods and apparatus for diagonal route shielding |
US7305647B1 (en) * | 2005-07-28 | 2007-12-04 | Transmeta Corporation | Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage |
US7472366B1 (en) * | 2005-08-01 | 2008-12-30 | Cadence Design Systems, Inc. | Method and apparatus for performing a path search |
US7694258B1 (en) | 2005-08-01 | 2010-04-06 | Cadence Design Systems, Inc. | Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout |
US7376921B2 (en) * | 2006-02-17 | 2008-05-20 | Athena Design Systems, Inc. | Methods for tiling integrated circuit designs |
TWM460297U (en) * | 2013-01-22 | 2013-08-21 | Darfon Electronics Corp | Back light structure and keyboard with back light |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5340772A (en) | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
US5493508A (en) | 1994-06-01 | 1996-02-20 | Lsi Logic Corporation | Specification and design of complex digital systems |
US5532934A (en) | 1992-07-17 | 1996-07-02 | Lsi Logic Corporation | Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions |
US5822214A (en) | 1994-11-02 | 1998-10-13 | Lsi Logic Corporation | CAD for hexagonal architecture |
US6230306B1 (en) * | 1998-04-17 | 2001-05-08 | Lsi Logic Corporation | Method and apparatus for minimization of process defects while routing |
US6317864B1 (en) | 1998-03-24 | 2001-11-13 | Nec Corporation | System and method for graphic layout modification |
-
2001
- 2001-12-20 US US10/027,642 patent/US6845495B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5340772A (en) | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
US5532934A (en) | 1992-07-17 | 1996-07-02 | Lsi Logic Corporation | Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions |
US5493508A (en) | 1994-06-01 | 1996-02-20 | Lsi Logic Corporation | Specification and design of complex digital systems |
US5822214A (en) | 1994-11-02 | 1998-10-13 | Lsi Logic Corporation | CAD for hexagonal architecture |
US6317864B1 (en) | 1998-03-24 | 2001-11-13 | Nec Corporation | System and method for graphic layout modification |
US6230306B1 (en) * | 1998-04-17 | 2001-05-08 | Lsi Logic Corporation | Method and apparatus for minimization of process defects while routing |
Non-Patent Citations (1)
Title |
---|
"Standard-Cell Design", M.J.S. Smith, ASIC Library Design, Addison-Wesley, 1997, Chapter 3, p. 150. |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050240893A1 (en) * | 2000-12-07 | 2005-10-27 | Cadence Design Systems, Inc. | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring |
US7171635B2 (en) * | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
US20040098694A1 (en) * | 2002-11-18 | 2004-05-20 | Steven Teig | Method and apparatus for routing |
US7506295B1 (en) * | 2002-12-31 | 2009-03-17 | Cadence Design Systems, Inc. | Non manhattan floor plan architecture for integrated circuits |
US7089526B1 (en) * | 2003-01-14 | 2006-08-08 | Cadence Design Systems, Inc. | Maximum flow analysis for electronic circuit design |
US7096445B1 (en) | 2003-01-14 | 2006-08-22 | Cadence Design Systems, Inc. | Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit |
US6983440B1 (en) | 2003-01-14 | 2006-01-03 | Cadence Design Systems, Inc. | Shape abstraction mechanism |
US7222322B1 (en) | 2003-01-14 | 2007-05-22 | Cadence Design Systems, Inc. | Method and mechanism for implementing tessellation-based routing |
US7516433B1 (en) | 2003-01-14 | 2009-04-07 | Cadence Design Systems, Inc. | Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit |
US7594214B1 (en) | 2003-01-14 | 2009-09-22 | Cadence Design Systems, Inc. | Maximum flow analysis for electronic circuit design |
US7694261B1 (en) | 2003-01-14 | 2010-04-06 | Cadence Design Systems, Inc. | Method and mechanism for implementing tessellation-based routing |
US7752590B1 (en) | 2003-01-14 | 2010-07-06 | Cadence Design Systems, Inc. | Method and mechanism for implementing tessellation-based routing |
US7243328B2 (en) * | 2003-05-07 | 2007-07-10 | Cadence Design Systems, Inc. | Method and apparatus for representing items in a design layout |
US20040225983A1 (en) * | 2003-05-07 | 2004-11-11 | Cadence Design Systems, Inc. | Method and apparatus for representing items in a design layout |
US8201128B2 (en) | 2006-06-16 | 2012-06-12 | Cadence Design Systems, Inc. | Method and apparatus for approximating diagonal lines in placement |
Also Published As
Publication number | Publication date |
---|---|
US20030121017A1 (en) | 2003-06-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6845495B2 (en) | Multidirectional router | |
US6895567B1 (en) | Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs | |
EP0932874B1 (en) | A method and apparatus for routing of nets in an electronic device | |
US5583788A (en) | Automatic layout design method of wirings in integrated circuit using hierarchical algorithm | |
EP0133466B1 (en) | Simultaneous placement and wiring for vlsi chips | |
US4908772A (en) | Integrated circuits with component placement by rectilinear partitioning | |
US8006216B1 (en) | Dynamic push for topological routing of semiconductor packages | |
US6678872B2 (en) | Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout | |
US6763512B2 (en) | Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits | |
US20020170020A1 (en) | Method and system of modifying integrated circuit power rails | |
US20050240893A1 (en) | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring | |
JPH05502549A (en) | Improved routing apparatus and method for integrated circuits | |
US8250514B1 (en) | Localized routing direction | |
US6397375B1 (en) | Method for managing metal resources for over-the-block routing in integrated circuits | |
US6735754B2 (en) | Method and apparatus to facilitate global routing for an integrated circuit layout | |
US6901506B2 (en) | Maximal tile generation technique and associated methods for designing and manufacturing VLSI circuits | |
US6532580B1 (en) | In-place method for inserting repeater buffers in an integrated circuit | |
JP2000067102A (en) | Hierarchical wiring method for semiconductor integrated circuit | |
US6408426B1 (en) | Method for determining locations of interconnect repeater farms during physical design of integrated circuits | |
US6477690B1 (en) | In-place repeater insertion methodology for over-the-block routed integrated circuits | |
Liu et al. | Substrate topological routing for high-density packages | |
US11461529B1 (en) | Routing with soft-penalizing pixels on a found path | |
US20020129326A1 (en) | Method for inserting repeaters in hierarchical chip design | |
JP4262660B2 (en) | Sequence pair creation device and sequence pair creation method | |
JP3422839B2 (en) | Logic cell division processing method for semiconductor integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LSI LOGIC CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDREEV, ALEXANDRE E.;SCEPANOVIC, RANKO;GASANOV, ELYAR E.;REEL/FRAME:012408/0121;SIGNING DATES FROM 20011214 TO 20011217 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
|
AS | Assignment |
Owner name: LSI CORPORATION, CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270 Effective date: 20070406 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388 Effective date: 20140814 |
|
AS | Assignment |
Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20170118 |
|
AS | Assignment |
Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044887/0109 Effective date: 20171208 |
|
AS | Assignment |
Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
|
AS | Assignment |
Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0223 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0223 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0223 Effective date: 20220401 |