US6917366B1 - System and method for aligning multi-channel coded data over multiple clock periods - Google Patents
System and method for aligning multi-channel coded data over multiple clock periods Download PDFInfo
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- US6917366B1 US6917366B1 US09/826,538 US82653801A US6917366B1 US 6917366 B1 US6917366 B1 US 6917366B1 US 82653801 A US82653801 A US 82653801A US 6917366 B1 US6917366 B1 US 6917366B1
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- data
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- circuit
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- signal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/18—Timing circuits for raster scan displays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Abstract
Description
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/826,538 US6917366B1 (en) | 2000-04-04 | 2001-04-04 | System and method for aligning multi-channel coded data over multiple clock periods |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US19455700P | 2000-04-04 | 2000-04-04 | |
US09/826,538 US6917366B1 (en) | 2000-04-04 | 2001-04-04 | System and method for aligning multi-channel coded data over multiple clock periods |
Publications (1)
Publication Number | Publication Date |
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US6917366B1 true US6917366B1 (en) | 2005-07-12 |
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US09/826,538 Expired - Lifetime US6917366B1 (en) | 2000-04-04 | 2001-04-04 | System and method for aligning multi-channel coded data over multiple clock periods |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7088398B1 (en) * | 2001-12-24 | 2006-08-08 | Silicon Image, Inc. | Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data |
US20060187966A1 (en) * | 2005-02-23 | 2006-08-24 | Wai-Bor Leung | Distributed multiple-channel alignment scheme |
US20060222017A1 (en) * | 2005-04-01 | 2006-10-05 | Quiroga Emilio J | Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface |
US20060273941A1 (en) * | 2005-06-02 | 2006-12-07 | Agere Systems, Inc. | Content deskewing for multichannel synchronization |
KR101058518B1 (en) | 2010-07-23 | 2011-08-23 | 주식회사 더즈텍 | Device and method of data symbol locking |
US8750320B2 (en) | 1997-01-23 | 2014-06-10 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US8798091B2 (en) | 1998-11-19 | 2014-08-05 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US9600232B2 (en) | 2013-12-11 | 2017-03-21 | International Business Machines Corporation | Aligning FIFO pointers in a data communications lane of a serial link |
CN113872745A (en) * | 2021-08-20 | 2021-12-31 | 中国船舶重工集团公司第七二三研究所 | Multichannel signal synchronization system and method |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4647986A (en) * | 1984-08-06 | 1987-03-03 | General Electric Company | Storing video images on disk using video time base and retrieving the images using disk time base |
US5887039A (en) * | 1993-12-16 | 1999-03-23 | Nec Corporation | Data transmission system using specific pattern for synchronization |
US6151334A (en) * | 1995-10-05 | 2000-11-21 | Silicon Image, Inc. | System and method for sending multiple data signals over a serial link |
US6512804B1 (en) * | 1999-04-07 | 2003-01-28 | Applied Micro Circuits Corporation | Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter |
US6578153B1 (en) * | 2000-03-16 | 2003-06-10 | Fujitsu Network Communications, Inc. | System and method for communications link calibration using a training packet |
US6578092B1 (en) * | 1999-04-21 | 2003-06-10 | Cisco Technology, Inc. | FIFO buffers receiving data from different serial links and removing unit of data from each buffer based on previous calcuations accounting for trace length differences |
-
2001
- 2001-04-04 US US09/826,538 patent/US6917366B1/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4647986A (en) * | 1984-08-06 | 1987-03-03 | General Electric Company | Storing video images on disk using video time base and retrieving the images using disk time base |
US5887039A (en) * | 1993-12-16 | 1999-03-23 | Nec Corporation | Data transmission system using specific pattern for synchronization |
US6151334A (en) * | 1995-10-05 | 2000-11-21 | Silicon Image, Inc. | System and method for sending multiple data signals over a serial link |
US6512804B1 (en) * | 1999-04-07 | 2003-01-28 | Applied Micro Circuits Corporation | Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter |
US6578092B1 (en) * | 1999-04-21 | 2003-06-10 | Cisco Technology, Inc. | FIFO buffers receiving data from different serial links and removing unit of data from each buffer based on previous calcuations accounting for trace length differences |
US6578153B1 (en) * | 2000-03-16 | 2003-06-10 | Fujitsu Network Communications, Inc. | System and method for communications link calibration using a training packet |
Non-Patent Citations (1)
Title |
---|
Digital Display Working Group (DDWG); Digital Visual Interface DVI, Revision 1.0; Apr. 2, 1999; pp. 1-76. |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8750320B2 (en) | 1997-01-23 | 2014-06-10 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US8774199B2 (en) | 1997-01-23 | 2014-07-08 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US8767756B2 (en) | 1997-01-23 | 2014-07-01 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US8798091B2 (en) | 1998-11-19 | 2014-08-05 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US7088398B1 (en) * | 2001-12-24 | 2006-08-08 | Silicon Image, Inc. | Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data |
US20060187966A1 (en) * | 2005-02-23 | 2006-08-24 | Wai-Bor Leung | Distributed multiple-channel alignment scheme |
WO2006091527A2 (en) * | 2005-02-23 | 2006-08-31 | Lattice Semiconductor Corporation | Distributed multiple-channel alignment scheme |
WO2006091527A3 (en) * | 2005-02-23 | 2007-05-31 | Lattice Semiconductor Corp | Distributed multiple-channel alignment scheme |
US7532646B2 (en) | 2005-02-23 | 2009-05-12 | Lattice Semiconductor Corporation | Distributed multiple-channel alignment scheme |
US7936793B2 (en) * | 2005-04-01 | 2011-05-03 | Freescale Semiconductor, Inc. | Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface |
US20060222017A1 (en) * | 2005-04-01 | 2006-10-05 | Quiroga Emilio J | Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface |
US7549074B2 (en) * | 2005-06-02 | 2009-06-16 | Agere Systems Inc. | Content deskewing for multichannel synchronization |
US20060273941A1 (en) * | 2005-06-02 | 2006-12-07 | Agere Systems, Inc. | Content deskewing for multichannel synchronization |
WO2012011772A2 (en) * | 2010-07-23 | 2012-01-26 | 주식회사 더즈텍 | Apparatus and method for locking data symbols |
WO2012011772A3 (en) * | 2010-07-23 | 2012-05-03 | 주식회사 더즈텍 | Apparatus and method for locking data symbols |
KR101058518B1 (en) | 2010-07-23 | 2011-08-23 | 주식회사 더즈텍 | Device and method of data symbol locking |
US9600232B2 (en) | 2013-12-11 | 2017-03-21 | International Business Machines Corporation | Aligning FIFO pointers in a data communications lane of a serial link |
CN113872745A (en) * | 2021-08-20 | 2021-12-31 | 中国船舶重工集团公司第七二三研究所 | Multichannel signal synchronization system and method |
CN113872745B (en) * | 2021-08-20 | 2024-02-13 | 中国船舶重工集团公司第七二三研究所 | Multichannel signal synchronization system and method |
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