US7009883B2 - Automatic programming time selection for one time programmable memory - Google Patents
Automatic programming time selection for one time programmable memory Download PDFInfo
- Publication number
- US7009883B2 US7009883B2 US10/696,356 US69635603A US7009883B2 US 7009883 B2 US7009883 B2 US 7009883B2 US 69635603 A US69635603 A US 69635603A US 7009883 B2 US7009883 B2 US 7009883B2
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- bit
- time
- programmed
- programming
- program
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- 230000015654 memory Effects 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000012360 testing method Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
Definitions
- the present invention relates to one-time programmable (OTP) memories, and more particularly, to a more efficient system and method for programming the memories faster.
- OTP one-time programmable
- the OTP memory has a gate oxide barrier that can be broken down by applying a voltage to one side of the gate. When the barrier is broken down, the resistance to the power rail (or the ground rail) becomes lower and the value is forever stored in the OTP bit. The value is either a 1 or 0.
- the time required to break down the barrier and program the bit is variable depending on the fabrication process of the silicon. Some memories require a longer programming time to program a bit if the wafer process is skewed to one comer of the fabrication process. Other memories will program in shorter periods of time.
- a particular problem that exists is the non-uniformity in programming time for one-time programmable memories.
- a wafer or a particular programmable memory might have 99% of its bits that may be programmed in a fairly short time, for example, 10 ⁇ sec.
- a handful of bits are such that they require much longer programming, sometimes as long as 1 sec.
- the longest possible time required to program any bit as the time to program all the bits means that for a 1K-bit memory, 1000 seconds would be required to program it. This means that the throughput of the programming device used to program the memories is extremely low, causing an increase in the cost of manufacturing of the memories.
- Tester time is costly, so a method is needed to determine the minimum amount of programming time to use on the tester.
- the present invention is directed to automatic programming time selection for one time programmable memory that substantially obviates, one or more of the disadvantages of the related art.
- a method of programming a memory including the steps of attempting to program a bit at a designated address for a predetermined time; testing the bit to see if it has been programmed; increasing the predetermined time by approximately an order of magnitude; repeating the previous steps (until the bit at the designated address is programmed; and repeating all the previous steps by advancing the designated address until all bits in the memory are programmed.
- FIG. 1 illustrates the proposed programming method according to the present invention.
- the programming of a bit in the OTP memory done based on time. If a bit is programmed for time X (e.g., 10 ⁇ sec), and the tester returns a GOOD status, the programming of the bit is done. If the time X program cycle is complete, and the bit is not programmed correctly yet, the programming can be done again (and again) until it returns a GOOD status.
- time X e.g. 10 ⁇ sec
- the gate oxide barrier of the OTP memory will have lower and lower resistance with each programming attempt. However lab results show that if a bit fails the first attempt, the subsequent attempts must be longer in duration to reach success.
- the algorithm is implemented in logic that will select the program time based on seeing the same bit get programmed repeatedly. On the first attempt, a default time is selected. On the second attempt, the address of the bit is compared and found to be the same location, then the programming time is extended by approximately an order of magnitude. On the third attempt, if the address is the same again, the program time is extended even longer. The process can continue.
- the programming can move on to another bit and the time can drop back to the shorter default value.
- FIG. 1 illustrates a flow diagram of the programming method of the present invention.
- the programming apparatus waits for a program Start command (step 101 ).
- a bit address is selected for programming (step 102 ). If the address is equal to the previous address (step 103 ), program time is increased (step 104 ). The bit is then programmed (step 105 ). On the next step, the status of the bit (Good or Bad) is returned to the tester (step 106 ). The tester then returns back to step 101 .
- a short (i.e., default or standard) program time is selected (step 107 ). The bit is then programmed (see step 105 , etc.)
- a set of bits can be used to determine the wafer process. These bits are programmed once for a short period. If any bits fail, then the wafer is assumed to be slow to program and a configuration bit (or bits) in the OTP is then programmed that will cause all future program times to be extended by roughly an order of magnitude.
- the default starting point for the program time can be selected based on the wafer process.
- the programming method of the present invention tests each bit to see whether it belongs to a fast programmable bit or a slow programmable bit.
- Most bits are typically of the fast programming type, and may be programmed, for example, in 10–20 ⁇ sec.
- the method involves programming a bit that corresponds to a given address, and then testing to see if the bit has in fact been programmed during the 10 ⁇ sec. If the bit programming was successful, then the programming apparatus moves onto the bit at the next address. If the programming has not been successful, then the tester increases the time required to program that particular bit by, for example, a factor of 10. The tester then tries again to program the bit. Following the next attempt, the tester again checks to see if the bit has been successfully programmed. If it has, then it moves onto the bit at the next address. If it has not, then it again increases the time required to program this particular bit by, for example, a factor of 10, and the process repeats itself.
Abstract
Description
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/696,356 US7009883B2 (en) | 2003-02-27 | 2003-10-30 | Automatic programming time selection for one time programmable memory |
Applications Claiming Priority (2)
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US44985603P | 2003-02-27 | 2003-02-27 | |
US10/696,356 US7009883B2 (en) | 2003-02-27 | 2003-10-30 | Automatic programming time selection for one time programmable memory |
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US20040170059A1 US20040170059A1 (en) | 2004-09-02 |
US7009883B2 true US7009883B2 (en) | 2006-03-07 |
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US10/696,356 Expired - Lifetime US7009883B2 (en) | 2003-02-27 | 2003-10-30 | Automatic programming time selection for one time programmable memory |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070236991A1 (en) * | 2006-03-28 | 2007-10-11 | Shih-Chung Lee | Program time adjustment as function of program voltage for improved programming speed in programming method |
US20070237008A1 (en) * | 2006-03-28 | 2007-10-11 | Shih-Chung Lee | Program time adjustment as function of program voltage for improved programming speed in memory system |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5524767B2 (en) * | 2009-09-02 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Semiconductor device and driving method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5467309A (en) * | 1993-09-06 | 1995-11-14 | Hitachi, Ltd. | Semiconductor nonvolatile memory device having reduced switching overhead time on the program mode |
US5991201A (en) * | 1998-04-27 | 1999-11-23 | Motorola Inc. | Non-volatile memory with over-program protection and method therefor |
US6396738B1 (en) * | 2000-09-28 | 2002-05-28 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory device capable of suppressing writing and erasure failure rate |
US6525955B1 (en) | 2001-12-18 | 2003-02-25 | Broadcom Corporation | Memory cell with fuse element |
US6693819B2 (en) | 2002-01-08 | 2004-02-17 | Broadcom Corporation | High voltage switch circuitry |
US6700176B2 (en) | 2002-07-18 | 2004-03-02 | Broadcom Corporation | MOSFET anti-fuse structure and method for making same |
US6704236B2 (en) | 2002-01-03 | 2004-03-09 | Broadcom Corporation | Method and apparatus for verification of a gate oxide fuse element |
-
2003
- 2003-10-30 US US10/696,356 patent/US7009883B2/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5467309A (en) * | 1993-09-06 | 1995-11-14 | Hitachi, Ltd. | Semiconductor nonvolatile memory device having reduced switching overhead time on the program mode |
US5991201A (en) * | 1998-04-27 | 1999-11-23 | Motorola Inc. | Non-volatile memory with over-program protection and method therefor |
US6396738B1 (en) * | 2000-09-28 | 2002-05-28 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory device capable of suppressing writing and erasure failure rate |
US6525955B1 (en) | 2001-12-18 | 2003-02-25 | Broadcom Corporation | Memory cell with fuse element |
US6704236B2 (en) | 2002-01-03 | 2004-03-09 | Broadcom Corporation | Method and apparatus for verification of a gate oxide fuse element |
US6693819B2 (en) | 2002-01-08 | 2004-02-17 | Broadcom Corporation | High voltage switch circuitry |
US6700176B2 (en) | 2002-07-18 | 2004-03-02 | Broadcom Corporation | MOSFET anti-fuse structure and method for making same |
US6902958B2 (en) | 2002-07-18 | 2005-06-07 | Broadcom Corporation | Method for making MOSFET anti-fuse structure |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070236991A1 (en) * | 2006-03-28 | 2007-10-11 | Shih-Chung Lee | Program time adjustment as function of program voltage for improved programming speed in programming method |
US20070237008A1 (en) * | 2006-03-28 | 2007-10-11 | Shih-Chung Lee | Program time adjustment as function of program voltage for improved programming speed in memory system |
US7327608B2 (en) * | 2006-03-28 | 2008-02-05 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in programming method |
US7330373B2 (en) | 2006-03-28 | 2008-02-12 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in memory system |
US20080137432A1 (en) * | 2006-03-28 | 2008-06-12 | Shih-Chung Lee | Program Time Adjustment as Function of Program Voltage For Improved Programming Speed in Memory System |
US7675780B2 (en) | 2006-03-28 | 2010-03-09 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in memory system |
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US20040170059A1 (en) | 2004-09-02 |
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