US7087500B2 - Charge trapping memory cell - Google Patents
Charge trapping memory cell Download PDFInfo
- Publication number
- US7087500B2 US7087500B2 US10/894,348 US89434804A US7087500B2 US 7087500 B2 US7087500 B2 US 7087500B2 US 89434804 A US89434804 A US 89434804A US 7087500 B2 US7087500 B2 US 7087500B2
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- United States
- Prior art keywords
- layer
- depositing
- trenches
- oxide
- semiconductor body
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 230000015654 memory Effects 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 238000003860 storage Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 12
- 230000000873 masking effect Effects 0.000 claims 7
- 239000011810 insulating material Substances 0.000 claims 3
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000009827 uniform distribution Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 8
- 244000208734 Pisonia aculeata Species 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000265 homogenisation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates generally to memories, and more particularly to a charge trapping memory cell.
- Memory transistors with a dielectric storage layer sequence are usually embodied as planar transistors or as trench transistors.
- the structure of these transistors therefore corresponds to the structure of standard NMOS transistors.
- the gate dielectric is replaced by a storage layer sequence comprising a storage layer between boundary layers, in which charge carriers from the channel are trapped during the programming of the memory cell.
- storage layer sequences comprising a channel-side bottom oxide having a typical thickness of 6 nm, a silicon nitride storage layer having a thickness of typically 6 nm and a top oxide on the side of the gate electrode having a thickness of typically 12 nm.
- the disadvantages of such a thick gate dielectric are a poor gate control, associated with a poor slope of the control curve, a high threshold voltage and an unfavorable scalability.
- the present invention provides an improved charge trapping memory cell which affords a sufficiently good gate control even in the case of embodiments in the sub-hundred nm range.
- the charge trapping memory cell of the preferred embodiment is based on the insight that the known phenomenon of a corner device occurs with a distinct elevation of the electric field at the lateral margins of the transistor channel. This is because the memory cell is delimited there by insulation regions for which reason edges are present at the margins of the active regions formed by the semiconductor material.
- the semiconductor material is doped there, albeit only in the low dopant concentration of typically 10 17 cm ⁇ 3 as is customary for well regions, and is therefore conductive.
- the electric field is thus essentially perpendicular to the conductor surface, so that a very high field strength occurs at the edges of the semiconductor material.
- the charge trapping memory cell is formed such that a largely homogeneous distribution of the magnitude of the electric field is present in the channel region.
- a largely homogeneous distribution of the magnitude of the electric field is present in the channel region. This is achieved by virtue of the fact that the top side of the channel region, which faces the gate electrode, is bulged in the direction transversely with respect to the longitudinal direction of the channel (that is to say transversely with respect to the connection between the source and drain regions) and in this case preferably assumes the form of an outer surface of a semicylinder.
- the largely uniform curvature results in a homogenization of the electric field, which is directed radially everywhere with respect to the cylinder form and preferably has at least approximately the same magnitude everywhere.
- the programming voltage can be decreased from typically 9 volts in the case of planar channel regions to approximately 6 volts in the case of the cylindrically symmetrical arrangement, given the same electron concentration in the channel.
- the charge trapping memory cell makes it possible to further reduce the dimensions of the memory cell in conjunction with improved gate control.
- the gate control is no longer determined by the electrostatic properties of a planar capacitor with corresponding fields in the planar dielectric (i.e., constant field strength), but rather by the properties of a cylindrical capacitor with radially symmetrical field dependence.
- FIGS. 1 to 6 Examples of the charge trapping memory cell will be described in more detail below with reference to FIGS. 1 to 6 which provide:
- FIG. 1 shows an intermediate product of the fabrication of the memory cell after the patterning of pad oxide and pad nitride
- FIG. 2 shows the cross section in accordance with FIG. 1 after the etching of isolation trenches
- FIG. 3 shows the cross section of FIG. 2 after an oxide filling of the trenches
- FIG. 4 shows the cross section of FIG. 3 after an etching-back of the oxide filling
- FIG. 5 shows the cross section of FIG. 4 after the application of a layer sequence provided for word lines
- FIG. 6 shows the arrangement of the isolation trenches and word lines schematically in plan view.
- FIG. 1 shows a cross section through a semiconductor body 1 or a substrate made of semiconductor material.
- a thin layer is applied as a pad oxide to an essentially planar top side in a conventional manner, and a layer is applied as a pad nitride to said thin layer.
- These layers are patterned by means of a suitable mask technique (lithography) such that the pad oxide 2 and the pad nitride 3 are removed in the region where STI isolations (shallow trench isolations) will be fabricated.
- the STI isolations are provided for insulating series of memory cells of a memory cell array from one another.
- the patterning of pad oxide 2 and pad nitride 3 is effected for example by means of RIE (reactive ion etching).
- the etching step is preferably performed such that the uncovered semiconductor material of the semiconductor body 1 is etched using the same mask, so that trenches are formed in the semiconductor material.
- FIG. 2 shows the cross section in accordance with FIG. 1 , after the trenches 4 have been etched into the semiconductor material in the regions in which the pad oxide 2 and the pad nitride 3 were removed.
- FIG. 2 illustrates the cross section transversely with respect to the longitudinal direction of the trenches. The trenches thus run perpendicularly to the plane of the drawing with an at least approximately uniform cross section.
- a further etching step follows as pull-back, by means of which the residual strip-like portions of the pad nitride 3 are etched back laterally and the nitride strips are thus narrowed.
- this pull-back etch is not absolutely necessary, it makes a significant contribution to the desired rounding of the edges of the semiconductor material in subsequent fabrication steps. Therefore, it is particularly preferred.
- a thermal oxide is grown on as a liner in a manner known per se.
- the dimensions of the rounding of the edges of the semiconductor material can likewise be influenced by the thickness of the layer made of thermal oxide and the process control during the fabrication thereof.
- the trenches are then filled with oxide 6 , which is removed in planarizing fashion on the top side as far as the top side of the pad nitride 3 . This may be effected e.g. by means of CMP (chemical mechanical polishing).
- FIG. 3 shows the cross section corresponding to FIG. 2 after these method steps. It can be seen in FIG. 3 that the residual strip-type portions of the pad nitride 3 have been laterally etched back somewhat as a result of the pull-back etching step. Therefore, the sidewalls 5 of the strip-type portions of the pad nitride 3 are situated such that they are set back somewhat with respect to the walls of the trenches (labeled 4 in FIG. 2 ) in the direction of the semiconductor material webs present between the latter.
- the pull-back etching step and the fabrication of the liner made of thermal oxide have resulted in the formation of the bulges 7 at the edges of the semiconductor webs.
- a lithography additionally ensues for implantation of dopant for the formation of the doped well 8 .
- a selective etching of the nitride and a preferably wet-chemical etching-back of the oxide filling 6 yields the structure illustrated in FIG. 4 , where reference numeral 6 denotes the residual oxide filling.
- top-side bulges of the webs made of semiconductor material are clearly discernable in FIG. 4 .
- These bulges 7 form a top-side rounding which, by way of example, may have the form of the outer surface of a semicylinder.
- the bulges 7 are illustrated somewhat flatter, however, in FIG. 4 since what is desired is that no sharp edges are present at the lateral margins of the channel regions.
- the residual portions 6 ′ of the oxide filling form the STI isolations between series of memory cells.
- the longitudinal directions of the channel regions run parallel to the STI isolations, i.e. perpendicularly to the plane of the drawing.
- the channel regions are bulged owing to the bulges 7 present in the transverse direction and are thus widened with respect to a planar channel region present in the plane formed by the top side of the semiconductor body 1 or substrate, so that the channel width is correspondingly larger. If appropriate, therefore, the lateral dimensions of the semiconductor webs may be correspondingly reduced and the lateral dimensions of the memory cells may thus also be reduced.
- the channel width is measured at the curved top side of the semiconductor material, to be precise over the region which is controlled by the gate electrode that is to be applied later. This region ends at the top side of the portions 6 ′ of the oxide filling. It suffices if the top side of the channel region is sufficiently uniformly curved only in regions and is formed in planar fashion at most up to a third of the channel width, preferably in a central region of the channel, and coincides there with the plane of the top side of the semiconductor body 1 .
- a plane touching the semiconductor material on the top side may be interpreted as a plane determined by the top side.
- the bulge 7 may be assumed to be at least so greatly pronounced that a maximum difference in height of two points at the top side of the channel region with respect to a plane determined by the top side of the semiconductor body 1 or substrate, measured in a direction perpendicular to said plane, amounts to at least one third of the dimensioning of a projection of the top side of the channel region into said plane.
- the maximum perpendicular dimension of the hatched region amounts to at least one third of the lower boundary section of the hatched region.
- a storage layer sequence 9 may then be deposited onto the top side, this forming the storage medium of the memory cell.
- the storage layer sequence 9 comprises an actual storage layer between boundary layers.
- the boundary layers are for example an oxide of the semiconductor material, for example silicon dioxide. Silicon nitride, tantalum oxide, hafnium silicate, titanium oxide, zirconium oxide, aluminum oxide, intrinsically conducting silicon or germanium are taken into consideration for the storage layer.
- the storage layer sequence may be formed in particular in the manner of the ONO layer of a SONOS memory cell.
- the layers provided for the word lines which also form respective gate electrodes, are deposited. They are for example a polysilicon layer 10 , a tungsten silicide layer 11 and a nitride layer 12 which is patterned to form the hard mask and with the aid of which the polysilicon layer 10 and the tungsten silicide layer 11 are patterned to form strip-type word lines arranged parallel at a distance with respect to one another.
- the word lines run transversely with respect to the longitudinal directions of the STI isolations.
- Dopant is then implanted, likewise using the hard mask layer formed by the nitride layer 12 , in order to fabricate the source/drain regions in a self-aligned manner.
- Spacers made of dielectric material may additionally be provided at the sidewalls of the word lines, in order to be able to better set the distance between the gate electrodes and the source/drain regions and thus to be able to better predetermine the transistor properties.
- Process steps then follow for making contact with the source/drain regions and connecting the gate electrodes. Such process steps are known per se from the fabrication of semiconductor memories.
- FIG. 6 illustrates a plan view of the scheme of the STI isolations 13 , the word lines 15 and the source/drain regions 14 formed in a self-aligned manner with respect thereto.
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10333549A DE10333549B3 (en) | 2003-07-23 | 2003-07-23 | Charge trapping memory cell used as transistor comprises semiconductor body or substrate having upper side with curve in channel region |
DE10333549.8 | 2003-07-23 |
Publications (2)
Publication Number | Publication Date |
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US20050045963A1 US20050045963A1 (en) | 2005-03-03 |
US7087500B2 true US7087500B2 (en) | 2006-08-08 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/894,348 Expired - Fee Related US7087500B2 (en) | 2003-07-23 | 2004-07-19 | Charge trapping memory cell |
Country Status (3)
Country | Link |
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US (1) | US7087500B2 (en) |
CN (1) | CN100382323C (en) |
DE (1) | DE10333549B3 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008172200A (en) * | 2006-11-01 | 2008-07-24 | Macronix Internatl Co Ltd | Cylindrical channel charge trapping devices with substantially high coupling ratios |
US20090323411A1 (en) * | 2008-06-30 | 2009-12-31 | Qimonda Ag | Method including selective treatment of storage layer |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI277210B (en) * | 2004-10-26 | 2007-03-21 | Nanya Technology Corp | FinFET transistor process |
KR100676598B1 (en) | 2005-04-01 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor memory device |
CN101046719B (en) * | 2006-03-28 | 2011-05-25 | 达诺光电股份有限公司 | Capacitor type contact panel |
US20070284650A1 (en) * | 2006-06-07 | 2007-12-13 | Josef Willer | Memory device and a method of forming a memory device |
US8642441B1 (en) * | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
KR20080102030A (en) * | 2007-05-17 | 2008-11-24 | 삼성전자주식회사 | Flash memory device and manufacturing method and operating method thereof |
US8551858B2 (en) * | 2010-02-03 | 2013-10-08 | Spansion Llc | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory |
CN104253131A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
TWI668870B (en) * | 2016-12-15 | 2019-08-11 | 財團法人工業技術研究院 | Transistor device |
CN112002634A (en) * | 2020-07-23 | 2020-11-27 | 上海华力微电子有限公司 | Method for forming semiconductor structure |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0888285A (en) | 1994-09-17 | 1996-04-02 | Toshiba Corp | Non-voltage semiconductor memory device and manufacture thereof |
US5889304A (en) | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US6194285B1 (en) * | 1999-10-04 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Formation of shallow trench isolation (STI) |
US20020024092A1 (en) | 2000-08-11 | 2002-02-28 | Herbert Palm | Memory cell, memory cell arrangement and fabrication method |
US20030015752A1 (en) | 2000-08-11 | 2003-01-23 | Infineon Technologies Ag | Memory cell, memory cell configuration and fabrication method |
US20030111687A1 (en) | 2001-12-18 | 2003-06-19 | Josef Willer | Memory cell with trench transistor |
DE10162261A1 (en) | 2001-12-18 | 2003-07-10 | Infineon Technologies Ag | Memory cell with trench transistor has pn junctions defining channel region abutting walls of trench within curved area at base of trench |
US6781193B2 (en) * | 2001-08-09 | 2004-08-24 | Samsung Electronics Co., Ltd. | Non-volatile memory device having floating trap type memory cell and method of forming the same |
US6806163B2 (en) * | 2002-07-05 | 2004-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Ion implant method for topographic feature corner rounding |
-
2003
- 2003-07-23 DE DE10333549A patent/DE10333549B3/en not_active Expired - Fee Related
-
2004
- 2004-07-19 US US10/894,348 patent/US7087500B2/en not_active Expired - Fee Related
- 2004-07-23 CN CNB2004100545480A patent/CN100382323C/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0888285A (en) | 1994-09-17 | 1996-04-02 | Toshiba Corp | Non-voltage semiconductor memory device and manufacture thereof |
US5889304A (en) | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US6194285B1 (en) * | 1999-10-04 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Formation of shallow trench isolation (STI) |
US20020024092A1 (en) | 2000-08-11 | 2002-02-28 | Herbert Palm | Memory cell, memory cell arrangement and fabrication method |
DE10039441A1 (en) | 2000-08-11 | 2002-02-28 | Infineon Technologies Ag | Memory cell, memory cell arrangement and manufacturing method |
US20030015752A1 (en) | 2000-08-11 | 2003-01-23 | Infineon Technologies Ag | Memory cell, memory cell configuration and fabrication method |
US6781193B2 (en) * | 2001-08-09 | 2004-08-24 | Samsung Electronics Co., Ltd. | Non-volatile memory device having floating trap type memory cell and method of forming the same |
US20030111687A1 (en) | 2001-12-18 | 2003-06-19 | Josef Willer | Memory cell with trench transistor |
DE10162261A1 (en) | 2001-12-18 | 2003-07-10 | Infineon Technologies Ag | Memory cell with trench transistor has pn junctions defining channel region abutting walls of trench within curved area at base of trench |
US6806163B2 (en) * | 2002-07-05 | 2004-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Ion implant method for topographic feature corner rounding |
Non-Patent Citations (1)
Title |
---|
Park, et al., "Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers," 2003 Symposium on VLSI Technology Digest of Technical Papers, Jun. 10-12, 2003, pp. 135-136. |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008172200A (en) * | 2006-11-01 | 2008-07-24 | Macronix Internatl Co Ltd | Cylindrical channel charge trapping devices with substantially high coupling ratios |
US20090323411A1 (en) * | 2008-06-30 | 2009-12-31 | Qimonda Ag | Method including selective treatment of storage layer |
Also Published As
Publication number | Publication date |
---|---|
US20050045963A1 (en) | 2005-03-03 |
DE10333549B3 (en) | 2005-01-13 |
CN100382323C (en) | 2008-04-16 |
CN1577865A (en) | 2005-02-09 |
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