US7107439B2 - System and method of controlling software decompression through exceptions - Google Patents
System and method of controlling software decompression through exceptions Download PDFInfo
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- US7107439B2 US7107439B2 US09/925,314 US92531401A US7107439B2 US 7107439 B2 US7107439 B2 US 7107439B2 US 92531401 A US92531401 A US 92531401A US 7107439 B2 US7107439 B2 US 7107439B2
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- instruction
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- misaligned
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Definitions
- the present invention relates generally to the field of microprocessors and more particularly to the use of modified microprocessor instructions to transform stored processor code.
- Single chip computers are used in a wide range of applications where their small size and processing power are an advantage over conventional systems.
- the system designer must balance the space available on the silicon chip against the space required by the components necessary to provide the desired functionality. Adding components to the computer system such as additional memory or digital to analog converters will add functionality but also will take up valuable chip space. If the chip size is fixed and all available space is already being used, it will not be possible to add functionality without removing a component of equivalent size. Reducing the number of components reduces the required chip size but the number of components cannot be reduced below the minimum necessary for a functional computer.
- memory One component that must be included in single chip computers is memory.
- the amount of memory required is a function of the complexity and execution speed desired for planned computer software applications. Larger and more complex software programs usually require more memory to properly execute, and more memory usually increases program execution speed.
- One way to reduce the memory required in a single chip computer is to store the computer's software code in a compressed form. Compressing the code allows it to be stored in a smaller amount of memory and thereby reduces the computer system memory requirements.
- the processor cannot directly execute code stored in compressed form, a method of decompressing the code prior to its execution by the processor is needed.
- Existing techniques decompress large amounts of code such as a subroutine or large blocks of a main program before executing it. These techniques require the code decompression to occur either in the boot process or by some means external to the system processor. When the system processor is not used for decompression, additional hardware is necessary to accomplish the decompression. This makes it difficult and expensive to incorporate software compression in existing systems.
- a further disadvantage to these techniques is the additional memory required to store the larger volume of decompressed code while it is waiting to be executed by the processor. This disadvantage reduces the memory savings originally achieved by compressing the code.
- a method for transforming data into an instruction for execution by the central processing unit is triggered by first receiving a misaligned instruction address, generating a hardware exception and then, in response to the exception, executing an exception handling routine that transforms the data into an instruction for the central processing unit.
- An advantage of this invention is its use of existing exception handling hardware as a trigger for the data transformation. This allows the invention to be used in any system with exception handling hardware.
- Another advantage of this method is that hardware data transformation triggers, such as special interrupts, are not necessary.
- the present invention gives control of the data transformation trigger to the software programmer vice the hardware designer. This improves the portability of the invention between different hardware platforms.
- this invention provides a flexible software tool for optimizing the quantity of data or code decompressed to the amount of memory available to store that data or code. Precise control of the code and data decompression enables the programmer to ensure his program will execute in the available memory and while taking advantage of the storage space reduction allowed by compression.
- FIG. 1 illustrates a processor core embodiment of the invention.
- FIG. 2 illustrates a method for using an exception handling routine to transform data.
- FIG. 3 illustrates additional details of receiving a misaligned instruction, step 204 of FIG. 2 .
- FIG. 4 illustrates details of an exception handling transform, step 208 of FIG. 2 .
- FIG. 5 illustrates details of transforming data into an instruction, step 404 of FIG. 4 .
- FIG. 6 illustrates a computer system embodiment of the invention.
- Core 100 provides an example hardware environment for implementing an embodiment of the invention.
- a person skilled in the relevant art will recognize that the invention is not limited to application in this example environment. In fact, after reading the following description, it will become apparent to a person skilled in the relevant art how to implement the invention in alternative environments.
- Core 100 includes a program counter 112 coupled to a fetch unit 110 , a decode unit 106 , an execution unit 108 , exception logic 104 and memory 114 .
- core 100 operates as follows: fetch unit 110 retrieves data from an address in memory 114 specified by program counter 112 .
- Decode unit 106 decodes the data into an instruction and sends it to execution unit 108 where it is executed.
- program counter 112 Under certain conditions, such as a software error, program counter 112 will provide an address to fetch unit 110 which is not allowed or does not exist. When this occurs an exception is generated by decode logic 106 and the address that was used in the attempted fetch is sent to exception handling logic 104 . Exception handling logic 104 performs the operations necessary to provide the address of a valid instruction to program counter 112 so that fetch unit 110 can retrieve an instruction and continue program execution.
- the present invention uses exception logic 104 , and a set of instructions known as an exception handling routine, to perform intentional, rather than error corrective, actions in response to software commands.
- processor instructions are stored in compressed form in memory 114 . Before these instruction can be decoded by decode unit 106 they must be decompressed. The programmer responsible for implementing his program on a particular hardware suite determines the locations where compressed data will be stored in memory 114 . He then configures software instructions to generate a misaligned address whenever processor instructions, stored in compressed form, are required for execution. The misaligned address is sent from program counter 112 to fetch unit 110 where it causes an exception error. The exception error causes core 100 to suspend its previous operation, and send the misaligned address to exception logic 104 .
- Exception logic 104 sets up core 100 to execute a set of processor instructions stored in memory 114 . These instructions constitute the exception handling routine which functions to process the misaligned address and cause data to be transformed from a stored form into an executable instruction. The executable instruction is then stored in memory for use after the exception routine is complete.
- the memory address containing the data to be transformed is offset by a known amount from the misaligned address provided by the programmer. The programmer sets up the exception handling routine to add this offset to the misaligned address and retrieve the data stored at the offset location.
- Another embodiment of the invention uses a misaligned instruction address as the data to be transformed.
- a further embodiment uses the misaligned address and a programmer generated lookup table to generate the memory address containing the compressed data.
- the exception handling routine After retrieving the stored data, the exception handling routine applies a transformative algorithm to the data.
- the transformation is a decompression algorithm.
- the programmer can select a number of transforming algorithms for implementation in the exception handling routine. A partial list of these algorithms are: decrypting an encrypted instruction, decoding a macro instruction, transforming a non-native instruction into a processor executable instruction and executing a random number of processor instructions.
- the exception handling routine When the data transformation is complete, the exception handling routine provides the address of the first transformed instruction to program counter 112 , and returns core 100 to the pre-exception condition. Program counter 112 then provides fetch unit 110 with the address of the first transformed instruction which is decoded by decode unit 106 and executed by execution unit 108 . Program execution continues as directed by the software program being executed.
- FIG. 2 illustrates a method of triggering data transformation according to the present invention.
- a misaligned instruction address is received by fetch unit 110 .
- the misaligned instruction address causes an exception.
- Exception logic 104 then executes an exception handling routine to transform the data in a step 208 .
- FIG. 3 describes step 204 in further detail.
- a “jump to” instruction is executed causing fetch unit 110 to attempt to retrieve the next processor instruction from a specified “jump to” address.
- the software programmer designates the jump address as an “odd” address, defined as an address with a least significant bit value of one.
- a core 100 with a 16 bit (4 bytes) address bus stores instructions at even byte boundaries in memory.
- a misaligned instruction address is defined as an “odd” address. Therefore, fetch unit 110 receives a misaligned instruction address in a step 204 . It will be apparent to a person skilled in the relevant art that other programming techniques can be used to cause the processor to receive a misaligned instruction address.
- FIG. 4 describes step 208 in further detail.
- the misaligned data is transformed into at least one instruction. Step 404 continues until all data specified by the programmer is transformed.
- the first transformed instruction is stored at a first address in memory 114 in a step 406 .
- the first address in memory 114 where the transformed instructions are stored, is then loaded into program counter 112 in a step 408 .
- a return from exception is executed, in a step 410 , to return core 100 to its pre-exception mode of operation.
- Fetch unit 110 then retrieves a transformed instruction (starting with the address indicated by program counter 112 ) for execution as indicated by step 412 .
- Step 404 is described in further detail with reference to FIG. 5 .
- a step 502 an offset value is added to the misaligned instruction address.
- Data stored at the address defined by the addition of the offset value and the misaligned instruction address is retrieved in a step 503 .
- a transformative algorithm is then applied to the retrieved data in a step 504 .
- the result of the transformation is designated a processor instruction in a step 506 .
- an exception handling routine When an exception is triggered the core 100 automatically executes a set of instructions known as an exception handling routine.
- An example of the software code embodying an exception handling routine is provided below. Additional information on programming exception handling routines is found in, Dominic Sweetman, See MIPS Run (1999), which is incorporated herein by reference in its entirety. Although this reference is for a particular hardware set, persons of skill in the art will understand how to implement the present invention on other hardware platforms.
- the example routine is written in a C language format pseudocode. This code is for illustrating the basic operation of an exception handling routine and cannot be compiled.
- the hardware exception logic transfers program execution to a preprogrammed address where a software exception handler is stored.
- the exception handler is called Exception_handler.
- the bad address is data that caused a hardware exception condition in the core 100.
- */ Execption_handler( ) ⁇ /* Check to see if this is an exception for a bad address. */ if (conduct hardware dependent check for bad address); ⁇ /*
- the hardware exception logic passes the bad address to the software exception handler (the detailed method is hardware dependent).
- the software exception handler uses the bad address to determine if the exception is a decode trigger or an actual bad address.
- the hardware may have a list of valid addresses that are acceptable or a range of addresses that are acceptable or just check to see if it is a odd address (lowest order address bit set). */ if (valid decode address); ⁇ /* If the software exception handler determines the cause of the exception is a purposeful decode trigger, it may use the bad address to determine where the encoded data is stored and decode that encoded data into a location in memory from which it can later be executed. If a transformation of the data is desired, a function, decode, is called to perform that function. The decode function will decide when to stop decoding. For example if this were a program instruction, being decoded, a good stopping point would be the next branch instruction.
- decode_return This value could represent an address of a decoded section of code that the core 100 can use to continue execution after it leaves the decode function or as an address where the newly decoded data is stored.
- */ decode_return decode(bad_address) /* What the software exception handler does depends on what was decoded. For this example, if the decoder decoded compressed instructions and the decode_return value was the address of the first instruction of a block of instructions that were decoded. The decode function will need to “fix” the address so the core 100 will know where to begin execution after the exception handling function finishes.
- a program counter 112 which is the address the core 100 uses to fetch the current instruction or the next instruction that will be executed.
- the program counter 112 may still contain the bad address that caused the exception. This address needs to be changed to the address of the decompressed code so the core 100 will begin executing the decompressed code.
- Computer system 600 includes one or more processors, such as processor 605 .
- Processor 605 is connected to a communication bus 606 .
- Computer system 600 also includes exception handling hardware 604 , a main memory 614 , preferably random access memory (RAM), and may also include a secondary memory 610 .
- the secondary memory 610 may include, for example, a hard disk drive 612 and/or a removable storage drive 613 , representing a floppy disk drive, a magnetic tape drive, an optical disk drive, etc.
- the removable storage drive 613 reads from and/or writes to a removable storage unit 618 in a well-known manner.
- Removable storage unit 618 represents a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive 613 .
- the removable storage unit 618 includes a computer usable storage medium having stored therein computer software and/or data.
- Secondary memory 610 may include similar means for allowing computer programs or other instructions to be loaded into computer system 600 .
- Such means may include, for example, a removable storage unit 622 and an interface 620 .
- Examples of such may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 622 and interfaces 620 which allow software and data to be transferred from the removable storage unit 622 to computer system 600 .
- Computer system 600 may also include a communications interface 624 .
- Communications interface 624 allows software and data to be transferred between computer system 600 and external devices. Examples of communications interface 624 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, etc.
- Software and data transferred via communications interface 624 are in the form of signals 628 which may be electronic, electromagnetic, optical or other signals capable of being received by communications interface 624 . These signals 628 are provided to communications interface 624 via a communications path (i.e., channel) 626 .
- This channel 626 carries signals 628 and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link, and other communications channels.
- Computer programs are stored in main memory 614 and/or secondary memory 610 . Computer programs may also be received via communications interface 624 . Such computer programs, when executed, enable the computer system 600 to perform the features of the present invention as discussed herein. In particular, the computer programs, when executed, enable the processor 605 to perform the features of the present invention. Accordingly, such computer programs represent controllers of the computer system 600 .
- the software may be stored as computer program product and loaded into computer system 600 using removable storage drive 613 , hard drive 612 or communications interface 624 .
- the control logic when executed by the processor 605 , causes the processor 605 to perform the functions of the invention as described herein.
- the invention is implemented primarily in hardware using, for example, hardware components such as application specific integrated circuits (ASICs).
- ASICs application specific integrated circuits
- the invention is implemented using a combination of hardware and software.
- the invention can be implemented in software that describes hardware and is disposed, for example, in a computer usable (i.e., readable) medium configured to store the software (i.e., a computer readable program code).
- the program code causes the enablement of the functions or fabrication (or both) of the systems and techniques described above. This may be accomplished, for example, through the use of general programming language (e.g., C, C++), hardware description language (HDL) including Verilog HDL, VHDL and so on, or other available programming and/or circuit (i.e., schematic) capture tools.
- the program code may be disposed in any known computer medium including semiconductor, magnetic disk, optical disc (e.g., CD-ROM, DVD-ROM) and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium).
- a computer usable (e.g., readable) transmission medium e.g., carrier wave or any other medium including digital, optical, or analog-based medium.
- the code can be transmitted over communication networks including the Internet and intranets.
Abstract
Description
/* The hardware exception logic transfers program execution to a preprogrammed | ||
address where a software exception handler is stored. For this example the | ||
exception handler is called Exception_handler. The bad address is data that caused | ||
a hardware exception condition in the |
||
*/ | ||
Execption_handler( ) | ||
{ |
/* Check to see if this is an exception for a bad address. | |
*/ | |
if (conduct hardware dependent check for bad address); | |
{ |
/* | |
The hardware exception logic passes the bad address to the | |
software exception handler (the detailed method is hardware | |
dependent). The software exception handler uses the bad address | |
to determine if the exception is a decode trigger or an actual bad | |
address. To do this the hardware may have a list of valid addresses | |
that are acceptable or a range of addresses that are acceptable or just | |
check to see if it is a odd address (lowest order address bit set). | |
*/ | |
if (valid decode address); | |
{ |
/* | |
If the software exception handler determines the cause of | |
the exception is a purposeful decode trigger, it may use | |
the bad address to determine where the encoded data is | |
stored and decode that encoded data into a location in | |
memory from which it can later be executed. If a | |
transformation of the data is desired, a function, decode, | |
is called to perform that function. The decode function will | |
decide when to stop decoding. For example if this were a | |
program instruction, being decoded, a good stopping point | |
would be the next branch instruction. The decode function | |
will return a value, decode_return. This value could | |
represent an address of a decoded section of code that the | |
|
|
decode function or as an address where the newly decoded | |
data is stored. | |
*/ | |
decode_return = decode(bad_address) | |
/* | |
What the software exception handler does depends on | |
what was decoded. For this example, if the decoder | |
decoded compressed instructions and the decode_return | |
value was the address of the first instruction of a block of | |
instructions that were decoded. The decode function will | |
need to “fix” the address so the core 100 will know where | |
to begin execution after the exception handling function | |
finishes. In |
|
|
|
the core 100 uses to fetch the current instruction or the | |
next instruction that will be executed. The | |
counter | |
112 may still contain the bad address that caused | |
the exception. This address needs to be changed to the | |
address of the decompressed code so the core 100 will | |
begin executing the decompressed code. | |
*/ | |
fix_program_counter(decode_return); |
} | |
else | |
{ |
/* | |
If this was not a valid decode address or exception then | |
the exception function will continue here with logic to | |
process the exception. | |
/* |
} |
} | |
else | |
{ |
/* | |
Check for other exceptions | |
*/ |
} | |
/* | |
At this point the exception function will do any addition housekeeping | |
that is need for the |
|
*/ | |
return; |
} | ||
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US20070294599A1 (en) * | 2006-05-30 | 2007-12-20 | Mattias Edlund | Method for patching a read-only memory and a data processing system comprising a means of patching the read-only memory based on patch contexts |
US20100257338A1 (en) * | 2009-04-07 | 2010-10-07 | Spracklen Lawrence A | Methods and mechanisms to support multiple features for a number of opcodes |
US11086631B2 (en) * | 2018-11-30 | 2021-08-10 | Western Digital Technologies, Inc. | Illegal instruction exception handling |
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EP1622009A1 (en) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM architecture and systems |
US7313566B1 (en) * | 2004-12-23 | 2007-12-25 | Sun Microsystems, Inc. | Method and apparatus for isolating selected heap objects using a faulting address trap |
US20070005625A1 (en) * | 2005-07-01 | 2007-01-04 | Nec Laboratories America, Inc. | Storage architecture for embedded systems |
Citations (101)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3543245A (en) | 1968-02-29 | 1970-11-24 | Ferranti Ltd | Computer systems |
US3631405A (en) | 1969-11-12 | 1971-12-28 | Honeywell Inc | Sharing of microprograms between processors |
US3794980A (en) | 1971-04-21 | 1974-02-26 | Cogar Corp | Apparatus and method for controlling sequential execution of instructions and nesting of subroutines in a data processor |
US3811114A (en) | 1973-01-11 | 1974-05-14 | Honeywell Inf Systems | Data processing system having an improved overlap instruction fetch and instruction execution feature |
US3840861A (en) | 1972-10-30 | 1974-10-08 | Amdahl Corp | Data processing system having an instruction pipeline for concurrently processing a plurality of instructions |
US3949372A (en) | 1973-10-10 | 1976-04-06 | Honeywell Information Systems, Inc. | System for extending the interior decor of a microprogrammed computer |
US3983541A (en) | 1969-05-19 | 1976-09-28 | Burroughs Corporation | Polymorphic programmable units employing plural levels of phased sub-instruction sets |
US4068303A (en) | 1975-03-24 | 1978-01-10 | Hitachi, Ltd. | Address translation managing system with translation pair purging |
US4077058A (en) | 1973-11-30 | 1978-02-28 | Compagnie Honeywell Bull | Method and apparatus for executing an extended decor instruction |
US4084235A (en) | 1975-04-14 | 1978-04-11 | Honeywell Information Systems Inc. | Emulation apparatus |
US4110822A (en) | 1975-03-26 | 1978-08-29 | Honeywell Information Systems, Inc. | Instruction look ahead having prefetch concurrency and pipeline features |
US4149244A (en) | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
US4229790A (en) | 1978-10-16 | 1980-10-21 | Denelcor, Inc. | Concurrent task and instruction processor and method |
US4274138A (en) | 1976-07-31 | 1981-06-16 | Tokyo Shibaura Denki Kabushiki Kaisha | Stored program control system with switching between instruction word systems |
US4285040A (en) | 1977-11-04 | 1981-08-18 | Sperry Corporation | Dual mode virtual-to-real address translation mechanism |
US4295193A (en) | 1979-06-29 | 1981-10-13 | International Business Machines Corporation | Machine for multiple instruction execution |
US4432056A (en) | 1979-06-05 | 1984-02-14 | Canon Kabushiki Kaisha | Programmable electronic computer |
US4456954A (en) | 1981-06-15 | 1984-06-26 | International Business Machines Corporation | Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations |
US4463342A (en) | 1979-06-14 | 1984-07-31 | International Business Machines Corporation | Method and means for carry-over control in the high order to low order pairwise combining of digits of a decodable set of relatively shifted finite number strings |
US4467409A (en) | 1980-08-05 | 1984-08-21 | Burroughs Corporation | Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations |
US4488143A (en) | 1981-08-07 | 1984-12-11 | International Business Machines Corporation | Fixed rate run length limited (RLL) code string generation using length oriented arithmetic code data string expansion and data string recovery using arithmetic code compression of RLL code strings |
US4507728A (en) | 1981-03-20 | 1985-03-26 | Fujitsu Limited | Data processing system for parallel processing of different instructions |
US4575797A (en) | 1981-05-22 | 1986-03-11 | Data General Corporation | Digital data processing system incorporating object-based addressing and capable of executing instructions belonging to several instruction sets |
US4603399A (en) | 1983-12-27 | 1986-07-29 | International Business Machines Corporation | Data processing apparatus for address substitution |
US4685080A (en) | 1982-02-22 | 1987-08-04 | International Business Machines Corp. | Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords |
US4724517A (en) | 1982-11-26 | 1988-02-09 | Inmos Limited | Microcomputer with prefixing functions |
US4727480A (en) | 1984-07-09 | 1988-02-23 | Wang Laboratories, Inc. | Emulation of a data processing system |
US4774652A (en) | 1987-02-18 | 1988-09-27 | Apple Computer, Inc. | Memory mapping unit for decoding address signals |
US4777594A (en) | 1983-07-11 | 1988-10-11 | Prime Computer, Inc. | Data processing apparatus and method employing instruction flow prediction |
US4782443A (en) | 1985-11-13 | 1988-11-01 | Fujitsu Limited | Main storage control system for virtual computing function system with plural address modes in main storage access operations |
US4782441A (en) | 1985-06-14 | 1988-11-01 | Hitachi, Ltd. | Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions |
US4799242A (en) | 1987-08-24 | 1989-01-17 | International Business Machines Corporation | Multi-mode dynamic code assignment for data compression |
US4802119A (en) | 1987-03-17 | 1989-01-31 | Motorola, Inc. | Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory |
US4814975A (en) | 1983-09-08 | 1989-03-21 | Hitachi, Ltd. | Virtual machine system and method for controlling machines of different architectures |
US4835734A (en) | 1986-04-09 | 1989-05-30 | Hitachi, Ltd. | Address translation apparatus |
US4839797A (en) | 1984-07-25 | 1989-06-13 | Nec Corporation | Microprocessor compatible with any software represented by different types of instruction formats |
US4868740A (en) | 1986-06-04 | 1989-09-19 | Hitachi, Ltd. | System for processing data with multiple virtual address and data word lengths |
US4876639A (en) | 1983-09-20 | 1989-10-24 | Mensch Jr William D | Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit |
US4992934A (en) | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US5031096A (en) | 1988-06-30 | 1991-07-09 | International Business Machines Corporation | Method and apparatus for compressing the execution time of an instruction stream executing in a pipelined processor |
US5091846A (en) | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5115500A (en) | 1988-01-11 | 1992-05-19 | International Business Machines Corporation | Plural incompatible instruction format decode method and apparatus |
US5132898A (en) | 1987-09-30 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | System for processing data having different formats |
US5193158A (en) | 1988-10-19 | 1993-03-09 | Hewlett-Packard Company | Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths |
US5241679A (en) | 1989-07-05 | 1993-08-31 | Hitachi Ltd. | Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register |
US5241636A (en) | 1990-02-14 | 1993-08-31 | Intel Corporation | Method for parallel instruction execution in a computer |
US5255379A (en) | 1990-12-28 | 1993-10-19 | Sun Microsystems, Inc. | Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor |
US5280593A (en) | 1991-04-24 | 1994-01-18 | International Business Machines Corporation | Computer system permitting switching between architected and interpretation instructions in a pipeline by enabling pipeline drain |
US5307504A (en) | 1991-03-07 | 1994-04-26 | Digital Equipment Corporation | System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events |
US5327566A (en) | 1991-07-12 | 1994-07-05 | Hewlett Packard Company | Stage saving and restoring hardware mechanism |
US5335331A (en) | 1990-07-13 | 1994-08-02 | Kabushiki Kaisha Toshiba | Microcomputer using specific instruction bit and mode switch signal for distinguishing and executing different groups of instructions in plural operating modes |
US5339422A (en) | 1991-03-07 | 1994-08-16 | Digital Equipment Corporation | System and method for jacketing cross-domain calls in a multi-code execution and debugging system within a multi-architecture environment |
US5355460A (en) | 1990-06-26 | 1994-10-11 | International Business Machines Corporation | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution |
US5420992A (en) | 1991-03-11 | 1995-05-30 | Silicon Graphics, Inc. | Backward-compatible computer architecture with extended word size and address space |
US5430862A (en) | 1990-06-29 | 1995-07-04 | Bull Hn Information Systems Inc. | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution |
US5438672A (en) | 1990-12-18 | 1995-08-01 | National Semiconductor Corporation | Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus |
US5438668A (en) | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
US5463700A (en) | 1987-01-14 | 1995-10-31 | Canon Kabushiki Kaisha | Image processing apparatus with compression error detector |
US5467134A (en) | 1992-12-22 | 1995-11-14 | Microsoft Corporation | Method and system for compressing video data |
US5481693A (en) | 1994-07-20 | 1996-01-02 | Exponential Technology, Inc. | Shared register architecture for a dual-instruction-set CPU |
US5481684A (en) | 1994-01-11 | 1996-01-02 | Exponential Technology, Inc. | Emulating operating system calls in an alternate instruction set using a modified code segment descriptor |
US5506974A (en) | 1990-03-23 | 1996-04-09 | Unisys Corporation | Method and means for concatenating multiple instructions |
US5517664A (en) | 1986-04-14 | 1996-05-14 | Hitachi, Ltd. | RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing |
US5519873A (en) | 1990-08-31 | 1996-05-21 | International Business Machines Corporation | Apparatus for switching digital command execution between a general purpose microprocessor and dedicted execution logic |
US5522086A (en) | 1993-10-29 | 1996-05-28 | Sierra Semiconductor Canada, Inc. | Software configurable ISA bus card interface with security access read and write sequence to upper data bits at addresses used by a game device |
US5542059A (en) | 1994-01-11 | 1996-07-30 | Exponential Technology, Inc. | Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order |
US5568646A (en) | 1994-05-03 | 1996-10-22 | Advanced Risc Machines Limited | Multiple instruction set mapping |
US5574928A (en) | 1993-10-29 | 1996-11-12 | Advanced Micro Devices, Inc. | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
US5574927A (en) | 1994-03-25 | 1996-11-12 | International Meta Systems, Inc. | RISC architecture computer configured for emulation of the instruction set of a target computer |
US5574873A (en) | 1993-05-07 | 1996-11-12 | Apple Computer, Inc. | Decoding guest instruction to directly access emulation routines that emulate the guest instructions |
US5574887A (en) | 1993-09-20 | 1996-11-12 | Apple Computer, Inc. | Apparatus and method for emulation routine pointer prefetch |
US5577200A (en) | 1994-02-28 | 1996-11-19 | Intel Corporation | Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system |
US5598546A (en) | 1994-08-31 | 1997-01-28 | Exponential Technology, Inc. | Dual-architecture super-scalar pipeline |
US5619665A (en) | 1995-04-13 | 1997-04-08 | Intrnational Business Machines Corporation | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture |
US5632024A (en) | 1993-06-08 | 1997-05-20 | Hitachi, Ltd. | Microcomputer executing compressed program and generating compressed branch addresses |
US5638525A (en) | 1995-02-10 | 1997-06-10 | Intel Corporation | Processor capable of executing programs that contain RISC and CISC instructions |
US5652852A (en) | 1993-10-21 | 1997-07-29 | Canon Kabushiki Kaisha | Processor for discriminating between compressed and non-compressed program code, with prefetching, decoding and execution of compressed code in parallel with the decoding, with modified target branch addresses accommodated at run time |
US5685009A (en) | 1994-07-20 | 1997-11-04 | Exponential Technology, Inc. | Shared floating-point registers and register port-pairing in a dual-architecture CPU |
US5732234A (en) | 1990-05-04 | 1998-03-24 | International Business Machines Corporation | System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories |
US5740461A (en) | 1994-05-03 | 1998-04-14 | Advanced Risc Machines Limited | Data processing with multiple instruction sets |
US5745058A (en) | 1996-10-21 | 1998-04-28 | International Business Machines Corporation | Method and system for compressing microcode to be executed within a data processing system |
US5751932A (en) * | 1992-12-17 | 1998-05-12 | Tandem Computers Incorporated | Fail-fast, fail-functional, fault-tolerant multiprocessor system |
US5758115A (en) | 1994-06-10 | 1998-05-26 | Advanced Risc Machines Limited | Interoperability with multiple instruction sets |
US5764994A (en) | 1996-09-16 | 1998-06-09 | International Business Machines Corporation | Method and system for compressing compiled microcode to be executed within a data processing system |
US5774686A (en) | 1995-06-07 | 1998-06-30 | Intel Corporation | Method and apparatus for providing two system architectures in a processor |
US5781750A (en) | 1994-01-11 | 1998-07-14 | Exponential Technology, Inc. | Dual-instruction-set architecture CPU with hidden software emulation mode |
US5794010A (en) | 1996-06-10 | 1998-08-11 | Lsi Logic Corporation | Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor |
US5796973A (en) | 1993-10-29 | 1998-08-18 | Advanced Micro Devices, Inc. | Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions |
US5829012A (en) | 1996-04-19 | 1998-10-27 | Unisys Corporation | System for programmably providing modified read signals within a ROM-based memory |
US5828859A (en) | 1991-09-30 | 1998-10-27 | Fujitsu Limited | Method and apparatus for setting the status mode of a central processing unit |
US5854913A (en) | 1995-06-07 | 1998-12-29 | International Business Machines Corporation | Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures |
US5867682A (en) | 1993-10-29 | 1999-02-02 | Advanced Micro Devices, Inc. | High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations |
US5867681A (en) | 1996-05-23 | 1999-02-02 | Lsi Logic Corporation | Microprocessor having register dependent immediate decompression |
US5896519A (en) | 1996-06-10 | 1999-04-20 | Lsi Logic Corporation | Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions |
US5905893A (en) | 1996-06-10 | 1999-05-18 | Lsi Logic Corporation | Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set |
US5948112A (en) * | 1996-03-19 | 1999-09-07 | Kabushiki Kaisha Toshiba | Method and apparatus for recovering from software faults |
US5954830A (en) | 1997-04-08 | 1999-09-21 | International Business Machines Corporation | Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs |
US5982459A (en) * | 1995-05-31 | 1999-11-09 | 8×8, Inc. | Integrated multimedia communications processor and codec |
US6012138A (en) | 1997-12-19 | 2000-01-04 | Lsi Logic Corporation | Dynamically variable length CPU pipeline for efficiently executing two instruction sets |
US6212630B1 (en) | 1997-12-10 | 2001-04-03 | Matsushita Electric Industrial Co., Ltd. | Microprocessor for overlapping stack frame allocation with saving of subroutine data into stack area |
US20020144041A1 (en) * | 2001-03-29 | 2002-10-03 | Revilla Juan G. | Early exception detection |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4707728A (en) * | 1982-02-24 | 1987-11-17 | Rca Corporation | Compatible HDTV with increased vertical and horizontal resolution |
JP2810068B2 (en) * | 1988-11-11 | 1998-10-15 | 株式会社日立製作所 | Processor system, computer system, and instruction processing method |
CA2016068C (en) * | 1989-05-24 | 2000-04-04 | Robert W. Horst | Multiple instruction issue computer architecture |
JP2984463B2 (en) * | 1991-06-24 | 1999-11-29 | 株式会社日立製作所 | Microcomputer |
US5539911A (en) * | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US6631460B1 (en) * | 2000-04-27 | 2003-10-07 | Institute For The Development Of Emerging Architectures, L.L.C. | Advanced load address table entry invalidation based on register address wraparound |
-
2001
- 2001-08-10 US US09/925,314 patent/US7107439B2/en not_active Expired - Lifetime
Patent Citations (104)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3543245A (en) | 1968-02-29 | 1970-11-24 | Ferranti Ltd | Computer systems |
US3983541A (en) | 1969-05-19 | 1976-09-28 | Burroughs Corporation | Polymorphic programmable units employing plural levels of phased sub-instruction sets |
US3631405A (en) | 1969-11-12 | 1971-12-28 | Honeywell Inc | Sharing of microprograms between processors |
US3794980A (en) | 1971-04-21 | 1974-02-26 | Cogar Corp | Apparatus and method for controlling sequential execution of instructions and nesting of subroutines in a data processor |
US3840861A (en) | 1972-10-30 | 1974-10-08 | Amdahl Corp | Data processing system having an instruction pipeline for concurrently processing a plurality of instructions |
US3811114A (en) | 1973-01-11 | 1974-05-14 | Honeywell Inf Systems | Data processing system having an improved overlap instruction fetch and instruction execution feature |
US3949372A (en) | 1973-10-10 | 1976-04-06 | Honeywell Information Systems, Inc. | System for extending the interior decor of a microprogrammed computer |
US4077058A (en) | 1973-11-30 | 1978-02-28 | Compagnie Honeywell Bull | Method and apparatus for executing an extended decor instruction |
US4068303A (en) | 1975-03-24 | 1978-01-10 | Hitachi, Ltd. | Address translation managing system with translation pair purging |
US4110822A (en) | 1975-03-26 | 1978-08-29 | Honeywell Information Systems, Inc. | Instruction look ahead having prefetch concurrency and pipeline features |
US4084235A (en) | 1975-04-14 | 1978-04-11 | Honeywell Information Systems Inc. | Emulation apparatus |
US4149244A (en) | 1976-06-07 | 1979-04-10 | Amdahl Corporation | Data processing system including a program-executing secondary system controlling a program-executing primary system |
US4274138A (en) | 1976-07-31 | 1981-06-16 | Tokyo Shibaura Denki Kabushiki Kaisha | Stored program control system with switching between instruction word systems |
US4285040A (en) | 1977-11-04 | 1981-08-18 | Sperry Corporation | Dual mode virtual-to-real address translation mechanism |
US4229790A (en) | 1978-10-16 | 1980-10-21 | Denelcor, Inc. | Concurrent task and instruction processor and method |
US4432056A (en) | 1979-06-05 | 1984-02-14 | Canon Kabushiki Kaisha | Programmable electronic computer |
US4463342A (en) | 1979-06-14 | 1984-07-31 | International Business Machines Corporation | Method and means for carry-over control in the high order to low order pairwise combining of digits of a decodable set of relatively shifted finite number strings |
US4295193A (en) | 1979-06-29 | 1981-10-13 | International Business Machines Corporation | Machine for multiple instruction execution |
US4467409A (en) | 1980-08-05 | 1984-08-21 | Burroughs Corporation | Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations |
US4507728A (en) | 1981-03-20 | 1985-03-26 | Fujitsu Limited | Data processing system for parallel processing of different instructions |
US4575797A (en) | 1981-05-22 | 1986-03-11 | Data General Corporation | Digital data processing system incorporating object-based addressing and capable of executing instructions belonging to several instruction sets |
US4456954A (en) | 1981-06-15 | 1984-06-26 | International Business Machines Corporation | Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations |
US4488143A (en) | 1981-08-07 | 1984-12-11 | International Business Machines Corporation | Fixed rate run length limited (RLL) code string generation using length oriented arithmetic code data string expansion and data string recovery using arithmetic code compression of RLL code strings |
US4685080A (en) | 1982-02-22 | 1987-08-04 | International Business Machines Corp. | Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords |
US4724517A (en) | 1982-11-26 | 1988-02-09 | Inmos Limited | Microcomputer with prefixing functions |
US4777594A (en) | 1983-07-11 | 1988-10-11 | Prime Computer, Inc. | Data processing apparatus and method employing instruction flow prediction |
US4814975A (en) | 1983-09-08 | 1989-03-21 | Hitachi, Ltd. | Virtual machine system and method for controlling machines of different architectures |
US4876639A (en) | 1983-09-20 | 1989-10-24 | Mensch Jr William D | Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit |
US4603399A (en) | 1983-12-27 | 1986-07-29 | International Business Machines Corporation | Data processing apparatus for address substitution |
US4727480A (en) | 1984-07-09 | 1988-02-23 | Wang Laboratories, Inc. | Emulation of a data processing system |
US4839797A (en) | 1984-07-25 | 1989-06-13 | Nec Corporation | Microprocessor compatible with any software represented by different types of instruction formats |
US4782441A (en) | 1985-06-14 | 1988-11-01 | Hitachi, Ltd. | Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions |
US4782443A (en) | 1985-11-13 | 1988-11-01 | Fujitsu Limited | Main storage control system for virtual computing function system with plural address modes in main storage access operations |
US4835734A (en) | 1986-04-09 | 1989-05-30 | Hitachi, Ltd. | Address translation apparatus |
US5517664A (en) | 1986-04-14 | 1996-05-14 | Hitachi, Ltd. | RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing |
US4868740A (en) | 1986-06-04 | 1989-09-19 | Hitachi, Ltd. | System for processing data with multiple virtual address and data word lengths |
US5091846A (en) | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US4992934A (en) | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US5463700A (en) | 1987-01-14 | 1995-10-31 | Canon Kabushiki Kaisha | Image processing apparatus with compression error detector |
US4774652A (en) | 1987-02-18 | 1988-09-27 | Apple Computer, Inc. | Memory mapping unit for decoding address signals |
US4802119A (en) | 1987-03-17 | 1989-01-31 | Motorola, Inc. | Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory |
US4799242A (en) | 1987-08-24 | 1989-01-17 | International Business Machines Corporation | Multi-mode dynamic code assignment for data compression |
US5132898A (en) | 1987-09-30 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | System for processing data having different formats |
US5115500A (en) | 1988-01-11 | 1992-05-19 | International Business Machines Corporation | Plural incompatible instruction format decode method and apparatus |
US5031096A (en) | 1988-06-30 | 1991-07-09 | International Business Machines Corporation | Method and apparatus for compressing the execution time of an instruction stream executing in a pipelined processor |
US5193158A (en) | 1988-10-19 | 1993-03-09 | Hewlett-Packard Company | Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths |
US5241679A (en) | 1989-07-05 | 1993-08-31 | Hitachi Ltd. | Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register |
US5241636A (en) | 1990-02-14 | 1993-08-31 | Intel Corporation | Method for parallel instruction execution in a computer |
US5506974A (en) | 1990-03-23 | 1996-04-09 | Unisys Corporation | Method and means for concatenating multiple instructions |
US5732234A (en) | 1990-05-04 | 1998-03-24 | International Business Machines Corporation | System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories |
US5355460A (en) | 1990-06-26 | 1994-10-11 | International Business Machines Corporation | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution |
US5430862A (en) | 1990-06-29 | 1995-07-04 | Bull Hn Information Systems Inc. | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution |
US5335331A (en) | 1990-07-13 | 1994-08-02 | Kabushiki Kaisha Toshiba | Microcomputer using specific instruction bit and mode switch signal for distinguishing and executing different groups of instructions in plural operating modes |
US5519873A (en) | 1990-08-31 | 1996-05-21 | International Business Machines Corporation | Apparatus for switching digital command execution between a general purpose microprocessor and dedicted execution logic |
US5438672A (en) | 1990-12-18 | 1995-08-01 | National Semiconductor Corporation | Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus |
US5255379A (en) | 1990-12-28 | 1993-10-19 | Sun Microsystems, Inc. | Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor |
US5339422A (en) | 1991-03-07 | 1994-08-16 | Digital Equipment Corporation | System and method for jacketing cross-domain calls in a multi-code execution and debugging system within a multi-architecture environment |
US5307504A (en) | 1991-03-07 | 1994-04-26 | Digital Equipment Corporation | System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events |
US5420992A (en) | 1991-03-11 | 1995-05-30 | Silicon Graphics, Inc. | Backward-compatible computer architecture with extended word size and address space |
US5280593A (en) | 1991-04-24 | 1994-01-18 | International Business Machines Corporation | Computer system permitting switching between architected and interpretation instructions in a pipeline by enabling pipeline drain |
US5327566A (en) | 1991-07-12 | 1994-07-05 | Hewlett Packard Company | Stage saving and restoring hardware mechanism |
US5828859A (en) | 1991-09-30 | 1998-10-27 | Fujitsu Limited | Method and apparatus for setting the status mode of a central processing unit |
US5619666A (en) | 1992-03-31 | 1997-04-08 | Seiko Epson Corporation | System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor |
US5546552A (en) * | 1992-03-31 | 1996-08-13 | Seiko Epson Corporation | Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor |
US5438668A (en) | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
US5751932A (en) * | 1992-12-17 | 1998-05-12 | Tandem Computers Incorporated | Fail-fast, fail-functional, fault-tolerant multiprocessor system |
US5467134A (en) | 1992-12-22 | 1995-11-14 | Microsoft Corporation | Method and system for compressing video data |
US5574873A (en) | 1993-05-07 | 1996-11-12 | Apple Computer, Inc. | Decoding guest instruction to directly access emulation routines that emulate the guest instructions |
US5632024A (en) | 1993-06-08 | 1997-05-20 | Hitachi, Ltd. | Microcomputer executing compressed program and generating compressed branch addresses |
US5574887A (en) | 1993-09-20 | 1996-11-12 | Apple Computer, Inc. | Apparatus and method for emulation routine pointer prefetch |
US5652852A (en) | 1993-10-21 | 1997-07-29 | Canon Kabushiki Kaisha | Processor for discriminating between compressed and non-compressed program code, with prefetching, decoding and execution of compressed code in parallel with the decoding, with modified target branch addresses accommodated at run time |
US5574928A (en) | 1993-10-29 | 1996-11-12 | Advanced Micro Devices, Inc. | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
US5867682A (en) | 1993-10-29 | 1999-02-02 | Advanced Micro Devices, Inc. | High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations |
US5796973A (en) | 1993-10-29 | 1998-08-18 | Advanced Micro Devices, Inc. | Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions |
US5522086A (en) | 1993-10-29 | 1996-05-28 | Sierra Semiconductor Canada, Inc. | Software configurable ISA bus card interface with security access read and write sequence to upper data bits at addresses used by a game device |
US5481684A (en) | 1994-01-11 | 1996-01-02 | Exponential Technology, Inc. | Emulating operating system calls in an alternate instruction set using a modified code segment descriptor |
US5542059A (en) | 1994-01-11 | 1996-07-30 | Exponential Technology, Inc. | Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order |
US5781750A (en) | 1994-01-11 | 1998-07-14 | Exponential Technology, Inc. | Dual-instruction-set architecture CPU with hidden software emulation mode |
US5577200A (en) | 1994-02-28 | 1996-11-19 | Intel Corporation | Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system |
US5574927A (en) | 1994-03-25 | 1996-11-12 | International Meta Systems, Inc. | RISC architecture computer configured for emulation of the instruction set of a target computer |
US5568646A (en) | 1994-05-03 | 1996-10-22 | Advanced Risc Machines Limited | Multiple instruction set mapping |
US5740461A (en) | 1994-05-03 | 1998-04-14 | Advanced Risc Machines Limited | Data processing with multiple instruction sets |
US6021265A (en) | 1994-06-10 | 2000-02-01 | Arm Limited | Interoperability with multiple instruction sets |
US5758115A (en) | 1994-06-10 | 1998-05-26 | Advanced Risc Machines Limited | Interoperability with multiple instruction sets |
US5685009A (en) | 1994-07-20 | 1997-11-04 | Exponential Technology, Inc. | Shared floating-point registers and register port-pairing in a dual-architecture CPU |
US5481693A (en) | 1994-07-20 | 1996-01-02 | Exponential Technology, Inc. | Shared register architecture for a dual-instruction-set CPU |
US5598546A (en) | 1994-08-31 | 1997-01-28 | Exponential Technology, Inc. | Dual-architecture super-scalar pipeline |
US5638525A (en) | 1995-02-10 | 1997-06-10 | Intel Corporation | Processor capable of executing programs that contain RISC and CISC instructions |
US5619665A (en) | 1995-04-13 | 1997-04-08 | Intrnational Business Machines Corporation | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture |
US5982459A (en) * | 1995-05-31 | 1999-11-09 | 8×8, Inc. | Integrated multimedia communications processor and codec |
US5774686A (en) | 1995-06-07 | 1998-06-30 | Intel Corporation | Method and apparatus for providing two system architectures in a processor |
US5854913A (en) | 1995-06-07 | 1998-12-29 | International Business Machines Corporation | Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures |
US5948112A (en) * | 1996-03-19 | 1999-09-07 | Kabushiki Kaisha Toshiba | Method and apparatus for recovering from software faults |
US5829012A (en) | 1996-04-19 | 1998-10-27 | Unisys Corporation | System for programmably providing modified read signals within a ROM-based memory |
US5867681A (en) | 1996-05-23 | 1999-02-02 | Lsi Logic Corporation | Microprocessor having register dependent immediate decompression |
US5905893A (en) | 1996-06-10 | 1999-05-18 | Lsi Logic Corporation | Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set |
US5794010A (en) | 1996-06-10 | 1998-08-11 | Lsi Logic Corporation | Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor |
US5896519A (en) | 1996-06-10 | 1999-04-20 | Lsi Logic Corporation | Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions |
US5764994A (en) | 1996-09-16 | 1998-06-09 | International Business Machines Corporation | Method and system for compressing compiled microcode to be executed within a data processing system |
US5745058A (en) | 1996-10-21 | 1998-04-28 | International Business Machines Corporation | Method and system for compressing microcode to be executed within a data processing system |
US5954830A (en) | 1997-04-08 | 1999-09-21 | International Business Machines Corporation | Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs |
US6212630B1 (en) | 1997-12-10 | 2001-04-03 | Matsushita Electric Industrial Co., Ltd. | Microprocessor for overlapping stack frame allocation with saving of subroutine data into stack area |
US6012138A (en) | 1997-12-19 | 2000-01-04 | Lsi Logic Corporation | Dynamically variable length CPU pipeline for efficiently executing two instruction sets |
US20020144041A1 (en) * | 2001-03-29 | 2002-10-03 | Revilla Juan G. | Early exception detection |
Non-Patent Citations (28)
Title |
---|
"High Performance Dual Architecture Processor," IBM Technical Disclosure Bulletin, vol. 36, No. 2, IBM Corp., pp. 231-234 (Feb. 1993). |
"LSI Tiny Risc development," http://www.redhat.com/support/manuals/gnupro99r1/6_embed/emb09.html, 13 pages (Apr. 2001). |
"MIPS32 Archtecture for Programmers vol. IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture," Document No. MD00076, Rev. 2.50, MIPS Technologies, Inc., Mountain View, California, 162 pages (Jul. 1, 2005). * |
Bandyopadhyay, A. and Zheng, Y.F., "Combining Both Micro-Code And Hardwired Control In RISC," 5 pages, (published in ACM SIGARCH Computer Architecture News, vol. 15, Issue 4, pp. 11-15 (Sep. 1987)). |
Bursky, D., "Software-Efficient RISC Core Trims System-Memory Needs," Reprinted from Electronic Design, Penton Publishing, Inc., 3 pages (Mar. 20, 1995). |
Case, Brian, "ARM Architecture Offers High Code Density: Non-Traditional RISC Encodes Many Options in Each Instruction," Microprocessor Report, vol. 5, No. 23, pp. 11-14 (Dec. 18, 1991). |
Cobb, Paul, "TinyRISC: a MIPS-16 embedded CPU core," Presentation for Microprocssor Forum, 13 slides (7 pages) (Oct. 22-23, 1996). |
Gwennap, Linley, "VLIW: The Wave of the Future?: Processor Design Style Could Be Faster, Cheaper Than RISC," Microprocessor Report vol. 8, No. 2, pp. 18-21 (Feb. 14, 1994). |
Hayashi, T. et al., "A 5.6-MIPS Call-Handling Processor for Switching Systems," IEEE Journal of Solid-State Circuits, vol. 24, No. 4, IEEE, pp. 945-950 (Aug. 1989). |
IBM Technical Disclosure Bulletin, "Micro scode Memory Changes," vol. 21, Issue 1, pp. 341-342 (Jun. 1, 1978) ( 3 pages). |
IBM Technical Disclosure Bulletin, "Patch RAM Load Technique," vol. 27, Issue 6, pp. 3597-3598 (Nov. 1, 1984) (3 pages). |
IBM Technical Disclosure Bulletin, "Patchable Read-Only Storage and Other Patchable Functions," vol. 27, Issue 6, pp. 3496-3499 (Nov. 1, 1984) (4 pages). |
Intel486TM Microprocessor Family Programmer's Reference Manual, Intel Corporation, 1992, pp. 23-25, 23-26, and 23-29. |
Kurosawa, K., et al., "Instruction Architecture For A High Performance Integrated Prolog Processor IPP," Programming: Proceedings of the Fifth International Conference and Symposium (Aug. 15-19, 1988), MIT Press, Cambridge, MA, vol. 2, pp. 1506-1530 (1988). |
LSI Logic announces world's highest-performing 64-bit MIPS embedded microprocessor core: Two new MIPS-based EasyMACRO ASIC cores offer size, speed and performance advantages for a broad range of applications, from http://www.lsilogic.com/news/product_news/pr20000605.html, LSI Logic Corporation, 2 pages (Jun. 5, 2000). |
McNeley, K.J. and Milutinovic, V.M., "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer," IEEE Micro, IEEE, pp. 60-72 (Feb. 1987). |
MIPS Technologies Licenses MIPS64(TM) 5Kf(TM) and MIPS32(TM) 4KEc(TM) Processor Cores to LSI Logic, from http://www.mips.com/pressReleases/061101C.html, MIPS Technologies, Inc., 3 pages (Jun. 11, 2001). |
MIPS64 Architecture for Proammers vol. IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecutre, Document No. MD00076, Rev. 2.50, MIPS Technologies, Inc., Mountain View, California, 210 pages (Jul. 1. 2005). * |
NEC Data Sheet, MOS INtegrated Circuit, uPD30121, VR4121 64-/32-Bit Microprocessor (Copyright NEC Electronics Corporation 2000) (76 pages). |
NEC User's Manual, VR4100 Series(TM), 64-/32-Bit Microprocessor Architecture, pp. 1-11 and 54-83 (Chapter 3) (Copyright NEC Corporation 2002). |
Preliminary Amendment, filed Feb. 1, 2002, in U.S. Appl. No. 10/066,475, inventor Edward Colles Nevill, filed Feb. 1, 2002 (based on U.S. Pat. No. 6,021,265, issued Feb. 1, 2000) (15 pages). |
Ross, Roger, "There's no risk in the future for RISC," Computer Design, vol. 28, No. 22, pp. 73-75 (Nov. 13, 1989). |
Sweetman, D., See MIPS Run, Morgan Kaufmann Publishers, Inc., ISBN 1-55860-140-3, pp. vii-xiv, 91-101, 369-386 and 423-425 (1999). |
Turley, J., "LSI's TinyRisc Core Shrinks Code Size: Code-Compaction Technique Squeezes MIPS Instructions Into 16 Bits," Microprocessor Report, Microdesign Resources, pp. 40-43 (Oct. 28, 1996). |
U.S. Appl. No. 09/702,112, inventors Jensen, M., et al., filed Oct. 30, 2000 (not published) (67 pages). |
U.S. Appl. No. 09/702,115, inventors Jensen, M., et al ., filed Oct. 30, 2000 (not published) (71 pages). |
U.S. Appl. No. 10/066,475, inventor Edward Colles Nevill, filed Feb. 1, 2002 (based on U.S. Pat. No., 6,021,265, issued Feb. 1, 2000) (9 pages). |
V<SUB>R</SUB>4121(TM) 64/32-Bit Microprocessor muPD30121, NEC Corporation 1998, Document No. U13569EJ4V1UM00 (4<SUP>th </SUP>edition), pp. 1-19 and 103-131, Published Jul. 2000. |
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US20100257338A1 (en) * | 2009-04-07 | 2010-10-07 | Spracklen Lawrence A | Methods and mechanisms to support multiple features for a number of opcodes |
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