US7129547B2 - Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region - Google Patents
Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region Download PDFInfo
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- US7129547B2 US7129547B2 US10/971,624 US97162404A US7129547B2 US 7129547 B2 US7129547 B2 US 7129547B2 US 97162404 A US97162404 A US 97162404A US 7129547 B2 US7129547 B2 US 7129547B2
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000012212 insulator Substances 0.000 claims abstract description 36
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 21
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- 229920005591 polysilicon Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- WEAMLHXSIBDPGN-UHFFFAOYSA-N (4-hydroxy-3-methylphenyl) thiocyanate Chemical compound CC1=CC(SC#N)=CC=C1O WEAMLHXSIBDPGN-UHFFFAOYSA-N 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
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- 150000004706 metal oxides Chemical class 0.000 claims description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 2
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- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 229910021355 zirconium silicide Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 65
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- 238000002513 implantation Methods 0.000 description 5
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
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- 150000002500 ions Chemical class 0.000 description 3
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
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- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 239000001301 oxygen Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Definitions
- the present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a high performance metal oxide semiconductor field effect transistor (MOSFET), device, via the implementation of a disposable insulator spacer component and of a raised source/drain region.
- MOSFET metal oxide semiconductor field effect transistor
- One method used to overcome the vulnerability of shallow source/drain regions in a semiconductor substrate, during silicide formation, is the raised or elevated source/drain structure, formed via selective growth of single crystalline silicon on the shallow source/drain region.
- the selectively grown raised source/drain structure comprised with the same dopant conductivity type as the underlying shallow source/drain region in the semiconductor substrate, can easily except overlying silicide formation without consumption of the underlying shallow source/drain region located in a top portion of the semiconductor substrate.
- raised source/drain structure incorporates removal of an insulator spacer located on the sides of a gate structure to expose additional portions of a heavily doped source/drain region, and therefore when overlaid with the raised source/drain structures provide still additional decreases in source/drain resistance.
- the removal of the insulator spacer component can however damage the exposed shallow source/drain region.
- some raised source/drain fabrication procedures do not allow silicide formation to occur on the gate structure, therefore limiting gate resistance reduction.
- the present invention will describe a novel process sequence in which a raised source/drain structure is formed via low temperature selective epitaxial growth procedures after formation of the shallow source/drain region in the semiconductor substrate, and after removal of an overlying or outer insulator spacer component, therefore regrowing non-damaged silicon on the possibly damaged surface of the shallow source/drain region.
- a novel process sequence for etching back a horizontal segment of an underlying, or inner insulator spacer component, allowing a portion of a lightly doped source/drain (LDD), region to be exposed and overlaid by the subsequently grown raised source/drain structure is also presented in this invention.
- Prior art such as Moslehi, in U.S. Pat. No.
- a method of forming a raised source/drain structure on a heavily doped source/drain region and on a portion of lightly doped source/drain region, located in portion of a semiconductor substrate previously damaged during procedures used to remove components of a composite insulator spacer is described.
- a lightly doped source/drain (LDD), or a source/drain extension region is formed in a portion of the semiconductor substrate not covered by the conductive gate structure.
- a heavily doped source/drain region is formed in the area of the semiconductor substrate not covered by the conductive gate structure or by the composite insulator spacer.
- a wet etch procedure is used to remove the silicon nitride component of the composite insulator spacer exposing the silicon oxide spacer component now comprised with a horizontal segment overlying a portion of the LDD region, with the wet etch procedure damaging as well as removing a top portion of surface of the exposed heavily doped source/drain region, and removing a top portion of the exposed conductive gate structure.
- a silicon oxide thinning procedure is used to remove the horizontal segment of the silicon oxide spacer component exposing of a portion of the LDD region, with the silicon oxide thinning procedure resulting in additional damage to, and removal of, the heavily doped source/drain region, as well as resulting in additional recessing of the conductive gate structure.
- a selective epitaxial growth (SEG), procedure is performed resulting in a raised source/drain structure, comprised of single crystalline silicon, located on the damaged heavily doped source/drain region and on the exposed portion of LDD region, with the SEG procedure also resulting in the regrowth of polycrystalline material in the recessed portion of the conductive gate structure. Implantation and anneal procedures are then employed to adequately dope the raised source/drain structures, as well as the regrown polycrystalline structure located on the recessed conductive gate structure.
- FIGS. 1–7 which schematically in cross-sectional style illustrate key stages used to fabricate a MOSFET device featuring a raised source/drain structure located on a heavily doped source/drain region and on a portion of lightly doped source/drain region, both located in portion of a semiconductor substrate previously damaged during procedures used to remove components of a composite insulator spacer.
- Semiconductor substrate 1 comprised of single crystalline P type silicon, featuring a ⁇ 100> crystallographic orientation, is used and schematically shown in FIG. 1 .
- Gate insulator layer 2 comprised of silicon dioxide, is thermally grown to a thickness between about 10 to 100 Angstroms, in an oxygen-steam ambient.
- a conductive material such as polysilicon
- LPCVD low pressure chemical vapor deposition
- the polysilicon layer can be doped in situ during deposition via the addition of arsine, or phosphine to a silane or disilane ambient, or the polysilicon layer can be intrinsically deposited then subjected to implantation of arsenic or phosphorous ions.
- a photoresist shape is next formed and used as an etch mask to allow an anisotropic reactive ion etch (RIE), procedure to define conductive gate structure 3 a, comprised with a width between about 200 to 2500 Angstroms.
- RIE anisotropic reactive ion etch
- the narrow width of conductive gate structure 3 a will allow a sub-50 nm MOSFET device, or a MOSFET device with a channel length less than 50 nm, to be ultimately be realized.
- the anisotropic RIE procedure is performed using Cl 2 or SF 6 as a selective etchant for polysilicon, terminating at the appearance of the top surface of gate insulator layer 2 .
- Removal of the photoresist shape used for definition of conductive gate structure 3 a is accomplished via plasma oxygen ashing and wet clean procedures, with a buffered hydrofluoric acid cycle, used as a component of the wet clean procedures, removing the portions of gate insulator layer 2 , not covered by conductive gate structure 3 a.
- LDD Lightly doped source/drain
- region 4 is next formed in a portion of semiconductor substrate 1 , not covered by conductive gate structure 3 a, via implantation of arsenic or phosphorous ions, at an energy between about 2 to 10 KeV, and at a dose between about 1E14 to 5E15 atoms/cm 2 . This is schematically shown in FIG. 1 .
- a silicon oxide layer is next deposited to a thickness between about 200 to 1000 Angstroms, via LPCVD or via plasma enhanced chemical vapor deposition (PECVD), procedures, followed by deposition of an overlying silicon nitride layer at a thickness between about 200 to 1000 Angstroms, again via LPCVD or PECVD procedures.
- An anisotropic RIE procedure is next employed to define a composite insulator spacer on the sides of conductive gate structure 3 a.
- the anisotropic RIE procedure initiates with definition of overlying silicon nitride spacer component 6 , using Cl 2 or CF 4 as a selective etchant for silicon nitride, with the anisotropic RIE procedure concluding with the definition of underlying silicon oxide spacer component 5 a, obtained using CHF 3 as a selective etchant for silicon oxide, with this cycle of the anisotropic RIE procedure terminating at the appearance of the top surface of LDD region 4 , and of the appearance of the top surface of conductive gate structure 3 a.
- This is schematically shown in FIG. 2 .
- Heavily doped source/drain region 7 also schematically shown in FIG.
- conductive gate structure 3 a is next formed via implantation of arsenic or phosphorous ions, at an energy between about 10 to 50 KeV, and at a dose between about 1E14 to 5E15 atoms/cm 2 , in portions of semiconductor substrate 1 , not covered by conductive gate structure 3 a, or by the composite insulator spacers located on the sides of conductive gate structure 3 a.
- FIGS. 3–4 The procedures employed to increase the level of surface area of heavily doped source/drain region 7 , and to expose a portion of LDD region 4 , for an overlying raised source/drain structure, via removal of regions of the composite insulator spacer, are next addressed and schematically shown using FIGS. 3–4 .
- a hot phosphoric acid solution at a temperature between about 150 to 250° C., is used to remove silicon nitride spacer component 6 , exposing underlying silicon oxide spacer component 5 a. This is schematically shown in FIG. 3 .
- Silicon oxide spacer component 5 a is comprised of a vertical feature located on the sides of the conductive gate structure, as well as a horizontal feature which overlays a portion of LDD region 4 .
- the hot phosphoric acid procedure in addition to removing silicon nitride spacer component 6 , also removed a top portion, between about 10 to 100 Angstroms, of the conductive gate structure, resulting in recessed conductive gate structure 3 b.
- the hot phosphoric acid solution resulted in the removal of a top portion, between about 10 to 100 Angstroms, of heavily doped source/drain 7 , leaving heavily doped source/drain region 7 , with a damaged top surface 8 a.
- a RIE procedure is used to remove the horizontal segment of silicon oxide spacer component 5 a. This is accomplished using CF 4 as a etchant for silicon oxide resulting in silicon oxide spacer component 5 b, now comprised of only a vertical feature located on the sides of the conductive gate structure.
- the RIE procedure in addition to removing the horizontal segment of the silicon oxide spacer component also removes a portion of exposed heavily doped source/drain region 7 , between about 10 to 100 Angstroms, resulting in a heavily doped source/drain region shallower than desired for attainment of a minimum source/drain resistance.
- the RIE procedure continued the damage procedure of the remaining heavily doped source/drain region 7 , resulting in damaged surface 8 b.
- the RIE procedure used for removal of the horizontal segment of the silicon oxide spacer component also continued the recessing of the conductive gate structure, removing between about 10 to 100 Angstroms of material from recessed conductive gate structure 3 b, resulting in fully recessed conductive gate structure 3 c. This is schematically shown in FIG. 4 .
- the method of selectively growing a raised source/drain structure on the underlying damaged surface of heavily doped source/drain region 7 , and on exposed portion of LDD region 4 , employed to reduce source/drain resistance and to bury the damaged surface, is next addressed and schematically shown using FIG. 5 .
- An SEG procedure is performed at a temperature between about 500 to 900° C., at a pressure between about 0.10 to 100 mtorr, for a time between about 1 to 60 min, using silane or disilane as a source of silicon.
- the result of the SEG procedure is the selective growth of single crystalline silicon, raised source/drain structure 9 , at a thickness between about 100 to 800 Angstroms, on the exposed surface of heavily doped source/drain region 7 , and on the exposed portion of LDD region 4 .
- the SEG procedure also results in the growth of raised conductive structure 15 , at a thickness between about 100 to 800 Angstroms, on the surface of recessed conductive gate 3 c. If recessed conductive gate structure 3 c, is comprised of material other than a single crystalline silicon, raised conductive gate shape 15 , will be comprised of polycrystalline silicon. No single crystalline or polycrystalline growth occurs on insulator surfaces, such as the surface of silicon oxide spacer component 5 b.
- an ion implantation procedure is employed to lower the resistance of raised source/drain structure 9 , and of raised conductive structure 15 .
- the implantation procedure is performed using arsenic or phosphorous ions, at an energy between about 5 to 50 KeV, at a dose between about 5E14 to 1E16 atoms/cm 2 , placing N+ ions 10 , in both raised source/drain structure 9 , and in raised conductive structure 15 .
- An anneal procedure is next performed using either conventional furnace procedures, or via rapid thermal anneal (RTA), procedures, to activate N+ ions 10 . The result of these procedures is schematically shown in FIG. 6 .
- metal silicide 16 is selectively formed on raised source/drain structure 9 , and on raised conductive gate structure 15 . This is accomplished via plasma vapor deposition of a metal layer such as titanium, cobalt, nickel, zirconium, tungsten, or tantalum, at a thickness between about 100 to 500 Angstroms.
- An anneal procedure is next performed, using either conventional furnace procedures, or rapid thermal anneal (RTA), procedures, to selectively form metal silicide 16 , on raised source/drain structure 9 , and on raised conductive gate structure 15 .
- RTA rapid thermal anneal
- metal silicide 16 comprised of either titanium silicide, cobalt silicide, nickel silicide, zirconium silicide, tungsten silicide, or tantalum silicide, is between about 100 to 300 Angstroms. Unreacted metal is selectively removed from the surface of silicon oxide spacer component 3 b, via wet etch procedures. If desired an additional anneal procedure can be employed to further reduce the resistance of metal silicide 16 .
- the result of the silicide procedure is schematically shown in FIG. 7 .
Abstract
Description
Claims (9)
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Application Number | Priority Date | Filing Date | Title |
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US10/971,624 US7129547B2 (en) | 2002-06-24 | 2004-10-22 | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
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US10/178,384 US6893917B2 (en) | 2002-06-24 | 2002-06-24 | Structure and fabricating method to make a cell with multi-self-alignment in split gate flash |
US10/455,038 US6902980B2 (en) | 2003-06-05 | 2003-06-05 | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
US10/971,624 US7129547B2 (en) | 2002-06-24 | 2004-10-22 | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
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US10/455,038 Division US6902980B2 (en) | 2002-06-24 | 2003-06-05 | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
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US20040248369A1 (en) | 2004-12-09 |
US6902980B2 (en) | 2005-06-07 |
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