US7269803B2 - System and method for mapping logical components to physical locations in an integrated circuit design environment - Google Patents
System and method for mapping logical components to physical locations in an integrated circuit design environment Download PDFInfo
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- US7269803B2 US7269803B2 US10/740,284 US74028403A US7269803B2 US 7269803 B2 US7269803 B2 US 7269803B2 US 74028403 A US74028403 A US 74028403A US 7269803 B2 US7269803 B2 US 7269803B2
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- the present invention relates to computer-aided design of integrated circuits. More particularly, the present invention relates to a system and method for optimized placement and orientation of logical components to physical locations on a selected prefabricated silicon wafer to form an integrated circuit.
- An integrated circuit sometimes referred to as a “chip” or “microchip”, is a semiconductor wafer on which thousands or millions of circuit elements, such as resistors, capacitors and transistors, are fabricated.
- the thousands or millions of circuit elements are electrically interconnected and arranged to perform various functions.
- transistors can be interconnected to perform boolean logic functions such as “AND”, “OR”, “NOT” and “NOR”.
- boolean logic functions such as “AND”, “OR”, “NOT” and “NOR”.
- Such an arrangement of transistors implementing a single boolean logic function is sometimes referred to as a “gate”.
- Such combinations of transistors, gates and their wire interconnections are the fundamental building blocks of even the most complex integrated circuits.
- Integrated circuits are generally fabricated on a thin, silicon wafer or substrate.
- semiconductor devices and electrical interconnections are formed using mask layers deposited on top of one another on the substrate.
- Each successive mask layer may have a pattern that is defined using a mask, which introduces a shape or a pattern on an underlying layer in a particular process step during fabrication.
- the pattern on the underlying layer may be processed to define various device features.
- the mask layers are fabricated through a sequence of pattern definition steps using the masks, which are interspersed with other process steps such as oxidation, etching, doping and material deposition.
- the mask layer is programmed or customized.
- the lowest, “base” layers of the substrate include the active areas of the semiconductor devices, such as diffusion regions and gate oxide areas, and desired patterns of the poly-silicon gate electrodes.
- One or more metal and insulating layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment of one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
- ICs include more transistors in less space than ever before.
- interconnections As the number of interconnections have increased, the challenge of translating a circuit designer's intended “specific functionality” into a working IC has also increased, exponentially.
- complex integrated circuits now contain large numbers of transistors, gates, semiconductors and interconnections, the circuits are more difficult to specify (interconnect) correctly.
- the laws of physics that govern the behavior of such densely populated integrated circuits are much more subtle and complex than that of larger, less dense chips. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. Such issues increase the expense and risk of designing and fabricating integrated circuits.
- function blocks can be optimized for particular frequencies, for power consumption or for various other design considerations.
- function blocks can be incorporated in an integrated circuit; however, inclusion of function blocks necessitates testing to ensure that such blocks operate correctly and that they do not introduce timing and other problems to the rest of the circuit.
- placement tools A class of computer programs, referred to as “placement tools”, have been written to automate placement of circuit elements. However, such tools are typically used to place logical elements in a circuit design before the underlying silicon layers are formed. None of these tools are capable of handling the complex process rules required for legal placement of cells on specific, pre-manufactured diffused silicon slices.
- a method maps logical components onto a pre-fabricated chip slice.
- a definition is received corresponding to the pre-fabricated chip slice.
- a logical function block is selected for placement onto the chip slice.
- the definition of the chip slice is searched for a location that is available for placement of the selected function block.
- the selected function block is mapped to the location.
- a function block is mapped to a chip slice layout.
- a slice definition of a chip slice is received.
- a logical block is selected for placement onto the chip slice corresponding to the chip slice layout.
- the slice definition is scanned for an open site on the chip slice with resources to match corresponding requirements of the logical block.
- the logical block is mapped to the open site.
- a system for mapping logical components to a pre-fabricated chip slice includes a slice database, logical definitions of circuit components, and a software application.
- the slice database contains information relating to the slice.
- the logical definitions of circuit components correspond to physical circuit element to be mapped onto the slice.
- the software application adapted to search the slice database for legal cell locations on the slice corresponding to each logical definition, the software application is adapted to map the logical circuit component onto the slice based on identified legal cell locations.
- FIG. 1 is a simplified block diagram of a process according to one embodiment of the present invention.
- FIG. 2 is a block diagram of a pre-fabricated, non-metallized microchip slice according to an embodiment of the present invention.
- FIG. 3A is a graphical representation of a typical RCELL component.
- FIGS. 3B-3F are simplified block diagrams illustrating various orientations of the RCELL component of FIG. 3A .
- FIG. 4 is a graphical representation of a typical diffused Mega cell.
- FIG. 5 is a graphical representation of a typical RCELL Mega cell component.
- FIG. 6 is a graphical representation of a chip where the logical to physical mapping of the present invention has taken place and components have been assigned to physical locations on a selected chip slice.
- FIG. 7 is screen shot of a design tool used to physically map the logical elements to the selected slice with a portion of the mapped slice of FIG. 6 visible within the display window.
- FIG. 8 is a simplified block diagram of the system of the present invention.
- FIG. 9 is a simplified flow diagram of an embodiment of instance generation according to a method of the present invention.
- FIG. 10 is a simplified flow diagram of a method of cell placement according to an embodiment of the present invention.
- FIG. 11 is a flow diagram of the method for RCELL placement according to an embodiment of the present invention.
- FIG. 12 is a flow diagram of the method for optimized placement of an RCELL Mega cell on a prefabricated slice.
- FIG. 13 is a flow diagram of the method for optimized placement of a diffused Mega cell on a prefabricated slice.
- the present invention relates to a computer aided physical design process of an integrated circuit.
- embodiments of the present invention are useful with the methods and processes described in U.S. patent application Ser. No. 10/335,360, filed on Dec. 31, 2002, and the other patent applications referenced above by serial number in the Cross-Reference to Related Applications, all of which are incorporated herein by reference in their entirety.
- IP Intelligent Property
- slice refers to a pre-manufactured chip in which all silicon-based layers have been constructed, leaving the top metal layers to be completed.
- the slice is customizable by building on top of the pre-fabricated silicon-based layers.
- One embodiment of the present invention is directed to a method for semiconductor platform design that proceeds in two stages.
- a slice is produced that incorporates standard circuit elements (such as configurable I/O circuitry) required for specific market or application needs.
- the slice is manufactured up to the point of metallization.
- Various slices can be designed and/or fabricated to meet specific needs.
- Such slices can be characterized by various parameters, including size, layout and placement of diffused areas, and the like to produce a slice definition, which can be used to map logical elements to the physical layout of the slice.
- an embodiment of the present invention is directed to a software tool for mapping a logical design of a circuit to a physical implementation of the circuit.
- the software tool utilizes a slice database containing design data about the layout of one or more pre-fabricated slices in order to identify optimal locations and orientations for placement of various standard cells, logic blocks, and custom circuit elements onto the pre-fabricated slice.
- the silicon layers of a slice provide features, including diffused regions and transistor fabric, which are connected with customer-specific metallization patterns.
- a prefabricated slice is selected, logical elements are added, and then custom circuit elements are added to form a customized integrated circuit.
- FIG. 1 illustrates a progression of a typical slice 10 .
- Slice 10 has diffused memory blocks 12 , phase lock loop elements (PLLs) 14 , proprietary or standard blocks 16 , and a configurable transistor area or “fabric” 18 .
- An input/output (I/O) ring 20 is made from configurable and dedicated I/Os according to specific needs. Thus, by selecting specific proprietary or standard blocks and by forming the I/O ring for specific implementations, entire families of slices can be created, which are aimed at particular applications.
- the configurable transistor fabric 18 provides the basis for implementing custom logic elements.
- An RCELL is a basic unit within the transistor fabric 18 .
- An RCELL is made up of specially sized “N” and “P” type transistors for maximum flexibility and performance.
- RCELLS are generally diffused in a regular pattern throughout the slice 10 and are arranged to implement efficiently both memory and logic structures.
- the RCELLS are configured by interconnecting the various components through multiple layers of metal to allow for the creation of a full range of logic functions.
- Transistors within the transistor fabric 18 are activated only when they are part of the implementation of a function used in the design, ensuring optimum power-efficiency.
- the memory blocks 12 are diffused into each slice.
- the memory blocks 12 can include single-port and dual-port, high density, high-performance RAM blocks, which define a memory space configurable to meet a particular application's needs. Additionally, diffused memories can be combined with RAM memory spaces constructed from the transistor fabric 18 , allowing a chip designer the flexibility to specify memory arrays of arbitrary width and depth.
- the PLLs 14 are electronic circuit elements with a voltage-driven or current-driven oscillator that can be constantly adjusted to match the phase and the frequency of an input signal, and thus lock onto the signal.
- a PLL 14 can be used to generate a signal (such as a clock signal), modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.
- blocks 16 typically refers to re-usable circuit blocks, available for use in larger circuit designs.
- the blocks 16 are typically standard circuit elements that have been tested and optimized, and often such blocks 16 are proprietary and protected by patents and copyrights.
- Such blocks or cores can be used as black box functions or modules for implementation in a circuit design.
- Blocks 16 may be hard, firm or soft.
- a hard block 16 is diffused at optimal locations within the slice, using cell-based elements for maximum performance and density.
- Firm blocks 16 are preconfigured for high performance and have known characteristics.
- Firm blocks 16 may be located anywhere within the transistor fabric 18 of the slice.
- Soft blocks are incorporated into the slice as functional blocks and are implemented in the transistor fabric 18 like any other block, but with specific timing criteria to ensure their functionality.
- I/Os are diffused in the slice 10 where industry standards dictate and performance and power provide a justification. Since chip designers typically require some flexibility, all slices 10 have configurable I/Os, which are capable of operating with the most commonly used signaling standards, such as LVTTL, LVDS, HSTL, SSTL, and the like. Using a software-based general I/O tool, the designer can specify the industry standard as well as the voltage levels, drive strengths and pin locations. These parameters cause the general I/O tool to create customized metal patterns that connect uncommitted transistor networks in an I/O region of a slice 10 in order to implement all required buffer types.
- additional elements 22 can be selected and added to the pre-configured slice 10 .
- the elements 22 are stored in one or more databases, and may be proprietary or open architecture, depending on the specific implementation. Typically, it is desirable that even proprietary blocks 16 work with existing standards, though that is not always necessary.
- the customer specific logic 24 (custom silicon) is added to the slice 10 . Specifically, the customer provides or designs custom logic 24 , which is mapped to the slice 10 .
- an embodiment of the present invention involves selecting a slice 10 and adding circuit elements to that selected slice. Another embodiment involves selecting a slice 10 from a family of slices, adding standard cells and standard blocks 16 to the slice 10 , and adding custom silicon and custom elements 24 onto the slice to form an integrated circuit.
- FIG. 2 illustrates an enlarged view of an embodiment of a slice 10 .
- the slice 10 represents the base layers for the integrated chip. Specifically, the base layers for the standard cells, diffused Mega cells, RCELLS and RCELL Mega cells have already been assigned fixed physical locations on the base layers. Therefore, it is desirable to identify a physical location for an instance of the design for a given slice that maps correctly to a pre-manufactured image of the given slice.
- the slice 10 has diffused memory blocks 12 , core blocks 16 , transistor fabric 18 , and configurable I/Os 20 .
- the core blocks 16 include a Gigblaze x8 block 26 , a Gigablaze x4 block 28 , and two HyperPHY standard x20 cores 30 , which are commonly available from LSI Logic Corporation.
- the PLL 14 A is configured as a clock generator, and a section of the configurable I/Os 20 has been set aside as control I/Os 32 .
- pin-outs 34 are provided around the periphery of the slice 10 for interfacing with electrical connections to a device, a printed circuit board, or other chips (not shown).
- the pre-fabricated slice 10 can be formed with any number of pre-diffused blocks 12 , with custom or core blocks 16 , with various PLLs 14 , and has configurable I/Os 20 to provide a versatile base on which the integrated circuit can be formed. Additionally, the transistor fabric 18 allows a designer a great deal of flexibility for adding various circuit elements.
- One embodiment of the present invention provides a technique for identifying the layout and structure of the slice 10 and for identifying legal site locations and orientations for RCELLs, RCELL Mega cells, and diffused Mega cells.
- RCELLs RCELL Mega cells
- diffused Mega cells a technique for identifying the layout and structure of the slice 10 and for identifying legal site locations and orientations for RCELLs, RCELL Mega cells, and diffused Mega cells.
- FIG. 3A is a layout diagram of a typical RCELL component 300 .
- the layout diagram specifies the base layer arrangement and interconnections within the RCELL component 300 .
- the RCELL component 300 has a row height (h) and column width (w).
- An orientation marker 302 is shown in phantom to indicate the direction and orientation of the RCELL component 300 relative to an origin 303 in FIGS. 3B-3F .
- the arrangement and orientation of the RCELL 300 is determined in part by the power/ground grid, which is fabricated onto the slice.
- Each RCELL 300 is arranged on the slice to correspond to the power grid. However, it can work either way, meaning that the power grid can be determined according to the RCELL layout.
- the orientation marker 302 (shown as a slanted F-shaped mark in phantom) indicates the direction and orientation of the cell 300 relative to an origin 303 .
- the cells 300 may be oriented back-to-back in a row or facing the same direction within a row.
- the row of cells can be flipped upside down.
- a row 310 of cells 300 are shown in a simplified block diagram.
- the cells 300 are oriented in a back-to-back configuration, with the back-to-back configuration beginning with cells two and three in the row.
- RCELL component 300 is shown facing in the same direction as in FIG. 3A , while component 300 ′ is shown in a flipped orientation.
- a dashed line is provided to mark the separation between RCELLS.
- the first cell site 312 and the second cell site 313 in row 310 are not back-to-back, but the second and third cell sites 313 and 314 , and the fourth and fifth cell sites 314 and 315 and so on are paired in a back-to-back configuration.
- the power/ground grid can be arranged such that the power lines 318 are drawn between back-to-back cells.
- the corresponding ground lines 320 may be drawn along one or both sides of the row 310 . If the cell sites are positioned back-to-back within a row 310 , the power grid lines 318 can be arranged approximately two cell widths apart.
- FIG. 3C illustrates a row 310 of cells 300 arranged so that they are all oriented in the same direction (meaning that the cell sites are not back to back within the row 310 ).
- the power grid is spaced such that the power lines 318 are spaced apart by a width of a cell 300 .
- a power line 318 must be drawn between each cell site.
- the ground grid 320 is drawn along the top of the row 310 .
- FIG. 3D illustrates a row 310 of cells 300 where the first cell is flipped.
- the power grid lines 318 are drawn such that two cells 300 are connected to each power grid line, and the grid lines are spaced apart by approximately the width of two RCELLS. As shown, the power grid lines 318 are drawn between the first and second cell sites 312 and 313 , between the third and fourth cell sites 314 and 315 , and so on.
- FIGS. 3E and 3F illustrate inverted rows 310 of cells 300 .
- FIG. 3E shows a row having an orientation similar to the first three cell sites of FIG. 3B , but oriented such that the row 310 is flipped upside down.
- FIG. 3F shows a row having an orientation similar to the first three cells of FIG. 3D , but oriented such that the row 310 is flipped upside down. Since both FIGS. 3E and 3F illustrate rows 310 having back-to-back configurations, the power grid lines 318 in both figures are positioned between back-to-back cells, and can be spaced two cell widths apart.
- the cells are oriented back-to-back so that fewer power grid lines are needed.
- the origin 303 is mapped to the power/ground grid, such that the origin 303 is positioned at an apparent intersection of a power line with a ground line. It will be understood by a worker skilled in the art that the power and ground lines are insulated from one another, such that no actual intersection between the power and the ground lines exists.
- the chip slice may contain an array of RCELL base components, arranged in horizontal rows.
- the RCELL is the smallest component that can be placed on the chip.
- a “standard cell” is a primitive logic function realized by one or more RCELL components that will fit in one horizontal row.
- An RCELL Mega cell is a complex logic function, which is composed of a number of RCELLs and which may span multiple rows. The RCELL Mega cell may be placed in any unused location on the slice.
- Diffused Mega cells are complex logic functions that may span multiple rows. Diffused Mega cells are not necessary made up of RCELLS.
- the base layers for the diffused Mega cells are pre-manufactured as diffused areas located at one or more fixed positions on the slice.
- FIG. 4 is an illustration of a typical diffused Mega cell 400 . While a typical RCELL is approximately four cells or four transistors, a Mega cell may be on the order of 10,000 to 100,000 gates.
- a diffused Mega cell is a Mega cell that requires a pre-diffused area on the slice.
- a pre-diffused area is an area made or adapted to accept only particular types of elements. In general, a pre-diffused area on the slice is an area of the slice that has been processed or otherwise prepared for particular circuit structures. For example, a pre-diffused area can be formed for use as a memory block.
- Mega cells are not necessarily made up of RCELLS 300 .
- This embodiment of a diffused Mega Cell includes an RCELL section 410 that is snapped to a power/ground grid formed of a ground lines 412 and power lines 414 . Viewed closely, the power lines 414 and ground lines 412 are partially visible between the closely clustered RCELL section 410 .
- a diffused Mega Cell may span multiple rows and columns, and can only be placed in an unused pre-diffused location on the slice.
- FIG. 5 illustrates a typical RCELL Mega cell component 500 .
- An RCELL Mega cell 500 is a complex logic function, which is composed of a number of RCELLS, and which may span multiple rows.
- An RCELL Mega cell can be placed in any unused location on the slice.
- the RCELL Mega cell 500 includes a grid of power lines 510 and ground lines 512 adapted to mate with a corresponding power grid of a slice.
- a chip is shown where the logical to physical mapping of the elements of FIGS. 3-5 has already been performed.
- a designer selects a prefabricated chip slice from a selection of pre-defined slice definitions. The selection is based on the slice definition that most closely matches the requirements of the end product.
- IP blocks (RCELLS 400 , diffused Mega cells 500 , and RCELL Mega cells 600 ) from a logic library such as that maintained by LSI Logic Corporation of Milpitas, Calif. and/or from logic libraries maintained by an open source organization.
- the designer selects custom or proprietary IP blocks for addition to the slice.
- Such proprietary IP blocks may be accessed from their netlist definitions or synthesized into a standard format.
- an embodiment of the present invention may then be operated to physically map the selected IP blocks onto the slice in legal and optimized locations and orientations.
- FIG. 6 illustrates a chip 600 where the logical to physical mapping has taken place, and the IP components have been assigned to physical locations on the slice 602 .
- the chip 600 has a plurality of I/Os 604 along its peripheral edges.
- Configurable I/Os 606 extend along a portion of one side.
- RCELLS which are too small to be visible on the transistor fabric 608 , diffused Mega Cells 610 , and RCELL Mega Cells 612 have been mapped to the chip 600 .
- RCELLs can be mapped to the transistor fabric 608 at any unused location.
- Diffused Mega Cells 610 are mapped to unused locations where the underlying slice 602 was diffused. Diffused areas 614 are generally visible as a slightly smaller outline within the mapped diffused Mega cell 610 structure.
- the RCELL Mega Cells 612 are mapped to diffused locations 614 on the slice 602 ; however, RCELL portions 616 of the RCELL Mega cell 612 (such as element 410 in FIG. 4 ) may extend beyond the edge of the diffused location 614 and into the transistor fabric of the slice 602 .
- the overlapping portion of the RCELL Mega cell 612 is shown in phantom.
- the RCELL Mega cells are mapped to diffused locations 614 on the slice 602 that are unused and that have unused transistor fabric directly adjacent to the diffused location 614 .
- This structure allows the designer flexibility in adding custom transistor logic to a circuit element that also requires a diffused area.
- FIG. 7 is a screen shot of the circuit chip layout of FIG. 6 within a graphical window 700 of a design tool according to an embodiment of the present invention.
- the view is a magnified view of the chip of FIG. 6 .
- the circuit elements are magnified such that individual RCELLs 702 between the larger diffused Mega cells 704 and RCELL Mega cells 706 are visible.
- the boundaries of the diffused areas 708 are visible within the Mega cell structures 704 , 706 .
- the RCELL portions 710 of the RCELL Mega cells 706 which extend beyond the borders of the prediffused areas 708 , are visible.
- I/Os 712 are visible just below a menu bar 714 of the graphical user interface.
- buttons 716 for interacting with the elements displayed.
- buttons 716 are provided for changing the magnification, for changing display options, for switching between layers of the design, for connecting elements, for adding elements, and to provide access to net lists and the like.
- FIG. 8 illustrates an embodiment of the present invention.
- a system 800 for mapping logical circuit elements to physical locations on a pre-fabricated slice includes a cell placement application 810 and an instance generator 812 .
- the application 810 has access to a slice definition database 814 and a design database 816 , as well as a customer netlist 818 .
- a customer netlist 818 typically includes the circuit definitions and rules corresponding to the customer's custom circuit design.
- the slice definition database 814 includes data related to the prefabricated microchip slice, including size and location of diffused areas, I/O locations and layout, location and definitions of any pre-fabricated circuit components, IP blocks, and the like.
- the design database 816 stores the logical-to-physical mapping of the completed chip design.
- the entire system can be stored on a single machine (indicated by dashed-line 820 ), or could be distributed on a network.
- the application 810 and instance generator 812 could be a single compiled application (indicated by dashed line 822 ) or a plurality of software tools coordinated to function together to map the logical elements to the physical slice.
- the specific implementation of the application 810 is secondary to its functionality. While an intuitive graphical user interface is desirable, it is not necessary to implement the method of the present invention. Command line type software applications could similarly to be used to implement some of the algorithms of the present invention. However, a graphical user interface that provides a graphical view of the circuit layout is desirable because it provides an intuitive interface for a designer to understand the particular implementation.
- the slice definition database 814 is updated to store information about the pre-fabricated slice, including information about the base RCELL array structure.
- the instance generator 812 abstracts the slice definition stored in the slice definition database 814 in such a way that the data can be used subsequently by a customer for their own unique design. This process is referred to as instance creation.
- FIG. 9 is a flow diagram illustrating one embodiment of the process of instance generation.
- the instance generator 812 accesses the slice database 814 (step 900 ).
- the instance generator 812 identifies row definitions, valid RCELL orientations within the rows, and the location and all possible valid orientations of diffused Mega cells and RCELL Mega cells (step 902 ). From this information, the instance generator creates site definitions for the base array rows and for the diffused Mega cell sites (step 904 ).
- the instance generator assigns properties to identify slice structures (step 906 ). The properties can be used to identify those structures during cell placement.
- the instance generator identifies the location and spacing of power and ground rail structures (step 908 ). Finally, the instance generator stores the site definitions, the properties, and the power/ground rail information in the database (step 910 ). This stored information represents an abstraction of the slice definition, which can be used by customers to create unique designs, and the process can be referred to as “instance creation.”
- the information generated by the instance generator is used to auto-place (or auto-interactively place) RCELLs ( FIG. 11 ), RCELL Mega cells ( FIG. 12 ), and diffused Mega cells ( FIG. 13 ) onto the slice based on legal orientations determined by the software application ( FIG. 10 ).
- the cell placement tool is a software application that may allow the designer to specify an approximate location for the particular cell. In another embodiment, the software application may simply choose an optimal location from available unused locations.
- the cell placement application searches the base layer definitions created by the instance generator to identify an open, acceptable location for a cell, and uses the properties added to the rows by the instance generator to determine the proper orientations for the cell.
- FIG. 10 shows a simplified flow diagram illustrating one possible flow for identifying the orientation and location of an open cell site for placement of a cell.
- the system of the present invention utilizes chip properties previously defined by the instance generator to determine the orientation of each row based on the “Normal” or “Flipped” orientation (step 1000 ). Then for the cells within each row, the system reads the previously defined properties of the standard cell to determine where the cell sites are inside the standard cell. (step 1002 ). The system locates a matching set of open cell sites within the row (step 1004 ). The system orients the standard cell to match the orientation of a selected open cell site (step 1006 ), and places the cell (step 1008 ).
- An excerpt of pseudo code for finding the nearest non-flipped cell site within a given row based on the properties is provided below.
- the grid is defined by “grid” and “offset” variables def SnapNearest(self,orig_loc,grid,offset): ... .
- the grid is defined by the “grid” and “offset” variables def SnapNearestOdd(self,orig_loc,grid,offset): ... .
- the grid is defined by the “grid” and “offset” variables def SnapNearestEven(self,orig_loc,grid,offset): ... .
- the RCELL orientation of the first RCELL is assigned such that if the power and ground lines of the RCELL match up with those of the corresponding slice. In this manner, by snapping the RCELL to the returned cell site, the RCELL is guaranteed to be over a legal base array site. In other words, the power and ground mesh of the RCELL is oriented and aligned to match precisely with the power and ground mesh of the slice.
- the method of auto-interactively placing RCELLs may allow a user to specify an approximate location for the RCELL cell.
- the pseudo code above provides an overview of the algorithm used by the application.
- a user specifies an approximate location for the RCELL cell (step 1100 ).
- the system assumes that the specified (suggested) location is the center of the cell outline (step 1102 ).
- the system identifies the closest rows (step 1104 ), iteratively.
- the system identifies the closest open cell sites within the closest rows (step 1106 ).
- the system picks the closest open cell site based on an Euclidean distance between the suggested point and the closest identified points (step 1108 ).
- the system places the RCELL (step 1110 ).
- FIGS. 12 and 13 involve steps similar to that of FIG. 11 ; however, within the cell definition, the number of legal sites available for diffused Mega cells and RCELL Mega cells are limited by the slice definition. Thus, though the system can search iteratively for the locations, fewer sites must be scanned.
- Mega cells are created using specific generation tools of a integrated circuit design suite, such as that disclosed in U.S. patent application Ser. No. 10/335,360 filed Dec. 31, 2002 and entitled “A SIMPLIFIED PROCESS TO DESIGN INTEGRATED CIRCUITS”, which is incorporated herein by reference in its entirety.
- the generation tools construct the power and ground mesh within the Mega cell to exactly match the power/ground mesh on the corresponding slice, in a process that is not the subject of the present invention.
- the system loads into memory the definition of the RCELL Mega cell that is to be placed onto the slice (step 1200 ).
- the system determines the snap boundaries of the RCELL Mega cell (step 1202 ).
- a user may provide a suggested target on the slice for the RCELL Mega cell (step 1204 ).
- the system then scans the slice definition for diffused locations on the slice that closely match the selected RCELL Mega cell (step 1206 ), and that are closest to the suggested location (if the user suggestion option is enabled).
- the system locates the closest available diffused location on the slice (step 1208 ).
- the system orients the RCELL Mega cell to match the power/ground grid of the cell to that of the slice (step 1210 ).
- the system maps the RCELL Mega cell to the diffused location (step 1212 ), and snaps the target point of the RCELL Mega cell to the power grid of the slice (step 1214 ). Since the power/ground mesh of the RCELL Mega cell is lined up with the power/ground mesh of the slice, the RCELL Mega cell is guaranteed to be over a legal base array.
- diffused Mega cells can only be placed in specific sites or areas on the target slice.
- the specific “legal” sites are pre-diffused areas. Typically, these sites allow the placement of Mega cells with multiple orientations. Additionally, some Mega cells may overlap multiple diffused areas. Such Mega cells contain multiple sites that may include several groupings of sites at the chip level. There may be a complex relationship between the orientation of the sites within the Mega cell and those on the slice.
- the system To place diffused Mega cells, the system must identify a matching group of sites on the slice that exactly match the grouping and orientation of the Mega cell. First, the system scans the slice definition to identify pre-diffused locations on the slice (step 1300 ). Next, the system loads the diffused Mega cell to be placed (step 1302 ). The system determines the parameters of the Mega cell to be placed (step 1304 ). The system searches all of the pre-diffused locations to find a matching site grouping that exactly matches the grouping and orientation of the Mega cell (step 1306 ). Once the system identifies an exact match, the diffused Mega cell is mapped to the location (step 1308 ), and the target point is snapped to the power/ground mesh of the slice (step 1310 ).
- the search for an exact match is exhaustive, meaning that all possible diffused locations are considered, and all legal orientations and placements of the Mega cell are determined to find the best possible match.
- the processing time required to identify the matching location is less than 10 milliseconds per Mega cell on a processor with a clock speed of approximately 1 GigaHertz for a typical slice. Thus, processing time is not significant.
- the auto-interactive placement algorithm provided within the placement software application enables designers to automatically place complex logic functions on a pre-fabricated slice with little or no knowledge of the configuration of the slice. Specifically, the designer need not be concerned with the complex electrical and manufacturing design rules involved in the placement. Since the placement of cells is correct at the time of the logical to physical mapping by means of the exhaustive placement algorithms, costly design iterations are eliminated, which ordinarily are occasioned by discovery of design rule violations by other design tools in later phases of the design process.
- the pre-fabricated slice can utilize a default base array power/ground grid or a custom grid, depending on the implementation.
- Each grid line is a valid placement location for an element. This allows other design tools to be used with the present invention.
- a legalizer algorithm within the system simply snaps the cells onto a valid gate array placement site.
- the system can be implemented either as a standalone tool (or executable) or as an option to another design tool, which could run the legalizing function after placement if the technology is gate array.
- the designer would call the legalizer function of the system as an option after placing the cells.
- the legalizer would then analyze the placement, and snap the various placed cells to the closest, legal target locations on the slice.
Abstract
Description
# The following returns the lower left X | ||
location of the nearest non-flipped acell site | ||
# within the given row | ||
def | ||
FindNearestNonFlippedAcellSite(self,x_loc,row): |
if (self.cell_sites_back_to_back): |
if ((row.rowtype == “Normal”) and | |
(self.row_normal_cell_site_flipped_first)) | |
or ((row.rowtype == “Flipped”) | |
and | |
(self.row_flipped_cell_site_flipped_first))): |
non_flip_acell_site = |
self.SnapNearestOdd(x_loc,self.acell_width, | |
row.outline.llx) |
else: | |
non_flip_acell_site = |
self.SnapNearestEven(x_loc,self.acell— | |
width,row.outline.llx) |
else: |
non_flip_acell_site = |
self.SnapNearest(x_loc,self.acell_width, | |
row.outline.llx) |
return non_flip_acell_site | ||
The above code returns a non-flipped cell site location to the calling function. The next code block snaps the cell element to the power/ground grid of the slice.
# The following snaps the orig_loc to the | ||
nearest multiple of the grid. | ||
# The grid is defined by “grid” and “offset” | ||
variables | ||
def SnapNearest(self,orig_loc,grid,offset): |
... . |
# The following snaps the orig_loc to the | |
nearest odd multiple of the grid. | |
# The grid is defined by the “grid” and “offset” | |
variables | |
def SnapNearestOdd(self,orig_loc,grid,offset): |
... . |
# The following snaps the orig_loc to the | |
nearest even multiple of the grid. | |
# The grid is defined by the “grid” and “offset” | |
variables | |
def SnapNearestEven(self,orig_loc,grid,offset): |
... . | ||
Claims (20)
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US10/740,284 US7269803B2 (en) | 2003-12-18 | 2003-12-18 | System and method for mapping logical components to physical locations in an integrated circuit design environment |
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US10/740,284 US7269803B2 (en) | 2003-12-18 | 2003-12-18 | System and method for mapping logical components to physical locations in an integrated circuit design environment |
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US20050138595A1 US20050138595A1 (en) | 2005-06-23 |
US7269803B2 true US7269803B2 (en) | 2007-09-11 |
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US10/740,284 Expired - Fee Related US7269803B2 (en) | 2003-12-18 | 2003-12-18 | System and method for mapping logical components to physical locations in an integrated circuit design environment |
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US20090249274A1 (en) * | 2008-03-25 | 2009-10-01 | Chien-Cheng Liu | Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof |
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Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5124776A (en) * | 1989-03-14 | 1992-06-23 | Fujitsu Limited | Bipolar integrated circuit having a unit block structure |
US5283753A (en) * | 1991-07-25 | 1994-02-01 | Motorola, Inc. | Firm function block for a programmable block architected heterogeneous integrated circuit |
US5737236A (en) * | 1996-02-08 | 1998-04-07 | Motorola, Inc. | Apparatus and method for the automatic determination of a standard library height within an integrated circuit design |
US5910899A (en) * | 1996-10-25 | 1999-06-08 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same |
US6054872A (en) * | 1996-12-27 | 2000-04-25 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit with mixed gate array and standard cell |
US6127874A (en) * | 1996-09-30 | 2000-10-03 | Kabushiki Kaisha Toshiba | Skew adjustable IC and a method for designing the same |
US6189131B1 (en) * | 1998-01-14 | 2001-02-13 | Lsi Logic Corporation | Method of selecting and synthesizing metal interconnect wires in integrated circuits |
US6334207B1 (en) | 1998-03-30 | 2001-12-25 | Lsi Logic Corporation | Method for designing application specific integrated circuits |
US6467074B1 (en) | 2000-03-21 | 2002-10-15 | Ammocore Technology, Inc. | Integrated circuit architecture with standard blocks |
US6470482B1 (en) * | 1990-04-06 | 2002-10-22 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US6480989B2 (en) * | 1998-06-29 | 2002-11-12 | Lsi Logic Corporation | Integrated circuit design incorporating a power mesh |
US6516457B1 (en) * | 1999-07-07 | 2003-02-04 | Nec Corporation | Method and system of data processing for designing a semiconductor device |
US6536028B1 (en) | 2000-03-14 | 2003-03-18 | Ammocore Technologies, Inc. | Standard block architecture for integrated circuit design |
US6578174B2 (en) | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
US6601228B1 (en) * | 1998-01-21 | 2003-07-29 | Micron Technology, Inc. | Method for modifying an integrated circuit |
US6611045B2 (en) * | 2001-06-04 | 2003-08-26 | Motorola, Inc. | Method of forming an integrated circuit device using dummy features and structure thereof |
US20030233628A1 (en) * | 2002-06-17 | 2003-12-18 | Rana Amar Pal Singh | Technology dependent transformations in CMOS and silicon-on-insulator during digital design synthesis |
US6760896B2 (en) | 2002-09-25 | 2004-07-06 | Lsi Logic Corporation | Process layout of buffer modules in integrated circuits |
US6779158B2 (en) | 2001-06-15 | 2004-08-17 | Science & Technology Corporation @ Unm | Digital logic optimization using selection operators |
US6823499B1 (en) * | 2001-09-18 | 2004-11-23 | Lsi Logic Corporation | Method for designing application specific integrated circuit structure |
US20050034086A1 (en) * | 2003-08-04 | 2005-02-10 | Hamlin Christopher L. | Method and apparatus for mapping platform-based design to multiple foundry processes |
US20050034087A1 (en) * | 2003-08-04 | 2005-02-10 | Hamlin Christopher L. | Method and apparatus for mapping platform-based design to multiple foundry processes |
US20050114818A1 (en) * | 2003-11-21 | 2005-05-26 | Lsi Logic Corporation | Chip design command processor |
US20050116738A1 (en) * | 2003-12-01 | 2005-06-02 | Lsi Logic Corporation | Integrated circuits, and design and manufacture thereof |
US7003738B2 (en) * | 2000-06-30 | 2006-02-21 | Zenasis Technologies, Inc. | Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process |
US7043713B2 (en) * | 2000-02-25 | 2006-05-09 | Lightspeed Semiconductor Corp. | Implementing programmable logic array embedded in mask-programmed ASIC |
-
2003
- 2003-12-18 US US10/740,284 patent/US7269803B2/en not_active Expired - Fee Related
Patent Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5124776A (en) * | 1989-03-14 | 1992-06-23 | Fujitsu Limited | Bipolar integrated circuit having a unit block structure |
US6470482B1 (en) * | 1990-04-06 | 2002-10-22 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US5283753A (en) * | 1991-07-25 | 1994-02-01 | Motorola, Inc. | Firm function block for a programmable block architected heterogeneous integrated circuit |
US5737236A (en) * | 1996-02-08 | 1998-04-07 | Motorola, Inc. | Apparatus and method for the automatic determination of a standard library height within an integrated circuit design |
US6127874A (en) * | 1996-09-30 | 2000-10-03 | Kabushiki Kaisha Toshiba | Skew adjustable IC and a method for designing the same |
US5910899A (en) * | 1996-10-25 | 1999-06-08 | Advanced Micro Devices, Inc. | Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same |
US6054872A (en) * | 1996-12-27 | 2000-04-25 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit with mixed gate array and standard cell |
US6189131B1 (en) * | 1998-01-14 | 2001-02-13 | Lsi Logic Corporation | Method of selecting and synthesizing metal interconnect wires in integrated circuits |
US6601228B1 (en) * | 1998-01-21 | 2003-07-29 | Micron Technology, Inc. | Method for modifying an integrated circuit |
US6334207B1 (en) | 1998-03-30 | 2001-12-25 | Lsi Logic Corporation | Method for designing application specific integrated circuits |
US6480989B2 (en) * | 1998-06-29 | 2002-11-12 | Lsi Logic Corporation | Integrated circuit design incorporating a power mesh |
US6516457B1 (en) * | 1999-07-07 | 2003-02-04 | Nec Corporation | Method and system of data processing for designing a semiconductor device |
US7043713B2 (en) * | 2000-02-25 | 2006-05-09 | Lightspeed Semiconductor Corp. | Implementing programmable logic array embedded in mask-programmed ASIC |
US6536028B1 (en) | 2000-03-14 | 2003-03-18 | Ammocore Technologies, Inc. | Standard block architecture for integrated circuit design |
US6467074B1 (en) | 2000-03-21 | 2002-10-15 | Ammocore Technology, Inc. | Integrated circuit architecture with standard blocks |
US7003738B2 (en) * | 2000-06-30 | 2006-02-21 | Zenasis Technologies, Inc. | Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process |
US6611045B2 (en) * | 2001-06-04 | 2003-08-26 | Motorola, Inc. | Method of forming an integrated circuit device using dummy features and structure thereof |
US6578174B2 (en) | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
US6779158B2 (en) | 2001-06-15 | 2004-08-17 | Science & Technology Corporation @ Unm | Digital logic optimization using selection operators |
US6792589B2 (en) | 2001-06-15 | 2004-09-14 | Science & Technology Corporation @ Unm | Digital design using selection operations |
US6823499B1 (en) * | 2001-09-18 | 2004-11-23 | Lsi Logic Corporation | Method for designing application specific integrated circuit structure |
US20030233628A1 (en) * | 2002-06-17 | 2003-12-18 | Rana Amar Pal Singh | Technology dependent transformations in CMOS and silicon-on-insulator during digital design synthesis |
US6760896B2 (en) | 2002-09-25 | 2004-07-06 | Lsi Logic Corporation | Process layout of buffer modules in integrated circuits |
US20050034087A1 (en) * | 2003-08-04 | 2005-02-10 | Hamlin Christopher L. | Method and apparatus for mapping platform-based design to multiple foundry processes |
US20050034086A1 (en) * | 2003-08-04 | 2005-02-10 | Hamlin Christopher L. | Method and apparatus for mapping platform-based design to multiple foundry processes |
US20050114818A1 (en) * | 2003-11-21 | 2005-05-26 | Lsi Logic Corporation | Chip design command processor |
US20050116738A1 (en) * | 2003-12-01 | 2005-06-02 | Lsi Logic Corporation | Integrated circuits, and design and manufacture thereof |
Non-Patent Citations (5)
Title |
---|
H. Zacatelco et al.; "AnGeLa: A Smart Tool for the Automatic Layout Generation of Analog Cells," IEEE Transactions 1996, pp. 282-285. |
H. Zheng et al.; "Modular Verification of Timed Circuits Using Automatic Abstraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 9, Sep. 2003, pp. 1138-1153. |
M. L. Anido et al.; "TEDMOS-A CAD System for ASIC Design on IBM(R)-PC like Computers," IEEE Transactions 1994, pp. 420-427. |
McMacken, J. and Chamberlain, S.; "CHORD: A Modular Semiconductor Device Simulation Development Tool Incorporating External Network Models," IEEE Transactions on Computer-Aided Design, vol. 8, No. 8, Aug. 1989, pp. 826-836. |
P. Agrawal.; "Emerging Technologies for Electronic Design and Test," IEEE Transactions 1994, p. 18. |
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US8549455B2 (en) | 2007-08-02 | 2013-10-01 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8759882B2 (en) | 2007-08-02 | 2014-06-24 | Tela Innovations, Inc. | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos |
US10734383B2 (en) | 2007-10-26 | 2020-08-04 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8680626B2 (en) | 2007-10-26 | 2014-03-25 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
US8951916B2 (en) | 2007-12-13 | 2015-02-10 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US10461081B2 (en) | 2007-12-13 | 2019-10-29 | Tel Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9818747B2 (en) | 2007-12-13 | 2017-11-14 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9281371B2 (en) | 2007-12-13 | 2016-03-08 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9530734B2 (en) | 2008-01-31 | 2016-12-27 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US8701071B2 (en) | 2008-01-31 | 2014-04-15 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US9202779B2 (en) | 2008-01-31 | 2015-12-01 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US10020321B2 (en) | 2008-03-13 | 2018-07-10 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on two gate electrode tracks |
US8785979B2 (en) | 2008-03-13 | 2014-07-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer |
US8772839B2 (en) | 2008-03-13 | 2014-07-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8836045B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track |
US8735944B2 (en) | 2008-03-13 | 2014-05-27 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors |
US8735995B2 (en) | 2008-03-13 | 2014-05-27 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track |
US8742462B2 (en) | 2008-03-13 | 2014-06-03 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications |
US9117050B2 (en) | 2008-03-13 | 2015-08-25 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications |
US9536899B2 (en) | 2008-03-13 | 2017-01-03 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US20100187627A1 (en) * | 2008-03-13 | 2010-07-29 | Tela Innovations, Inc. | Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes |
US8785978B2 (en) | 2008-03-13 | 2014-07-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer |
US8847329B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts |
US9208279B2 (en) | 2008-03-13 | 2015-12-08 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods |
US8587034B2 (en) | 2008-03-13 | 2013-11-19 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8729643B2 (en) | 2008-03-13 | 2014-05-20 | Tela Innovations, Inc. | Cross-coupled transistor circuit including offset inner gate contacts |
US8729606B2 (en) | 2008-03-13 | 2014-05-20 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels |
US9245081B2 (en) | 2008-03-13 | 2016-01-26 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods |
US10727252B2 (en) | 2008-03-13 | 2020-07-28 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US10658385B2 (en) | 2008-03-13 | 2020-05-19 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on four gate electrode tracks |
US8872283B2 (en) | 2008-03-13 | 2014-10-28 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature |
US10651200B2 (en) | 2008-03-13 | 2020-05-12 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on three gate electrode tracks |
US8680583B2 (en) | 2008-03-13 | 2014-03-25 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels |
US8835989B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications |
US8853793B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends |
US8669594B2 (en) | 2008-03-13 | 2014-03-11 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels |
US8669595B2 (en) | 2008-03-13 | 2014-03-11 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications |
US8853794B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit within semiconductor chip including cross-coupled transistor configuration |
US9081931B2 (en) | 2008-03-13 | 2015-07-14 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer |
US8742463B2 (en) | 2008-03-13 | 2014-06-03 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts |
US8866197B2 (en) | 2008-03-13 | 2014-10-21 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature |
US8581304B2 (en) | 2008-03-13 | 2013-11-12 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships |
US8592872B2 (en) | 2008-03-13 | 2013-11-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature |
US8575706B2 (en) | 2008-03-13 | 2013-11-05 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode |
US9213792B2 (en) | 2008-03-13 | 2015-12-15 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods |
US8552508B2 (en) | 2008-03-13 | 2013-10-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer |
US8847331B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures |
US8581303B2 (en) | 2008-03-13 | 2013-11-12 | Tela Innovations, Inc. | Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer |
US8552509B2 (en) | 2008-03-13 | 2013-10-08 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors |
US8569841B2 (en) | 2008-03-13 | 2013-10-29 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel |
US8816402B2 (en) | 2008-03-13 | 2014-08-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor |
US8558322B2 (en) | 2008-03-13 | 2013-10-15 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature |
US8564071B2 (en) | 2008-03-13 | 2013-10-22 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact |
US9871056B2 (en) | 2008-03-13 | 2018-01-16 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
US8046728B2 (en) * | 2008-03-25 | 2011-10-25 | Realtek Semiconductor Corp. | Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof |
US20090249274A1 (en) * | 2008-03-25 | 2009-10-01 | Chien-Cheng Liu | Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof |
US8759985B2 (en) | 2008-03-27 | 2014-06-24 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US9779200B2 (en) | 2008-03-27 | 2017-10-03 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US9390215B2 (en) | 2008-03-27 | 2016-07-12 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8471391B2 (en) | 2008-03-27 | 2013-06-25 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8863063B2 (en) | 2009-05-06 | 2014-10-14 | Tela Innovations, Inc. | Finfet transistor circuit |
US10446536B2 (en) | 2009-05-06 | 2019-10-15 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US20140167117A1 (en) * | 2009-10-13 | 2014-06-19 | Tela Innovations, Inc. | Methods for Cell Boundary Encroachment and Layouts Implementing the Same |
US20110084312A1 (en) * | 2009-10-13 | 2011-04-14 | Tela Innovations, Inc. | Methods for Cell Boundary Encroachment and Layouts Implementing the Same |
US8661392B2 (en) * | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9269702B2 (en) * | 2009-10-13 | 2016-02-23 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the same |
US20170104004A1 (en) * | 2009-10-13 | 2017-04-13 | Tela Innovations, Inc. | Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same |
US9530795B2 (en) * | 2009-10-13 | 2016-12-27 | Tela Innovations, Inc. | Methods for cell boundary encroachment and semiconductor devices implementing the same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US9704845B2 (en) | 2010-11-12 | 2017-07-11 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
CN105095531B (en) * | 2014-04-15 | 2018-07-20 | 台湾积体电路制造股份有限公司 | The implementation method and device of device analysis |
CN105095531A (en) * | 2014-04-15 | 2015-11-25 | 台湾积体电路制造股份有限公司 | Method and device for realizing device analysis |
US11182533B2 (en) * | 2017-08-30 | 2021-11-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard cells and variations thereof within a standard cell library |
US11704472B2 (en) * | 2017-08-30 | 2023-07-18 | Taiwan Semiconductor Manufacutring Co., Ltd. | Standard cells and variations thereof within a standard cell library |
US20220067266A1 (en) * | 2017-08-30 | 2022-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard cells and variations thereof within a standard cell library |
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