US7411407B2 - Testing target resistances in circuit assemblies - Google Patents
Testing target resistances in circuit assemblies Download PDFInfo
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- US7411407B2 US7411407B2 US11/581,203 US58120306A US7411407B2 US 7411407 B2 US7411407 B2 US 7411407B2 US 58120306 A US58120306 A US 58120306A US 7411407 B2 US7411407 B2 US 7411407B2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
Definitions
- I/O data interfaces often now use passive elements (such as termination resistors and coupling capacitors) to satisfy the signal integrity requirements of high-frequency data signals.
- Some circuits use surface mount passive devices that can be difficult to place and solder correctly given their compact size.
- keeping up with test requirements is expensive, particularly when it is not possible to physically access nodes to be tested (for example, when the node exists on a printed circuit board trace that is on a surface obscured by other components or boards or when the node comprises a solder joint intended to couple a small (in size) surface mount resistor).
- Such nodes often either are not tested at all or are tested using indirect access methods, which typically have long test times and less than ideal resolution.
- An embodiment of a system includes a circuit assembly having an integrated circuit (IC) and a circuit external to the IC.
- the IC comprises test circuitry used to observe data indicative of target resistances associated with the external circuit.
- the system evaluates the data to determine target resistance values.
- An alternative embodiment of a system for determining a target resistance of an external circuit coupled to an IC comprises an IC with test circuitry, a first data store, a second data store, and logic.
- the test circuitry applies a reference voltage that varies over time and first and second output voltages that are different from each other.
- the first data store records a representation of a first reference voltage responsive to a first stimulus from within the IC when the reference voltage is substantially equal to the first output voltage.
- the second data store records a representation of a second reference voltage responsive to a second stimulus from within the IC when the reference voltage is substantially equal to the second output voltage.
- the logic determines first and second values associated with an electrical characteristic of the external circuit responsive to the first and second reference voltages.
- An embodiment of an IC enabled method for determining an electrical characteristic in a circuit assembly of a coupled circuit external to the IC comprises the steps of providing a reference voltage that varies in magnitude over time, providing a first input that directs the IC to transmit a first output voltage to a circuit external to the IC, monitoring the first output voltage within the IC, generating a first signal when the first output voltage is substantially equal to the reference voltage, storing the magnitude of the reference voltage responsive to the first signal, replacing the first input with a second input that directs the IC to transmit a second output voltage different from the first output voltage to the circuit external to the IC, monitoring the second output voltage within the IC, generating a second signal when the second output voltage is substantially equal to the reference voltage, storing the magnitude of the reference voltage responsive to the second signal and determining a value of an electrical characteristic of the circuit external to the IC responsive to the first and second input signals and the reference voltage.
- FIG. 1 is a schematic diagram depicting an embodiment of a circuit assembly.
- FIG. 2 is a flow diagram depicting an embodiment of a method for determining a target resistance on an external device.
- FIG. 3 is a circuit schematic of an embodiment of the pad circuitry of the IC of the circuit assembly of FIG. 1 .
- FIG. 4 is a circuit schematic of an alternative embodiment of the pad circuitry illustrated in FIG. 3 .
- FIGS. 5A and 5B are graphs illustrating how a voltage is determined by the IC of FIG. 1 .
- FIG. 6A is an embodiment of a circuit diagram depicting resistances along a path of a logic high signal transmitted by the IC of FIG. 1 .
- FIG. 6B is an embodiment of a circuit diagram depicting resistances along a path of a logic low signal transmitted by the IC of FIG. 1 .
- FIG. 6C is an embodiment of a circuit diagram depicting resistances in an input termination network on the IC of FIG. 1 .
- FIGS. 7A and 7B are graphs illustrating how a voltage is determined by an IC using the circuit of FIG. 6C .
- FIGS. 8A and 8B are flow diagrams depicting an embodiment of a method for testing target resistances.
- FIG. 9 is a flow diagram depicting an embodiment of an alternative method for testing target resistances.
- a test system includes a circuit assembly having an IC and an external circuit.
- the IC comprises test circuitry used to observe data indicative of target resistances associated with the external circuit.
- the test system evaluates the data to determine target resistance values.
- a first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit.
- a second embodiment disables a driver on the IC, controllably fixes a pull-down termination element in the IC, controllably sweeps a pull-up termination element in the IC until the voltage at a node between the termination elements and coupled to the external circuit exceeds a reference voltage.
- the IC is configured such that the IC provides both the measurement stimuli and receives the measurement results. Consequently, the IC can be used to check both the existence and an appropriate value of a target resistance as seen by the IC along a connection that couples the IC to an external circuit or circuit device without the need for expensive test equipment.
- the external device can be a receiver circuit coupled to the IC.
- the receiver can be embodied on a printed circuit board that hosts both the IC and the receiver circuit. Alternatively, the receiver can be embodied on a separate printed circuit board coupled to the IC via a wire or other flexible conductor.
- a direct-coupled (DC) reference voltage is compared with an input signal.
- a measurement stimulus is generated when the input signal exceeds the reference voltage.
- the system responds by identifying the reference voltage level that produced the measurement stimulus.
- the reference voltage level is recorded in a data storage element within the IC. Alternatively or additionally, the reference voltage level can be sent to a storage element external to the IC.
- test circuitry within the IC is arranged to determine target resistance values associated with the receiver circuit within the external circuit or circuit device. In other embodiments, the test circuitry within the IC is arranged to identify a fault condition within the signal termination element(s) of the external device.
- a representative circuit assembly 100 includes IC 110 and external circuit 150 .
- IC 110 includes core 112 , which incorporates combinational logic 114 and electrically communicates with external circuit 150 via pad 116 .
- Pad 116 and core 112 are coupled via connection 128 , which provides a medium for one or more data signals.
- pad 116 Although only a single pad 116 is shown in the illustrated embodiment, it will be understood that typical integrated circuits will comprise a host of pads to receive one or more supply voltages, one or more clock signals, provide an electrical ground, and enable additional data signals to be communicated with one or more additional external devices (not shown).
- Pad 116 includes contact site 120 and pad circuitry 122 .
- Contact site 120 couples the IC 110 via conductor 123 with external circuit 150 .
- Pad circuitry 122 cooperates with the contact site 120 to enable electrical communication between components of the IC and components external to the IC.
- pad circuitry 122 may include one or more receivers, for receiving signals provided to pad 116 from external devices, and one or more drivers, for providing signals from pad 116 to external devices.
- integrated circuit 110 includes test circuitry 130 .
- Test circuitry 130 communicates with core 112 via conductor 132 and with pad 116 via multiple connections.
- Test circuitry 130 provides a voltage, V REF , via conductor 140 to pad 116 .
- Test circuitry 130 receives a measurement stimulus signal, COMPARE, via conductor 160 from pad 116 .
- one or more additional control and data signals are communicated via connection 126 between pad 116 and test circuitry 130 .
- test circuitry 130 resides outside core 112 and outside pad 116 . It should be noted that various other arrangements of test circuitry 130 may be used, such as arranging the test circuitry 130 within core 112 and/or within pad 116 . Moreover, test circuitry 130 may be configured to communicate with external test equipment (not shown) via one or more pads other than pad 116 .
- IC 110 can verify and quantify the values of termination elements, such as R TERM1 152 and R TERM2 154 , used to provide signal termination in external circuit 150 . It is significant to note that while termination elements 152 , 154 illustrated in FIG. 1 are shown as integrated (i.e., internal) devices, these elements can be discrete devices such as resistors or transistors coupled to conductor 123 on a printed circuit board or some other assembly between external circuit 150 and IC 110 .
- termination elements 152 , 154 illustrated in FIG. 1 are shown as integrated (i.e., internal) devices, these elements can be discrete devices such as resistors or transistors coupled to conductor 123 on a printed circuit board or some other assembly between external circuit 150 and IC 110 .
- the flow diagram of FIG. 2 shows an embodiment of a method 200 for identifying a target resistance that can be implemented by the circuit assembly 100 of FIG. 1 .
- profile data corresponding to the circuit assembly 100 ( FIG. 1 ) to be tested is received.
- profile data may include, but is not limited to, information relating to the type of IC and/or electrical continuity information corresponding to the interconnection of IC 110 ( FIG. 1 ) with external circuit 150 ( FIG. 1 ) and perhaps other devices.
- the profile data may be provided in numerous manners, such as by being provided in the form of an operator input at a work station or via a netlist or other representation of the circuit of interest in response to a test initiation signal.
- method 200 proceeds to block 204 where the profile data is evaluated, i.e., a determination is made as to what tests should be performed on a select connection of the circuit assembly 100 .
- test parameters are provided to an IC 110 within the circuit assembly 100 to direct test circuitry 130 within IC 110 to collect data regarding electrical characteristics associated with conductor 123 between IC 110 and external circuit 150 .
- Test parameters include appropriate signals to facilitate resistance testing.
- test circuitry in the IC is used to observe data indicative of a target resistance associated with an external device (e.g., external circuit 150 ) coupled to IC 110 .
- Data is received, such as by the test circuitry 130 , with the data being received in any suitable manner, e.g., intermittently throughout the testing cycle, or after testing has been completed.
- the received data is evaluated to identify a value of a target resistance. It will be understood that subsequent to the data evaluation in block 210 , the test circuitry 130 or a device external to the IC 110 can be programmed to make a determination that the IC 110 and the coupled external circuit 150 are functioning as desired.
- FIG. 3 illustrates a circuit schematic depicting an embodiment of the pad circuitry 122 of IC 110 .
- IC 110 includes contact site 120 , pad circuitry 122 , and test circuitry 130 .
- Conductor 123 couples contact site 120 to external circuit 150 .
- External circuit 150 can be another integrated circuit separate from IC 110 or some other circuit component in communication with IC 110 .
- Test circuitry 130 includes voltage generator 350 , which produces reference voltage, V REF .
- the reference voltage is supplied via conductor 140 to pad circuitry 122 .
- Voltage generator 350 can be a digital-to-analog converter (DAC), or any of a number of other devices configured to provide a controllable DC voltage.
- DAC digital-to-analog converter
- Pad circuitry 122 includes driver 310 , comparator 320 , and D flip-flop 330 .
- Pad circuitry 122 receives an input along conductor 305 coupled to an input of driver 310 .
- the output of driver 310 is coupled via conductor 315 , contact site 120 , and conductor 123 on its way to external circuit 150 .
- Conductor 315 further couples the output of driver 310 to an input of comparator 320 .
- the remaining input of comparator 320 is coupled via switch 345 to receive V REF .
- the output of comparator 320 i.e., a digital signal labeled “COMPARE” is forwarded along conductor 325 to D flip-flop 330 , which latches the comparator result, thus generating signal Q.
- Conductor 160 forwards signal Q to one or more devices configured to determine the voltage level of V REF that caused the steady-state value of the comparator to change.
- the COMPARE signal may be directly forwarded to these one or more devices.
- the described one or more devices may comprise data stores such as registers 352 , 354 in communication with a DAC in voltage generator 350 , a register within test circuitry 130 and external to the voltage generator, or a register within pad circuitry 122 .
- Register 352 is configured to receive a representation of the reference voltage when COMPARE or signal Q changes state. Thus, register 352 records the digital value that generated V REF when V REF is substantially equal to V OUT when INPUT is set to direct driver 310 to drive a first voltage to external circuit 150 .
- register 354 is configured to receive a representation of the reference voltage when COMPARE or signal Q changes state. Register 354 records the digital value that generated V REF when V REF is substantially equal to V OUT when INPUT is set to direct driver 310 to drive a second voltage to external circuit 150 .
- registers 352 , 354 can be configured external to the voltage generator 350 and within test circuitry 130 .
- registers 352 , 354 can be configured in pad circuitry 122 or within other portions of IC 110 .
- Test circuitry 130 further includes logic 360 .
- Logic 360 is configured to solve one or more equations responsive to the values in registers 352 , 354 to determine resistance values associated with external circuit 150 . More specifically, logic 360 determines resistance values for resistors R RTERM1 1152 and R RTERM2 154 .
- switch 345 can be controlled to receive V REF from a voltage generator configured within IC 110 .
- switch 345 can be controlled to receive V REF from a voltage generator external to IC 110 via conductor 355 .
- the reference voltage could be provided by an analog power supply among other devices.
- a receiver circuit, associated with driver 310 can be used as the comparator 320 so that test circuitry 130 does not require dedicated IC area.
- a scan register associated with the receiver can be used to capture the receiver output. Since each receiver typically has its own scan register (as per IEEE Standard 1149.1, for example), many target resistances may be tested simultaneously.
- INPUT is driven by driver 310 to provide a driven signal V OUT1 to external circuit 150 via contact site 120 and conductor 123 .
- V OUT1 is coupled to comparator 320 .
- Comparator 320 compares V OUT1 to a controllably adjustable reference signal V REF .
- the comparator 320 outputs a logic 1 when the reference signal V REF exceeds the sampled signal V OUT1 .
- the output of the comparator, COMPARE is captured by D flip-flop 330 and/or forwarded to register 352 and perhaps other devices configured to store a representation of the reference voltage level that caused the output of comparator 320 to change its steady-state value.
- INPUT is driven by driver 310 to provide a driven signal V OUT2 to external circuit 150 via contact site 120 and conductor 123 .
- the voltage level of V OUT2 is not equal to that of V OUT1 .
- V OUT2 is coupled to comparator 320 .
- Comparator 320 compares V OUT2 to a controllably adjustable reference signal V REF .
- the comparator 320 outputs a logic 1 when the reference signal V REF exceeds the sampled signal V OUT2 .
- the output of the comparator, COMPARE is captured by D flip-flop 330 and/or forwarded to register 354 and perhaps other devices configured to store a representation of the reference voltage level that caused the output of comparator 320 to change its steady-state value.
- FIG. 4 illustrates a circuit schematic depicting an alternative embodiment of the pad circuitry 122 of IC 110 .
- IC 110 includes contact site 120 , pad circuitry 422 , and test circuitry 130 .
- Conductor 123 couples contact site 120 to external circuit 150 .
- Test circuitry 130 includes voltage generator 350 , which produces reference voltage, V REF , and reference voltage, DATA REF .
- V REF is supplied via conductor 140 to pad circuitry 122 .
- DATA REF is supplied via conductor 415 to pad circuitry 122 .
- Pad circuitry 122 includes driver 310 , receiver 420 , D flip-flop 430 , comparator 440 , and multiplexor 450 .
- Pad circuitry 122 receives a signal labeled “INPUT” along conductor 305 , which is coupled to an input of driver 310 .
- the output of driver 310 is coupled via conductor 315 , contact site 120 , and conductor 123 to external circuit 150 .
- Conductor 315 further connects the output of driver 310 to an input of receiver 420 and an input of comparator 440 .
- the remaining input of receiver 420 is coupled via conductor 415 to receive DATA REF .
- the remaining input of comparator 440 is coupled via conductor 140 to receive V REF .
- receiver 420 produces a digital signal labeled “DATA COMPARE” that is forwarded along conductor 425 to D flip-flop 430 .
- D flip-flop 430 latches DATA COMPARE, thus generating signal Q.
- Conductor 160 forwards signal Q to one or more devices configured to receive the data signal.
- the output of comparator 440 generates a digital signal labeled “TEST COMPARE” that is forwarded along conductor 445 to multiplexor 450 .
- Multiplexor 450 selects between TEST COMPARE and DATA COMPARE to generate signal TEST OUT.
- Conductor 460 forwards TEST OUT to one or more devices configured to determine the voltage level of V REF or DATA REF that caused the steady-state value of the associated comparator to change.
- the described one or more devices may comprise data stores such as registers 352 , 354 in communication with a DAC in voltage generator 350 (not shown), one or more registers within test circuitry 130 and external to the voltage generator, or one or more registers within a device external to IC 110 .
- INPUT is driven by driver 310 to provide a driven signal V OUT1 to external circuit 150 via contact site 120 and conductor 123 .
- V OUT1 is sampled or otherwise monitored by receiver 420 and comparator 440 .
- Comparator 440 compares the sampled signal V OUT1 to a controllable reference signal V REF .
- the comparator 440 outputs a logic 1 when the reference signal V REF exceeds the sampled signal V OUT1 .
- the output of the comparator, TEST COMPARE is captured by multiplexor 450 and output to register 352 to store a representation of the reference voltage level that caused the output of comparator 440 to change its steady-state value.
- INPUT is driven by driver 310 to provide a driven signal V OUT2 to external circuit 150 via contact site 120 and conductor 123 .
- the voltage level of V OUT2 is not equal to that of V OUT1 .
- V OUT2 is coupled to comparator 440 .
- Comparator 440 compares V OUT2 to a controllably adjustable reference signal V REF .
- the comparator 440 outputs a logic 1 when the reference signal V REF exceeds the sampled signal V OUT2 .
- the output of the comparator, TEST COMPARE is captured by multiplexor 450 and forwarded to register 354 and perhaps other devices configured to store a representation of the reference voltage level that caused the output of comparator 440 to change its steady-state value.
- a test system further includes logic 360 .
- Logic 360 is provided external to IC 110 and is coupled via connection 435 to receive the values in registers 352 , 354 .
- Logic 360 is configured to solve one or more equations responsive to the values in registers 352 , 354 to determine resistance values associated with external circuit 150 . More specifically, logic 470 determines resistance values for resistors R RTERM1 152 and R RTERM2 154 .
- FIGS. 5A and 5B are graphs 500 and 510 that illustrate how a voltage V OUT corresponding to a voltage output by IC 110 ( FIG. 1 ) is determined.
- Graphs 500 and 510 illustrate increasing voltage from the bottom to the top of the graph with time increasing from left to right across the figures.
- V REF 502 increases step-wise linearly from 0 volts to approximately V DD .
- IC 110 When directed to output a high voltage signal, IC 110 generates V OUT ( FIG. 3 ), which in turn drives V X1 in external circuit 150 ( FIG. 3 ).
- Signal V OUT is represented by trace 504 .
- V OUT 504 is substantially equal to V REF 502 .
- trace 512 representing COMPARE transitions from logic 0 to a logic 1.
- COMPARE can be used to direct test circuitry 130 to store a first value equal to the magnitude of V REF 502 when V REF 502 is substantially equal to V OUT 504 .
- V REF 502 can be initially set to V DD and decreased step-wise linearly over time until it is determined that V REF 502 and V OUT 504 are substantially equal.
- COMPARE can be initially set to a logic 1 with test circuitry 130 configured to store a first value when COMPARE transitions to logic 0. Whether V REF 502 is adjusted to increase or decrease over time and whether test circuitry 130 is configured to react to COMPARE when COMPARE transitions from low to high voltage or when COMPARE transitions from high to low voltage, a second value can be identified and stored when V OUT 504 is adjusted to a different voltage level. In this way, the first and second values are associated with a logic high and a logic low, respectively. In an alternative embodiment, the first value is associated with a logic low and the second value is associated with a logic high.
- FIG. 6A is a schematic diagram illustrating a circuit 600 that models a connection between IC 110 and external circuit 150 .
- the connection between IC 110 and external circuit 150 is represented by a resistive network comprising resistor R STERM1 602 (the series resistance of the driver 310 to V DD ), R PCB 604 (the resistance of the conductor between driver 310 and external circuit 150 ), and resistors R RTERM1 152 and R RTERM2 154 in the external circuit 150 .
- the resistive network further comprises a node between resistance R PCB 604 , resistor R RTERM1 152 , and resistor R RTERM2 154 .
- a voltage V X1 is associated with this node.
- IC 110 drives a signal having a first voltage, V OUT1 , to the external circuit 150 .
- the first voltage is a high voltage.
- R RTERM1 152 and R RTERM2 154 form a voltage divider which, when coupled to supply voltage V DD , supplies a steady-state current from V DD to electrical ground, V GND .
- the input stage of receiver 151 of the external circuit 150 is configured with a very high input resistance so little or no current flows into it, so it may be ignored.
- Equation 1 has four unknowns (R PCB , V X1 , R RTERM1 , R RTERM2 ).
- R STERM1 is known from testing the IC, either approximately since it was tested to a certain specification with a certain tolerance and passed, or (preferably) exactly, since it was measured and stored along with the unique IC identifier (such as a fused-based identification code or a visible bar code) and can be uniquely recalled from a database.
- the latter is preferred in cases where a high degree of accuracy of the measurement is valuable, but implies the need for unique IC identification and data transfer between manufacturing steps; the former is subject to a measurement accuracy tolerance proportional to the range of specification tolerance during IC testing, but vastly simplifies data transfer requirements.
- V DD and V GND are known because their values are set by the test system, and V OUT is measured (as shown in FIGS. 5A and 5B ).
- R PCB 604 the resistance of the conductor between IC 110 and external circuit 150
- R RTERM1 152 and R RTERM2 154 are insignificant compared to the termination resistance provided by resistors R RTERM1 152 and R RTERM2 154 .
- resistance R PCB 604 goes to zero and the voltage at V X1 becomes the same as V OUT1 , the voltage at the first comparator input (see FIG. 3 ).
- FIG. 6B is a schematic diagram illustrating a circuit 600 that models a connection between IC 110 and external circuit 150 .
- the connection between IC 110 and external circuit 150 is represented by a resistive network comprising resistor R STERM2 612 (the series resistance of the driver 310 to ground), R PCB 604 (the resistance of the conductor between driver 310 and external circuit 150 ), and resistors R RTERM1 152 and R RTERM2 154 in the external circuit 150 .
- the resistive network further comprises a node between resistance R PCB 604 , resistor R RTERM1 152 , and resistor R RTERM2 154 .
- a voltage V X2 is associated with this node.
- IC 110 drives a signal having a second voltage, V OUT2 , to the external circuit 150 .
- the second voltage is a low voltage.
- R RTERM1 152 and R RTERM2 154 form a voltage divider, which when coupled to supply voltage V DD supplies a steady-state current from V DD to electrical ground, V GND .
- the receiver 151 of the external circuit 150 is configured with a very high input resistance so little or no current flows into it.
- R RTERM2 ( V OUT1 ⁇ V GND )* R STERM1 *R RTERM1 /[( V DD ⁇ V OUT1 )( R STERM1 +R RTERM1 )] EQ. 4
- R RTERM1 [R STERM1 *R STERM2 ( V DD ⁇ V GND )( V OUT1 ⁇ V OUT2 )]/[ R STERM1 ( V OUT1 ⁇ V GND )( V OUT2 ⁇ V GND )+ R STERM2 ( V DD ⁇ V OUT1 )( V OUT2 ⁇ V GND )] EQ. 5
- test circuitry 130 can be configured with registers and combinational logic to perform equations 4 and 5 to identify resistance values for the termination resistors associated with a circuit external to IC 110 .
- external agents such as a software program or a piece of test equipment, may be configured to perform equations 4 and 5.
- FIG. 6C is a schematic diagram illustrating a circuit 610 that represents a connection between IC 110 and external circuit 150 .
- the connection between IC 110 and external circuit 150 is represented by a resistive network comprising resistor R STERM1 620 (the series resistance of the driver 310 to V DD ), R STERM2 625 (the series resistance of the driver 310 to ground), resistance R PCB 604 (the resistance associated with the conductor between driver 310 and external circuit 150 ), and resistors R TERM1 152 and R TERM2 154 .
- Resistor R STERM1 620 and resistor R STERM2 625 are controllably adjustable via a plurality of digital signals to adjust the resistances as may be required to provide the specified drive current from IC 110 due to variations caused by semiconductor process, voltage, and temperature.
- the resistive network further comprises a node between R PCB 604 , R TERM1 152 , and R TERM2 154 . In the circuit model, a voltage V X2 is associated with this node.
- driver 310 ( FIG. 3 ) on integrated circuit 110 is disabled, such that paths to both V DD and ground can be activated simultaneously.
- a comparator is configured such that it has a range of operation from about 1 ⁇ 4 V DD to 3 ⁇ 4 V DD .
- the comparator is adjusted such that it is configured to trip when the voltage at node V X1 exceeds 1 ⁇ 2 V DD .
- Resistor R STERM2 625 is controllably adjusted to a fixed (and known) resistance. Thereafter, the aforementioned logic contention condition is introduced and varied between external circuit 150 and integrated circuit 110 by controllably adjusting the resistance of R STERM1 620 over time.
- Logic either internal to IC 110 or external to IC 110 is configured to receive a representation of the voltage at node V X1 that caused the comparator to change its steady-state value.
- the logic is further configured to receive digital signals that represent the commanded strengths of the resistors R STERM2 625 and R STERM1 620 .
- the logic having received the commanded strengths of the pull-down and pull-up drive elements and a representation of the V X1 voltage that tripped the comparator can be configured to identify open and short circuit conditions or failure conditions as well as nominal circuit conditions or pass conditions. Care must be taken to size the driver devices and interconnecting wires and contacts appropriately to withstand the extended logic contention conditions present during test and measurement activity.
- R RTERM2 pull-down termination resistance
- This additional test controllably removes resistor R STERM2 625 , controllably adjusts the resistance of R STERM1 620 to a relatively low or weak resistance, and reconfigures the comparator to trip at 3 ⁇ 4 VDD. If the comparator output is a logic 1 or high, the termination is too weak.
- This weak termination test can be used to identify open circuit faults in the termination network of the external circuit.
- an additional test can be performed to determine if the pull-up termination resistance (R RTERM1 ) is too weak.
- This additional test controllably removes resistor R STERM1 620 , controllably adjusts the resistance of R STERM2 625 to a relatively low or weak resistance, and reconfigures the comparator to trip at 1 ⁇ 4 VDD. If the comparator output is a logic 0 or low, the termination is too weak.
- This weak termination test can be used to identify open circuit faults in the termination network of the external circuit.
- FIGS. 7A and 7B are graphs 700 and 710 that illustrate how a voltage V OUT (i.e., V OUT from FIG. 6C ) corresponding to a voltage received by IC 110 ( FIG. 1 ) is determined.
- Graphs 700 and 710 illustrate increasing voltage from the bottom to the top of the graph with time increasing from left to right across the figures.
- V REF 702 is held constant at approximately 1 ⁇ 2 V DD .
- the pull-down driver element e.g., R STERM2 625
- the pull-up driver element e.g., R STERM1 620
- V OUT increases accordingly as indicated by trace 704 .
- V OUT 704 is substantially equal to V REF 702 .
- trace 712 representing COMPARE transitions from 0 volts to a higher voltage.
- COMPARE can be used to direct logic to determine a condition associated with the termination network associated with a circuit external to IC 110 .
- the pull-up and pull-down driver elements described above are associated with a signal driver in a bi-directional transceiver on IC 110 .
- the pull-up and pull-down elements can be associated with a receiver in a bi-directional transceiver on IC 110 .
- IC 110 can be configured with one or more additional resistive elements (e.g., test resistors and/or test transistors) in any of a number of configurations to realize desired resistances on IC 110 .
- additional resistive elements e.g., test resistors and/or test transistors
- FIG. 8A is a flow diagram illustrating an IC enabled method 800 for determining an electrical characteristic in a circuit assembly of a coupled circuit external to the IC.
- a reference voltage that varies in time is provided. As described above, the provided reference voltage can be generated on the IC itself or supplied externally.
- a first input directs the IC to transmit a first output voltage to an external circuit, as shown in block 804 .
- the first output voltage is monitored from within the IC.
- the IC generates a first signal when the first output voltage is substantially equal to the reference voltage, as shown in block 808 .
- the test system stores the magnitude of the reference voltage in response to the first signal, as shown in block 810 .
- FIG. 8B is a flow diagram illustrating a continuation of the method 800 for determining an electrical characteristic in a circuit assembly.
- method 800 continues by replacing the first input with a second input that directs the IC to transmit a second output voltage to the external circuit.
- the second output voltage is different than the first output voltage.
- the second output voltage is monitored from within the IC.
- the IC generates a second signal when the second output voltage is substantially equal to the reference voltage, as shown in block 818 .
- the test system stores the magnitude of the reference voltage in response to the second signal, as shown in block 820 .
- the values of the resistances internal to the IC are retrieved, as indicated in block 822 .
- the test system determines a target resistance using the first and second stored voltage values along with the retrieved internal resistance values by solving equations 4 and 5 presented above. A determination may then be made as to whether the target resistance meets a predetermined specification requirement. For example, the target resistance may meet a specification requirement if it falls within a range of permissible values.
- FIG. 9 is a flow diagram illustrating an alternative IC enabled method for testing an external circuit.
- Method 900 begins with block 902 where a transceiver is allowed to produce a logic contention situation in the IC. Thereafter, a first input controllably sets a reference voltage that is substantially constant in magnitude over time, as indicated in block 904 . In block 906 , a second input directs the IC to set a first resistor element on the IC to a select fixed value. In block 908 , a third input controllably directs the IC to sweep across a range of values of a second resistance element on the IC.
- the IC In block 910 , the IC generates a signal when the voltage at a node between the first and second resistance elements and coupled to the circuit external to the IC exceeds the reference voltage. Thereafter, as indicated in block 912 , a test system determines a condition associated with the external circuit responsive to the signal.
- the signal generated in block 910 can be used to determine a ratio of the actual termination voltage on the external circuit to the supply voltage.
- a ratio of the actual termination voltage on the external circuit to the supply voltage can be used to identify a pass/fail status of the resistance of the external device.
Abstract
Description
(V DD −V X1)/(R STERM1 +R PCB)+(V DD −V X1)/R RTERM1=(V X1 −V GND)/R RTERM2 EQ. 1
(V DD −V OUT)/(R STERM1)+(V DD −V OUT)/R RTERM1=(V OUT −V GND)/R RTERM2 EQ. 2
(V DD −V OUT2)/R RTERM1=(V OUT2 −V GND)/R STERM2+(V OUT2 −V GND)/R RTERM2 EQ. 3
R RTERM2=(V OUT1 −V GND)*R STERM1 *R RTERM1/[(V DD −V OUT1)(R STERM1 +R RTERM1)] EQ. 4
R RTERM1 =[R STERM1 *R STERM2(V DD −V GND)(V OUT1 −V OUT2)]/[R STERM1(V OUT1 −V GND)(V OUT2 −V GND)+R STERM2(V DD −V OUT1)(V OUT2 −V GND)] EQ. 5
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Cited By (8)
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US20100188908A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
US20100192000A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus |
US20100188917A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus |
US20100188918A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
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US20110148429A1 (en) * | 2009-12-21 | 2011-06-23 | Minemier Ronald K | DC Testing Integrated Circuits |
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Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5117129A (en) | 1990-10-16 | 1992-05-26 | International Business Machines Corporation | Cmos off chip driver for fault tolerant cold sparing |
US5361032A (en) * | 1992-01-27 | 1994-11-01 | Motorola, Inc. | Method of troubleshooting electronic circuit board assemblies using temperature isolation |
US5682392A (en) | 1994-09-28 | 1997-10-28 | Teradyne, Inc. | Method and apparatus for the automatic generation of boundary scan description language files |
US5796260A (en) | 1996-03-12 | 1998-08-18 | Honeywell Inc. | Parametric test circuit |
US5977775A (en) | 1993-08-31 | 1999-11-02 | Hewlett-Packard Company | System and method for detecting shorts, opens and connected pins on a printed circuit board using automatic equipment |
US6275962B1 (en) | 1998-10-23 | 2001-08-14 | Teradyne, Inc. | Remote test module for automatic test equipment |
US6324485B1 (en) | 1999-01-26 | 2001-11-27 | Newmillennia Solutions, Inc. | Application specific automated test equipment system for testing integrated circuit devices in a native environment |
US6365859B1 (en) | 2000-06-28 | 2002-04-02 | Advanced Micro Devices | Processor IC performance metric |
US6396279B1 (en) | 1997-04-04 | 2002-05-28 | Omicron Electronics Gmbh | Method and device for testing differential protection relays or differential protection relay systems |
US6397361B1 (en) | 1999-04-02 | 2002-05-28 | International Business Machines Corporation | Reduced-pin integrated circuit I/O test |
US6448865B1 (en) | 1999-02-25 | 2002-09-10 | Formfactor, Inc. | Integrated circuit interconnect system |
US6456124B1 (en) * | 1999-08-09 | 2002-09-24 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling impedance of an off-chip driver circuit |
US6556938B1 (en) | 2000-08-29 | 2003-04-29 | Agilent Technologies, Inc. | Systems and methods for facilitating automated test equipment functionality within integrated circuits |
US6577980B1 (en) | 2000-11-28 | 2003-06-10 | Agilent Technologies, Inc. | Systems and methods for facilitating testing of pad receivers of integrated circuits |
US6586921B1 (en) | 2000-05-12 | 2003-07-01 | Logicvision, Inc. | Method and circuit for testing DC parameters of circuit input and output nodes |
US6658613B2 (en) | 2001-03-21 | 2003-12-02 | Agilent Technologies, Inc. | Systems and methods for facilitating testing of pad receivers of integrated circuits |
US6661250B2 (en) * | 2000-11-27 | 2003-12-09 | Samsung Electronics Co., Ltd. | Programmable impedance control circuit |
US6725171B2 (en) * | 2000-11-01 | 2004-04-20 | International Business Machines Corporation | Self-test with split, asymmetric controlled driver output stage |
US6762614B2 (en) | 2002-04-18 | 2004-07-13 | Agilent Technologies, Inc. | Systems and methods for facilitating driver strength testing of integrated circuits |
US6963212B2 (en) | 2004-03-23 | 2005-11-08 | Agilent Technologies, Inc. | Self-testing input/output pad |
-
2006
- 2006-10-13 US US11/581,203 patent/US7411407B2/en active Active
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5117129A (en) | 1990-10-16 | 1992-05-26 | International Business Machines Corporation | Cmos off chip driver for fault tolerant cold sparing |
US5361032A (en) * | 1992-01-27 | 1994-11-01 | Motorola, Inc. | Method of troubleshooting electronic circuit board assemblies using temperature isolation |
US5977775A (en) | 1993-08-31 | 1999-11-02 | Hewlett-Packard Company | System and method for detecting shorts, opens and connected pins on a printed circuit board using automatic equipment |
US5682392A (en) | 1994-09-28 | 1997-10-28 | Teradyne, Inc. | Method and apparatus for the automatic generation of boundary scan description language files |
US5796260A (en) | 1996-03-12 | 1998-08-18 | Honeywell Inc. | Parametric test circuit |
US6396279B1 (en) | 1997-04-04 | 2002-05-28 | Omicron Electronics Gmbh | Method and device for testing differential protection relays or differential protection relay systems |
US6275962B1 (en) | 1998-10-23 | 2001-08-14 | Teradyne, Inc. | Remote test module for automatic test equipment |
US6324485B1 (en) | 1999-01-26 | 2001-11-27 | Newmillennia Solutions, Inc. | Application specific automated test equipment system for testing integrated circuit devices in a native environment |
US6448865B1 (en) | 1999-02-25 | 2002-09-10 | Formfactor, Inc. | Integrated circuit interconnect system |
US6397361B1 (en) | 1999-04-02 | 2002-05-28 | International Business Machines Corporation | Reduced-pin integrated circuit I/O test |
US6456124B1 (en) * | 1999-08-09 | 2002-09-24 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling impedance of an off-chip driver circuit |
US6586921B1 (en) | 2000-05-12 | 2003-07-01 | Logicvision, Inc. | Method and circuit for testing DC parameters of circuit input and output nodes |
US6365859B1 (en) | 2000-06-28 | 2002-04-02 | Advanced Micro Devices | Processor IC performance metric |
US6556938B1 (en) | 2000-08-29 | 2003-04-29 | Agilent Technologies, Inc. | Systems and methods for facilitating automated test equipment functionality within integrated circuits |
US6725171B2 (en) * | 2000-11-01 | 2004-04-20 | International Business Machines Corporation | Self-test with split, asymmetric controlled driver output stage |
US6661250B2 (en) * | 2000-11-27 | 2003-12-09 | Samsung Electronics Co., Ltd. | Programmable impedance control circuit |
US6577980B1 (en) | 2000-11-28 | 2003-06-10 | Agilent Technologies, Inc. | Systems and methods for facilitating testing of pad receivers of integrated circuits |
US6658613B2 (en) | 2001-03-21 | 2003-12-02 | Agilent Technologies, Inc. | Systems and methods for facilitating testing of pad receivers of integrated circuits |
US6762614B2 (en) | 2002-04-18 | 2004-07-13 | Agilent Technologies, Inc. | Systems and methods for facilitating driver strength testing of integrated circuits |
US6963212B2 (en) | 2004-03-23 | 2005-11-08 | Agilent Technologies, Inc. | Self-testing input/output pad |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100308850A1 (en) * | 2007-06-22 | 2010-12-09 | Continental Teves Ag & Co. Ohg | Method for testing a container warning device of a compensation container, and testing apparatus for testing a container warning device |
US9168907B2 (en) * | 2007-06-22 | 2015-10-27 | Continental Teves Ag & Co. Ohg | Method for testing a container warning device of a compensation container, and testing apparatus for testing a container warning device |
US7974141B2 (en) * | 2009-01-29 | 2011-07-05 | International Business Machines Corporation | Setting memory device VREF in a memory controller and memory device interface in a communication bus |
US20100188918A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
US20100188917A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus |
US20100188908A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
US7978538B2 (en) * | 2009-01-29 | 2011-07-12 | International Business Machines Corporation | Setting memory device termination in a memory device and memory controller interface in a communication bus |
US8102724B2 (en) | 2009-01-29 | 2012-01-24 | International Business Machines Corporation | Setting controller VREF in a memory controller and memory device interface in a communication bus |
US8111564B2 (en) | 2009-01-29 | 2012-02-07 | International Business Machines Corporation | Setting controller termination in a memory controller and memory device interface in a communication bus |
US20100192000A1 (en) * | 2009-01-29 | 2010-07-29 | International Business Machines Corporation | Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus |
US20110148429A1 (en) * | 2009-12-21 | 2011-06-23 | Minemier Ronald K | DC Testing Integrated Circuits |
US8681571B2 (en) | 2010-06-15 | 2014-03-25 | International Business Machines Corporation | Training a memory controller and a memory device using multiple read and write operations |
US8902681B2 (en) | 2010-06-15 | 2014-12-02 | International Business Machines Corporation | Setting a reference voltage in a memory controller trained to a memory device |
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