US7443041B2 - Packaging of a microchip device - Google Patents
Packaging of a microchip device Download PDFInfo
- Publication number
- US7443041B2 US7443041B2 US10/312,589 US31258904A US7443041B2 US 7443041 B2 US7443041 B2 US 7443041B2 US 31258904 A US31258904 A US 31258904A US 7443041 B2 US7443041 B2 US 7443041B2
- Authority
- US
- United States
- Prior art keywords
- interposer
- aperture
- microchip
- microchip device
- electrical contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 238000004806 packaging method and process Methods 0.000 title abstract description 21
- 239000000463 material Substances 0.000 claims description 39
- 239000004020 conductor Substances 0.000 claims description 23
- 239000012777 electrically insulating material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 16
- 238000001721 transfer moulding Methods 0.000 description 17
- 239000011810 insulating material Substances 0.000 description 15
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003019 stabilising effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
-
- The conductor length for connecting the electrical contacts on the microchip surface with the external contacts can be kept very short, especially if the edge of the aperture is located close to the contacts on the microchip device surface.
- The external contacts on the outside of the interposer will be connected from the same side as the contacts on the microchip surface during the connecting process. Therefore, the arrangement can be very compact.
- The conductors are protected by the encapsulating material.
- The external contacts of the package can directly be connected to contacts of a board. Further, the microchip device is located on or near the opposite surface of the package so as to allow the maximum possible heat dissipation to the ambient.
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG200100220A SG94734A1 (en) | 2001-01-15 | 2001-01-15 | Packaging of a microchip device |
PCT/SG2002/000125 WO2004002003A1 (en) | 2001-01-15 | 2002-06-19 | Packaging of a microchip device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050257955A1 US20050257955A1 (en) | 2005-11-24 |
US7443041B2 true US7443041B2 (en) | 2008-10-28 |
Family
ID=32502020
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/312,589 Expired - Lifetime US7443041B2 (en) | 2001-01-15 | 2002-06-19 | Packaging of a microchip device |
Country Status (2)
Country | Link |
---|---|
US (1) | US7443041B2 (en) |
TW (2) | TW567562B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110084410A1 (en) * | 2009-10-12 | 2011-04-14 | Tae-Sung Yoon | Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate |
US20210398907A1 (en) * | 2020-06-18 | 2021-12-23 | Advanced Semiconductor Engineering, Inc. | Substrate, semiconductor package, and method of manufacturing the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013010178A1 (en) * | 2011-07-14 | 2013-01-17 | Brigham And Women's Hospital, Inc. | System and method for integration of mobile device imaging with microchip elisa |
CN111432555A (en) * | 2020-03-24 | 2020-07-17 | 环维电子(上海)有限公司 | Double-sided PCB and one-time double-sided plastic packaging method thereof |
Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4868349A (en) | 1988-05-09 | 1989-09-19 | National Semiconductor Corporation | Plastic molded pin-grid-array power package |
US5126824A (en) | 1989-08-09 | 1992-06-30 | Mitsubishi Denki Kabushiki Kaisha | Carrier tape and method of manufacturing semiconductor device employing the same |
US5554885A (en) | 1993-06-04 | 1996-09-10 | Seiko Epson Corporation | Semiconductor device including means for dispersing and absorbing tensile forces acting on film tape |
JPH08306817A (en) | 1995-04-28 | 1996-11-22 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacture |
US5777391A (en) * | 1994-12-20 | 1998-07-07 | Hitachi, Ltd. | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
US5818698A (en) * | 1995-10-12 | 1998-10-06 | Micron Technology, Inc. | Method and apparatus for a chip-on-board semiconductor module |
US6091140A (en) * | 1998-10-23 | 2000-07-18 | Texas Instruments Incorporated | Thin chip-size integrated circuit package |
JP2000208540A (en) | 1998-08-25 | 2000-07-28 | Texas Instr Inc <Ti> | Method for airtightly sealing thin semiconductor chip scale package |
JP2000260791A (en) | 1999-03-08 | 2000-09-22 | Fuji Xerox Co Ltd | Semiconductor device and its manufacture |
US6133627A (en) | 1990-09-24 | 2000-10-17 | Tessera, Inc. | Semiconductor chip package with center contacts |
US6144102A (en) * | 1997-05-16 | 2000-11-07 | Texas Instruments Incorporated | Semiconductor device package |
US6177723B1 (en) * | 1997-04-10 | 2001-01-23 | Texas Instruments Incorporated | Integrated circuit package and flat plate molding process for integrated circuit package |
US6242283B1 (en) * | 1999-12-30 | 2001-06-05 | Siliconware Precision Industries Co., Ltd. | Wafer level packaging process of semiconductor |
US6268650B1 (en) * | 1999-05-25 | 2001-07-31 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6300165B2 (en) * | 1999-11-15 | 2001-10-09 | Substrate Technologies Incorporated | Ball grid substrate for lead-on-chip semiconductor package |
US6376916B1 (en) | 1999-01-21 | 2002-04-23 | Hitachi Cable, Ltd. | Tape carrier for BGA and semiconductor device using the same |
US20020050654A1 (en) | 2000-06-16 | 2002-05-02 | Bolken Todd O. | Method and apparatus for packaging a microelectronic die |
US6385049B1 (en) * | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
US20020149917A1 (en) | 2001-04-02 | 2002-10-17 | Christian Hauser | Electronic component with a semiconductor chip, and method of producing the electronic component |
US6476507B1 (en) * | 1999-08-10 | 2002-11-05 | Towa Corporation | Resin sealing method and resin sealing apparatus |
DE10127009A1 (en) | 2001-06-05 | 2002-12-12 | Infineon Technologies Ag | Plastic housing used for packing semiconductor chips comprises semiconductor chips arranged in lines and gaps |
US6522018B1 (en) * | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US6531335B1 (en) * | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
US6548764B1 (en) * | 2000-06-07 | 2003-04-15 | Micron Technology, Inc. | Semiconductor packages and methods for making the same |
JP2003234436A (en) | 2002-02-12 | 2003-08-22 | Apic Yamada Corp | Matrix board and resin molding method |
US6781248B2 (en) * | 2001-05-21 | 2004-08-24 | Micron Technology, Inc. | Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged |
-
2002
- 2002-04-09 TW TW091107070A patent/TW567562B/en not_active IP Right Cessation
- 2002-04-09 TW TW091107069A patent/TW567594B/en not_active IP Right Cessation
- 2002-06-19 US US10/312,589 patent/US7443041B2/en not_active Expired - Lifetime
Patent Citations (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0217665A (en) | 1988-05-09 | 1990-01-22 | Natl Semiconductor Corp <Ns> | Synthetic resin covered pin-grid-array power package |
US4868349A (en) | 1988-05-09 | 1989-09-19 | National Semiconductor Corporation | Plastic molded pin-grid-array power package |
US5126824A (en) | 1989-08-09 | 1992-06-30 | Mitsubishi Denki Kabushiki Kaisha | Carrier tape and method of manufacturing semiconductor device employing the same |
US6133627A (en) | 1990-09-24 | 2000-10-17 | Tessera, Inc. | Semiconductor chip package with center contacts |
US5554885A (en) | 1993-06-04 | 1996-09-10 | Seiko Epson Corporation | Semiconductor device including means for dispersing and absorbing tensile forces acting on film tape |
US5777391A (en) * | 1994-12-20 | 1998-07-07 | Hitachi, Ltd. | Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof |
JPH08306817A (en) | 1995-04-28 | 1996-11-22 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacture |
US5818698A (en) * | 1995-10-12 | 1998-10-06 | Micron Technology, Inc. | Method and apparatus for a chip-on-board semiconductor module |
US6177723B1 (en) * | 1997-04-10 | 2001-01-23 | Texas Instruments Incorporated | Integrated circuit package and flat plate molding process for integrated circuit package |
US6144102A (en) * | 1997-05-16 | 2000-11-07 | Texas Instruments Incorporated | Semiconductor device package |
US6331737B1 (en) | 1998-08-25 | 2001-12-18 | Texas Instruments Incorporated | Method of encapsulating thin semiconductor chip-scale packages |
JP2000208540A (en) | 1998-08-25 | 2000-07-28 | Texas Instr Inc <Ti> | Method for airtightly sealing thin semiconductor chip scale package |
US6091140A (en) * | 1998-10-23 | 2000-07-18 | Texas Instruments Incorporated | Thin chip-size integrated circuit package |
US6376916B1 (en) | 1999-01-21 | 2002-04-23 | Hitachi Cable, Ltd. | Tape carrier for BGA and semiconductor device using the same |
JP2000260791A (en) | 1999-03-08 | 2000-09-22 | Fuji Xerox Co Ltd | Semiconductor device and its manufacture |
US6268650B1 (en) * | 1999-05-25 | 2001-07-31 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6372552B1 (en) | 1999-05-25 | 2002-04-16 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6476507B1 (en) * | 1999-08-10 | 2002-11-05 | Towa Corporation | Resin sealing method and resin sealing apparatus |
US6300165B2 (en) * | 1999-11-15 | 2001-10-09 | Substrate Technologies Incorporated | Ball grid substrate for lead-on-chip semiconductor package |
US6242283B1 (en) * | 1999-12-30 | 2001-06-05 | Siliconware Precision Industries Co., Ltd. | Wafer level packaging process of semiconductor |
US6531335B1 (en) * | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
US6522018B1 (en) * | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
US6548764B1 (en) * | 2000-06-07 | 2003-04-15 | Micron Technology, Inc. | Semiconductor packages and methods for making the same |
US20020050654A1 (en) | 2000-06-16 | 2002-05-02 | Bolken Todd O. | Method and apparatus for packaging a microelectronic die |
US6589820B1 (en) * | 2000-06-16 | 2003-07-08 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US20020149917A1 (en) | 2001-04-02 | 2002-10-17 | Christian Hauser | Electronic component with a semiconductor chip, and method of producing the electronic component |
DE10116069A1 (en) | 2001-04-02 | 2002-10-17 | Infineon Technologies Ag | Electronic component with a semiconductor chip and method for its production |
US6906928B2 (en) * | 2001-04-02 | 2005-06-14 | Infineon Technologies Ag | Electronic component with a semiconductor chip, and method of producing the electronic component |
US6781248B2 (en) * | 2001-05-21 | 2004-08-24 | Micron Technology, Inc. | Method for encapsulating intermediate conductive elements connecting a semiconductor die to a substrate and semiconductor devices so packaged |
DE10127009A1 (en) | 2001-06-05 | 2002-12-12 | Infineon Technologies Ag | Plastic housing used for packing semiconductor chips comprises semiconductor chips arranged in lines and gaps |
US20040175866A1 (en) | 2001-06-05 | 2004-09-09 | Andreas Woerz | Plastic housing comprising several semiconductor chips and a wiring modification plate, and method for producing the plastic housing in an injection-molding mold |
US6385049B1 (en) * | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
JP2003234436A (en) | 2002-02-12 | 2003-08-22 | Apic Yamada Corp | Matrix board and resin molding method |
Non-Patent Citations (6)
Title |
---|
English language Abstract of DE 10127009. |
English language Abstract of JP 2000-208540. |
English language Abstract of JP 2000-260791. |
English language Abstract of JP 2003-234436. |
English language Abstract of JP 2-017665. |
English language Abstract of JP 8-306817. |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110084410A1 (en) * | 2009-10-12 | 2011-04-14 | Tae-Sung Yoon | Wiring Substrate for a Semiconductor Chip, and Semiconducotor Package Having the Wiring Substrate |
US8294250B2 (en) * | 2009-10-12 | 2012-10-23 | Samsung Electronics Co., Ltd. | Wiring substrate for a semiconductor chip, and semiconducotor package having the wiring substrate |
US20210398907A1 (en) * | 2020-06-18 | 2021-12-23 | Advanced Semiconductor Engineering, Inc. | Substrate, semiconductor package, and method of manufacturing the same |
US11296034B2 (en) * | 2020-06-18 | 2022-04-05 | Advanced Semiconductor Engineering, Inc. | Substrate and semiconductor package comprising an interposer element with a slot and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20050257955A1 (en) | 2005-11-24 |
TW567562B (en) | 2003-12-21 |
TW567594B (en) | 2003-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5665651A (en) | Process for encapsulating a semiconductor device and lead frame | |
US7220615B2 (en) | Alternative method used to package multimedia card by transfer molding | |
US6395579B2 (en) | Controlling packaging encapsulant leakage | |
US6432742B1 (en) | Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages | |
US7141886B2 (en) | Air pocket resistant semiconductor package | |
US5475259A (en) | Semiconductor device and carrier for carrying semiconductor device | |
US8232658B2 (en) | Stackable integrated circuit package system with multiple interconnect interface | |
US7723157B2 (en) | Method for cutting and molding in small windows to fabricate semiconductor packages | |
US6476507B1 (en) | Resin sealing method and resin sealing apparatus | |
JPH11176865A (en) | Semiconductor integrated circuit element | |
EP0923120A1 (en) | Method for manufacturing semiconductor device | |
KR19990023662A (en) | Method and apparatus for forming panel of packaged integrated circuit | |
US7504715B2 (en) | Packaging of a microchip device | |
US7443041B2 (en) | Packaging of a microchip device | |
US7265453B2 (en) | Semiconductor component having dummy segments with trapped corner air | |
US9362194B2 (en) | Semiconductor chip covered with sealing resin having a filler material | |
US20090134504A1 (en) | Semiconductor package and packaging method for balancing top and bottom mold flows from window | |
US7763983B2 (en) | Stackable microelectronic device carriers, stacked device carriers and methods of making the same | |
WO2004002003A1 (en) | Packaging of a microchip device | |
US9034697B2 (en) | Apparatus and methods for quad flat no lead packaging | |
JP4376781B2 (en) | Microchip package | |
CN113394118B (en) | Package structure and method for forming the same | |
US20090096070A1 (en) | Semiconductor package and substrate for the same | |
JP2012084908A (en) | Packaging method for microchip device | |
US11309236B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED TEST & ASSEMBLY CENTER LIMITED, SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KHIANG, WANG CHUEN;REEL/FRAME:013853/0455 Effective date: 20030121 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: UTAC HEADQUARTERS PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNITED TEST AND ASSEMBLY CENTER LIMITED;REEL/FRAME:037959/0822 Effective date: 20150508 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
AS | Assignment |
Owner name: UTAC HEADQUARTERS PTE. LTD., SINGAPORE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO ADD THE ANNEX A AND THE ANNEX B WHICH WAS INADVERTENTLY LEFTOUT IN THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037959 FRAME 0822. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:UNITED TEST AND ASSEMBLY CENTER LIMITED;REEL/FRAME:039885/0541 Effective date: 20150508 |
|
AS | Assignment |
Owner name: UTAC HEADQUARTERS PTE. LTD., SINGAPORE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCLUDE PATENT NUMBER 8816482 PREVIOUSLY RECORDED AT REEL: 039885 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:UNITED TEST AND ASSEMBLY CENTER LIMITED;REEL/FRAME:043979/0820 Effective date: 20150508 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |