US7536528B2 - Memory arrangement - Google Patents

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US7536528B2
US7536528B2 US11/679,609 US67960907A US7536528B2 US 7536528 B2 US7536528 B2 US 7536528B2 US 67960907 A US67960907 A US 67960907A US 7536528 B2 US7536528 B2 US 7536528B2
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memory
data
bank access
bank
interface
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US20070204116A1 (en
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Paul Wallner
Chaitanya Dudha
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Polaris Innovations Ltd
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Qimonda AG
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • the memory arrangement is not driven via parallel application of data signals, address signals and control signals, as in typical conventional memory arrangements, but rather via data packets that are transmitted at high speed and at high frequency, in accordance with a predefined protocol, between, for example, a computer system and an interface of the memory arrangement.
  • These data packets may contain write data, read data, addressing data, and command data.
  • the received data are interpreted and processed as commands, address data, or write data.
  • read data can also be coded into data packets by the interface and transmitted to, for example, a computer system.
  • the memory arrangement of such a type comprises several memory banks that can be accessed via several memory-bank access devices and that each include a plurality of memory cells.
  • One embodiment provides a memory arrangement including an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol.
  • the memory arrangement includes at least two memory banks, each memory bank including at least one memory cell.
  • the memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks.
  • the memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
  • FIG. 1 is a schematic top view of a memory arrangement according to one embodiment with two temporary storage devices.
  • FIG. 2 illustrates a schematic top view of one embodiment of the memory arrangement with four temporary storage devices.
  • FIG. 3 is a schematic top view of a memory arrangement in which a data flow is represented
  • FIG. 4 is a schematic top view of a memory arrangement with only one temporary storage device.
  • FIG. 3 illustrates an example memory arrangement 10 with sixteen memory banks 6 which are arranged in a four-by-four matrix.
  • the upper eight memory banks 6 are spaced from the lower eight memory banks 6 , so that a strip-shaped area 7 , which is also referred to as spine, is formed between the upper eight memory banks 6 and the lower eight memory banks 6 .
  • the sixteen memory banks 6 are further partitioned into two groups, each of eight memory banks 6 , in which, referring to FIG.
  • a left group defines the eight memory banks 6 located on the left in a top view
  • a right group defines the eight memory banks 6 located on the right in the top view.
  • a memory bank 6 pertaining to the left group is accessed via the first memory-bank access device 1
  • a memory bank 6 pertaining to the right group is accessed via the second memory-bank access device 2 .
  • the interface 4 , the memory-bank access devices 1 and 2 , and further devices of the memory arrangement, such as, for example, a clock-pulse supply, are arranged in the spine 7 .
  • the interface 4 is arranged substantially at a center in the longitudinal direction of the spine 7 , the first memory-bank access device 1 , which is assigned to the left group of memory banks, is substantially arranged at a center in a left half of the spine 7 , and the second memory-bank access device 2 , which is assigned to the right group of memory banks, is substantially arranged at a center in a right half of the spine 7 .
  • Write data received by the interface 4 are transmitted in the direction of arrows 8 and 9 to the corresponding memory-bank access devices 1 and 2 , respectively.
  • read data are transmitted contrary to the arrow directions of the arrows 8 and 9 from the memory-bank access devices 1 and 2 , respectively, to the interface 4 .
  • An arrangement of such a type enables a uniform timing response of the individual memory banks to be obtained.
  • temporary storage devices are inserted between the interface and the memory-bank access devices.
  • these temporary storage devices cause the write data that are decoded from a data packet to be firstly stored by the interface in the temporary storage device, in order then to be stored in the memory banks in temporally independent manner via the memory-bank access devices.
  • write data can be transmitted to the memory arrangement at a speed that is far higher than the maximum possible speed of storage of these write data in the memory banks.
  • a command for making read data available can be received by the interface, and the read operation can be triggered, so that the interface is then ready for receiving further write data, read data, addressing data, or command data, while the read data from the memory banks are sent to the temporary storage devices via the memory-bank access devices, in order to be read out from there at a later time via the interface.
  • a further advantage of the temporary storage is the on-chip timing response can be decoupled from the off-chip timing response.
  • FIG. 4 illustrates an example memory arrangement 10 with a temporary storage device 3 which is suitable to temporarily store data from data packets that are received by the interface 4 .
  • the interface 4 is connected to the temporary storage device 3 via connecting lines in an area 11
  • the temporary storage device 3 is in turn connected to the memory-bank access devices 1 and 2 via connecting lines in areas 12 .
  • a symmetrical arrangement of both the temporary storage device 3 and the interface 4 is employed for reasons concerning the timing.
  • FIG. 4 illustrates that a central arrangement of the temporary storage device 3 in the center of the spine 7 has the consequence that, on the one hand, a large chip area is employed in the center of the spine 7 , which as a result is no longer available to other central functions of the memory arrangement, and that, on the other hand, relatively large areas 12 employed within the spine 7 for the connecting lines from the temporary storage device 3 to the memory-bank access devices 1 and 2 .
  • Located in the areas 12 are, for example, 72 lines in each instance, which correspond to 64 lines for 64 data bits of the data-bank memory width plus eight lines for eight masking bits.
  • a further advantage of the use of the temporary storage device is that, for example, the temporary storage device temporarily stores the contents of several related packets of write data, and these contents are then stored in the memory banks in one write access via the memory-bank access devices. If, for example, 64 bits can be written simultaneously via a memory-bank access device, and two memory-bank access devices are present, it is possible to transmit, firstly, 128 data bits and additional 16 masking bits which can each be used for the purpose of masking eight of the 128 data bits in each instance in, for example, four data packets, and then to transmit these 128 data bits and 16 masking bits in one write operation to the memory-bank access devices which then store the unmasked bits of the 128 data bits in the memory banks. As a result, the system performance is further enhanced.
  • One embodiment of a memory arrangement comprises an interface, which is suitable for transmitting, coding and/or decoding data in the form of data packets in accordance with a predefined protocol, at least two memory banks, which each include at least one memory cell, at least two memory-bank access devices, via which the data of the memory cells of the at least two memory banks are accessed, and at least two temporary storage devices, the temporary storage devices being suitable for temporarily storing data that are being transmitted between the interface and the at least two memory-bank access devices, and each of the at least two temporary storage devices being connected both to the interface and to one of the at least two memory-bank access devices.
  • the memory arrangement includes an even number of memory banks, a first memory-bank access device and a second memory-bank access device.
  • the memory cells pertaining to a first half of the memory banks are accessed via the first memory-bank access device, and the memory cells pertaining to a second half of the memory banks are accessed via the second memory-bank access device.
  • two temporary storage devices and two memory-bank access devices can be arranged on the memory arrangement, one of the two temporary storage devices being arranged in each instance adjacent to one of the two memory-bank access devices.
  • each of the two temporary storage devices only that portion of the data is temporarily stored which is being transmitted via the adjacently arranged memory-bank access device.
  • the chip area of each individual temporary storage device that is employed amounts approximately to one half of the chip area of a comparable unpartitioned temporary storage device.
  • two memory-bank access devices and four temporary storage devices are provided on the memory arrangement, two of the four temporary storage devices being arranged in each instance adjacent to each of the two memory-bank access devices.
  • each of the four temporary storage devices only that portion of the data is temporarily stored in each instance which is being transmitted via the adjacently arranged memory-bank access devices, so that the chip area of each of the four temporary storage devices corresponds approximately to one quarter of a comparable unpartitioned temporary storage device.
  • the interface of the memory arrangement is configured in such a manner that the interface is able to transmit code and/or decode write data, read data, addressing data, and command data in the form of data packets.
  • the data packets may be structured in such a manner that a data packet includes a defined number of bits which are transmitted via several parallel lines.
  • the number of parallel lines may be distinctly less than the number of bits of a data packet, by several consecutive bit groups being transmitted via the parallel lines and then being assembled into a data packet.
  • Data packets with a length of, for example, 54 bits can consequently, for example, be transmitted via six lines in nine consecutive 6 bit groups.
  • the interface synchronizes to the serial data stream and parallelizes the serially received data.
  • Data that are being transmitted from the memory arrangement to, for example, a computer system are serialized by the interface.
  • the memory arrangement includes several memory banks that can be accessed via several memory-bank access devices.
  • memory-bank access devices it holds that memory cells of one or more memory banks can be accessed via a memory-bank access device.
  • Access to memory cells of a defined memory bank is possible only from exactly one memory-bank access device. Consequently several memory banks can be assigned to one memory-bank access device, but one memory bank cannot be assigned to various memory-bank access devices.
  • the memory arrangement is employed in dynamic random access memory (DRAM) memory modules on a common chip.
  • DRAM dynamic random access memory
  • ROM read only memory
  • the memory arrangement is employed in a computer system as read/write memory or DRAM memory.
  • FIG. 1 illustrates schematically an embodiment of a memory arrangement 10 with an even number of memory banks 6 , a first memory-bank access device 1 , and a second memory-bank access device 2 .
  • the sixteen memory banks 6 are partitioned into two areas. Like in FIG. 3 , eight memory banks 6 are located in an upper area, and eight memory banks 6 are located in a lower area. Located between the upper area and the lower area is a narrow, strip-shaped area 7 in which the memory-bank access devices 1 and 2 and an interface 4 are located. This narrow area 7 between each of the eight memory banks is designated as the spine 7 .
  • the sixteen memory banks 6 are further partitioned into two groups of, in each instance, eight memory banks 6 , in which, referring to FIG.
  • a left group defines the eight memory banks located on the left in a top view
  • a right group defines the eight memory banks located on the right in the top view.
  • One of the memory banks 6 pertaining to the left group is accessed via the first memory-bank access device 1
  • one of the memory banks 6 pertaining to the right group is accessed via the second memory-bank access device 2 .
  • the interface 4 is arranged substantially at a center in a longitudinal direction of the spine 7 ; the first memory-bank access device 1 , which is assigned to the left group of memory banks, is arranged substantially at a center of a left half of the spine 7 ; and the second memory-bank access device 2 , which is assigned to the right group of memory banks, is arranged substantially at a center of a right half of the spine 7 .
  • a first temporary storage device 5 and a second temporary storage device 5 are arranged respectively adjacent to one of the memory-bank access devices 1 and 2 , respectively, the first temporary storage device 5 being arranged in an area that extends from the center of the spine in the direction of the first memory-bank access device 1 , and the second temporary storage device 5 being arranged in an area that extends from the center of the spine in the direction of the second memory-bank access device 2 .
  • the temporary storage devices 5 are arranged in the aforementioned areas in such a manner that they each have a spacing from the respectively adjacently arranged memory-bank access devices 1 and 2 that is as small as possible.
  • the two temporary storage devices 5 are connected to the interface 4 via connecting lines that are arranged in an area 11 .
  • the two memory-bank access devices 1 and 2 are each connected to one of the two temporary storage devices 5 via connecting lines that are arranged in areas 12 .
  • each temporary storage device 5 corresponds substantially to one half of the area requirement of the unpartitioned temporary storage device 3 of FIG. 4 , since in each temporary storage device 5 only those data are stored which are to be stored in the memory banks 6 via the memory-bank access device 1 or 2 to which the respective temporary storage device 5 is connected. Since the write data are received by the interface 4 in several data packets, after they have been decoded by the interface 4 the write data are transmitted packet-by-packet from the interface 4 to the temporary storage devices 5 . As a result of this partly serialized transmission between the interface 4 and the temporary storage device 5 , the number of necessary connecting lines in the area 11 between the interface 4 and the temporary storage devices 5 is reduced.
  • each portion of the area 11 approximately 30 connecting lines are arranged, wherein the portions of area 11 extend from the center of the spine in the direction of the memory-bank access devices 1 and 2 , respectively.
  • 72 lines are arranged, wherein the areas 12 likewise extend from the center of the spine in the direction of the memory-bank access devices 1 and 2 , respectively.
  • FIG. 2 illustrates a schematic top view of an embodiment of a memory arrangement 10 .
  • the interface 4 , the memory banks 6 , the spine 7 and the memory-bank access devices 1 , 2 are arranged similar to as described above in the description of FIG. 1 .
  • four temporary storage devices 5 are arranged at four places in the memory arrangement 10 , specifically in such a manner that two temporary storage devices 5 are arranged adjacent to each memory-bank access device 1 and 2 , as illustrated in FIG.
  • a first of the temporary storage devices 5 being arranged to the left of the first memory-bank access device 1
  • a second of the temporary storage devices 5 being arranged between the center of the spine 7 and the first memory-bank access device 1
  • a third of the temporary storage devices 5 being arranged between the center of the spine 7 and the second memory-bank access device 2
  • a fourth of the temporary storage devices 5 being arranged to the right of the second memory-bank access device 2 .
  • the chip area employed for each of the four temporary storage devices 5 corresponds, in each instance, to approximately one quarter of the surface area of the unpartitioned temporary storage device 3 illustrated in FIG. 4 , because in each of the four temporary storage devices 5 only that portion of the data is stored which is to be stored in the memory banks 6 via the memory-bank access device 1 or 2 to which the respective temporary storage devices 5 are connected. In turn, approximately 30 connecting lines are located in the area 11 between the interface 4 and the temporary storage devices 5 . In the areas 12 , on the other hand, only 36 connecting lines are now arranged between, in each instance, a temporary storage device and a memory-bank access device.
  • temporary storage devices embodiments described above may be employed advantageously in conjunction with the partitioning, according embodiments, of the temporary storage devices also in the case of the readout of data from the memory banks 6 .
  • temporary storage devices 5 that are arranged between memory-bank access devices 1 and 2 and an interface 4 , which is configured for transmitting, coding and decoding read data, addressing data and command data, have read data written to them from the memory banks 6 via the memory-bank access devices 1 and 2 by reason of a read request.
  • a readout of the temporary storage devices 5 is possible in temporally independent manner via data packets that are coded and transmitted by the interface 4 .
  • temporary storage devices temporarily store commands and command sequences that are executed in a manner temporally independent of the receiving of the commands or command sequences, in order, for example, to refresh memory banks or to provide read data.

Abstract

A memory arrangement includes an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This Utility Patent Application claims priority to German Patent Application No. DE 10 2006 009 027.6, filed on Feb. 27, 2006, which is incorporated herein by reference.
BACKGROUND
In many modem memory arrangements for computer systems and other electronic data processing systems, the memory arrangement is not driven via parallel application of data signals, address signals and control signals, as in typical conventional memory arrangements, but rather via data packets that are transmitted at high speed and at high frequency, in accordance with a predefined protocol, between, for example, a computer system and an interface of the memory arrangement. These data packets may contain write data, read data, addressing data, and command data.
Data packets that, for example, are sent from a computer system to the memory arrangement, are received and decoded by the interface of the memory arrangement. In accordance with the predefined protocol, the received data are interpreted and processed as commands, address data, or write data. In comparable manner, read data can also be coded into data packets by the interface and transmitted to, for example, a computer system.
The memory arrangement of such a type comprises several memory banks that can be accessed via several memory-bank access devices and that each include a plurality of memory cells.
SUMMARY
One embodiment provides a memory arrangement including an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol. The memory arrangement includes at least two memory banks, each memory bank including at least one memory cell. The memory arrangement includes at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks. The memory arrangement includes at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices. Each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 is a schematic top view of a memory arrangement according to one embodiment with two temporary storage devices.
FIG. 2 illustrates a schematic top view of one embodiment of the memory arrangement with four temporary storage devices.
FIG. 3 is a schematic top view of a memory arrangement in which a data flow is represented,
FIG. 4 is a schematic top view of a memory arrangement with only one temporary storage device.
 DETAILED DESCRIPTION
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
FIG. 3 illustrates an example memory arrangement 10 with sixteen memory banks 6 which are arranged in a four-by-four matrix. In the top view of the memory arrangement 10 illustrated in FIG. 3, the upper eight memory banks 6 are spaced from the lower eight memory banks 6, so that a strip-shaped area 7, which is also referred to as spine, is formed between the upper eight memory banks 6 and the lower eight memory banks 6. For example, in the case of an arrangement with a first memory-bank access device 1 and a second memory-bank access device 2, the sixteen memory banks 6 are further partitioned into two groups, each of eight memory banks 6, in which, referring to FIG. 3, a left group defines the eight memory banks 6 located on the left in a top view, and a right group defines the eight memory banks 6 located on the right in the top view. A memory bank 6 pertaining to the left group is accessed via the first memory-bank access device 1, and a memory bank 6 pertaining to the right group is accessed via the second memory-bank access device 2. The interface 4, the memory- bank access devices 1 and 2, and further devices of the memory arrangement, such as, for example, a clock-pulse supply, are arranged in the spine 7. The interface 4 is arranged substantially at a center in the longitudinal direction of the spine 7, the first memory-bank access device 1, which is assigned to the left group of memory banks, is substantially arranged at a center in a left half of the spine 7, and the second memory-bank access device 2, which is assigned to the right group of memory banks, is substantially arranged at a center in a right half of the spine 7. Write data received by the interface 4 are transmitted in the direction of arrows 8 and 9 to the corresponding memory- bank access devices 1 and 2, respectively. Analogously, read data are transmitted contrary to the arrow directions of the arrows 8 and 9 from the memory- bank access devices 1 and 2, respectively, to the interface 4. An arrangement of such a type enables a uniform timing response of the individual memory banks to be obtained.
With a different number of memory banks and/or memory-bank access devices, appropriately optimised arrangements can be chosen.
In order to keep the costs of the memory arrangement as low as possible, it is desirable to keep the chip area as small as possible. For the spine, this means that its width, (i.e., the spacing between the upper memory banks and the lower memory banks) should be as small as possible.
In order to achieve a high system performance of the memory arrangement, temporary storage devices are inserted between the interface and the memory-bank access devices. In the course of writing, these temporary storage devices cause the write data that are decoded from a data packet to be firstly stored by the interface in the temporary storage device, in order then to be stored in the memory banks in temporally independent manner via the memory-bank access devices. Thus, for example, write data can be transmitted to the memory arrangement at a speed that is far higher than the maximum possible speed of storage of these write data in the memory banks. After the write data have been stored by the interface in the temporary storage device, the interface is ready for receiving new write data, read data, addressing data, or command data. Similarly, a command for making read data available can be received by the interface, and the read operation can be triggered, so that the interface is then ready for receiving further write data, read data, addressing data, or command data, while the read data from the memory banks are sent to the temporary storage devices via the memory-bank access devices, in order to be read out from there at a later time via the interface. A further advantage of the temporary storage is the on-chip timing response can be decoupled from the off-chip timing response.
FIG. 4 illustrates an example memory arrangement 10 with a temporary storage device 3 which is suitable to temporarily store data from data packets that are received by the interface 4. To this end, the interface 4 is connected to the temporary storage device 3 via connecting lines in an area 11, and the temporary storage device 3 is in turn connected to the memory- bank access devices 1 and 2 via connecting lines in areas 12. A symmetrical arrangement of both the temporary storage device 3 and the interface 4 is employed for reasons concerning the timing. FIG. 4 illustrates that a central arrangement of the temporary storage device 3 in the center of the spine 7 has the consequence that, on the one hand, a large chip area is employed in the center of the spine 7, which as a result is no longer available to other central functions of the memory arrangement, and that, on the other hand, relatively large areas 12 employed within the spine 7 for the connecting lines from the temporary storage device 3 to the memory- bank access devices 1 and 2. Located in the areas 12 are, for example, 72 lines in each instance, which correspond to 64 lines for 64 data bits of the data-bank memory width plus eight lines for eight masking bits.
A further advantage of the use of the temporary storage device is that, for example, the temporary storage device temporarily stores the contents of several related packets of write data, and these contents are then stored in the memory banks in one write access via the memory-bank access devices. If, for example, 64 bits can be written simultaneously via a memory-bank access device, and two memory-bank access devices are present, it is possible to transmit, firstly, 128 data bits and additional 16 masking bits which can each be used for the purpose of masking eight of the 128 data bits in each instance in, for example, four data packets, and then to transmit these 128 data bits and 16 masking bits in one write operation to the memory-bank access devices which then store the unmasked bits of the 128 data bits in the memory banks. As a result, the system performance is further enhanced.
On the other hand, it is therefore necessary to have many parallel lines between the temporary storage device and the memory-bank access devices in the above example, 72 lines to each memory-bank access device. Since these lines are also located in the spine, this employs a large surface area within the spine, and consequently a large width of the spine.
One embodiment of a memory arrangement comprises an interface, which is suitable for transmitting, coding and/or decoding data in the form of data packets in accordance with a predefined protocol, at least two memory banks, which each include at least one memory cell, at least two memory-bank access devices, via which the data of the memory cells of the at least two memory banks are accessed, and at least two temporary storage devices, the temporary storage devices being suitable for temporarily storing data that are being transmitted between the interface and the at least two memory-bank access devices, and each of the at least two temporary storage devices being connected both to the interface and to one of the at least two memory-bank access devices.
According to one embodiment, the memory arrangement includes an even number of memory banks, a first memory-bank access device and a second memory-bank access device. The memory cells pertaining to a first half of the memory banks are accessed via the first memory-bank access device, and the memory cells pertaining to a second half of the memory banks are accessed via the second memory-bank access device.
According to one embodiment, two temporary storage devices and two memory-bank access devices can be arranged on the memory arrangement, one of the two temporary storage devices being arranged in each instance adjacent to one of the two memory-bank access devices. In each of the two temporary storage devices only that portion of the data is temporarily stored which is being transmitted via the adjacently arranged memory-bank access device. Hence the chip area of each individual temporary storage device that is employed amounts approximately to one half of the chip area of a comparable unpartitioned temporary storage device.
According to one embodiment, two memory-bank access devices and four temporary storage devices are provided on the memory arrangement, two of the four temporary storage devices being arranged in each instance adjacent to each of the two memory-bank access devices. In each of the four temporary storage devices only that portion of the data is temporarily stored in each instance which is being transmitted via the adjacently arranged memory-bank access devices, so that the chip area of each of the four temporary storage devices corresponds approximately to one quarter of a comparable unpartitioned temporary storage device.
According to one embodiment, the interface of the memory arrangement is configured in such a manner that the interface is able to transmit code and/or decode write data, read data, addressing data, and command data in the form of data packets. The data packets may be structured in such a manner that a data packet includes a defined number of bits which are transmitted via several parallel lines. The number of parallel lines may be distinctly less than the number of bits of a data packet, by several consecutive bit groups being transmitted via the parallel lines and then being assembled into a data packet. Data packets with a length of, for example, 54 bits can consequently, for example, be transmitted via six lines in nine consecutive 6 bit groups. If data are being transmitted, for example, from a computer system to the memory arrangement, the interface synchronizes to the serial data stream and parallelizes the serially received data. Data that are being transmitted from the memory arrangement to, for example, a computer system are serialized by the interface.
According to one embodiment, the memory arrangement includes several memory banks that can be accessed via several memory-bank access devices. In this case, for each of the memory-bank access devices it holds that memory cells of one or more memory banks can be accessed via a memory-bank access device. Access to memory cells of a defined memory bank, on the other hand, is possible only from exactly one memory-bank access device. Consequently several memory banks can be assigned to one memory-bank access device, but one memory bank cannot be assigned to various memory-bank access devices.
According to one embodiment, the memory arrangement is employed in dynamic random access memory (DRAM) memory modules on a common chip. Of course, the invention is not restricted to this memory application but can also be employed in read only memory (ROM) memory modules or other suitable memory modules.
According to one embodiment, the memory arrangement is employed in a computer system as read/write memory or DRAM memory.
Hereinafter, embodiments are described in more detail with reference to the drawings. The description relates firstly only to the receiving and decoding of data packets and consequently to the receiving and processing of write data, addressing data, and command data. The processing of read data is effected in analogous manner and will be described briefly at the end of the description.
FIG. 1 illustrates schematically an embodiment of a memory arrangement 10 with an even number of memory banks 6, a first memory-bank access device 1, and a second memory-bank access device 2. The sixteen memory banks 6 are partitioned into two areas. Like in FIG. 3, eight memory banks 6 are located in an upper area, and eight memory banks 6 are located in a lower area. Located between the upper area and the lower area is a narrow, strip-shaped area 7 in which the memory- bank access devices 1 and 2 and an interface 4 are located. This narrow area 7 between each of the eight memory banks is designated as the spine 7. The sixteen memory banks 6 are further partitioned into two groups of, in each instance, eight memory banks 6, in which, referring to FIG. 1, a left group defines the eight memory banks located on the left in a top view, and a right group defines the eight memory banks located on the right in the top view. One of the memory banks 6 pertaining to the left group is accessed via the first memory-bank access device 1, and one of the memory banks 6 pertaining to the right group is accessed via the second memory-bank access device 2. The interface 4 is arranged substantially at a center in a longitudinal direction of the spine 7; the first memory-bank access device 1, which is assigned to the left group of memory banks, is arranged substantially at a center of a left half of the spine 7; and the second memory-bank access device 2, which is assigned to the right group of memory banks, is arranged substantially at a center of a right half of the spine 7.
Instead of one temporary storage device 3 as illustrated in FIG. 4, which is arranged centrally therein in the spine 7, in the embodiment illustrated in FIG. 1 a first temporary storage device 5 and a second temporary storage device 5 are arranged respectively adjacent to one of the memory- bank access devices 1 and 2, respectively, the first temporary storage device 5 being arranged in an area that extends from the center of the spine in the direction of the first memory-bank access device 1, and the second temporary storage device 5 being arranged in an area that extends from the center of the spine in the direction of the second memory-bank access device 2. In one embodiment, the temporary storage devices 5 are arranged in the aforementioned areas in such a manner that they each have a spacing from the respectively adjacently arranged memory- bank access devices 1 and 2 that is as small as possible. The two temporary storage devices 5 are connected to the interface 4 via connecting lines that are arranged in an area 11. The two memory- bank access devices 1 and 2 are each connected to one of the two temporary storage devices 5 via connecting lines that are arranged in areas 12.
The area requirement of each temporary storage device 5 corresponds substantially to one half of the area requirement of the unpartitioned temporary storage device 3 of FIG. 4, since in each temporary storage device 5 only those data are stored which are to be stored in the memory banks 6 via the memory- bank access device 1 or 2 to which the respective temporary storage device 5 is connected. Since the write data are received by the interface 4 in several data packets, after they have been decoded by the interface 4 the write data are transmitted packet-by-packet from the interface 4 to the temporary storage devices 5. As a result of this partly serialized transmission between the interface 4 and the temporary storage device 5, the number of necessary connecting lines in the area 11 between the interface 4 and the temporary storage devices 5 is reduced. In an embodiment, in each portion of the area 11 approximately 30 connecting lines are arranged, wherein the portions of area 11 extend from the center of the spine in the direction of the memory- bank access devices 1 and 2, respectively. In the memory arrangement embodiment illustrated in FIG. 4, on the other hand, in each area 12 72 lines are arranged, wherein the areas 12 likewise extend from the center of the spine in the direction of the memory- bank access devices 1 and 2, respectively. As a result of the partitioning of the temporary storage devices 5 and as a result of the arrangement of the temporary storage devices 5 adjacent to the memory- bank access devices 1 and 2, only very short areas 12 are employed, in which 72 lines run, as FIG. 1 illustrates.
As a result of this partitioned arrangement of the temporary storage devices 5, considerably less chip area is employed in the middle of the spine 7. Furthermore, as a result of the diminished number of connecting lines in the area 11 less chip area is employed in the spine 7. In addition, as a result of the symmetrical arrangement of the temporary storage devices with respect to the memory-bank access devices a uniform timing drive of the individual memory banks is obtained in one embodiment. Even if, instead of an aforementioned partitioning of the temporary storage device, only a doubling of the temporary storage device is possible, for reasons concerned with control engineering, for example, by virtue of the saving of area in the case of the connecting lines and by virtue of the arrangement of the temporary storage devices outside the central area of the spine a possible reduction in the width of the spine is achieved.
FIG. 2 illustrates a schematic top view of an embodiment of a memory arrangement 10. The interface 4, the memory banks 6, the spine 7 and the memory- bank access devices 1, 2 are arranged similar to as described above in the description of FIG. 1. In this embodiment, four temporary storage devices 5 are arranged at four places in the memory arrangement 10, specifically in such a manner that two temporary storage devices 5 are arranged adjacent to each memory- bank access device 1 and 2, as illustrated in FIG. 2, a first of the temporary storage devices 5 being arranged to the left of the first memory-bank access device 1, a second of the temporary storage devices 5 being arranged between the center of the spine 7 and the first memory-bank access device 1, a third of the temporary storage devices 5 being arranged between the center of the spine 7 and the second memory-bank access device 2, and a fourth of the temporary storage devices 5 being arranged to the right of the second memory-bank access device 2.
The chip area employed for each of the four temporary storage devices 5 corresponds, in each instance, to approximately one quarter of the surface area of the unpartitioned temporary storage device 3 illustrated in FIG. 4, because in each of the four temporary storage devices 5 only that portion of the data is stored which is to be stored in the memory banks 6 via the memory- bank access device 1 or 2 to which the respective temporary storage devices 5 are connected. In turn, approximately 30 connecting lines are located in the area 11 between the interface 4 and the temporary storage devices 5. In the areas 12, on the other hand, only 36 connecting lines are now arranged between, in each instance, a temporary storage device and a memory-bank access device.
As a result of this further partitioning of the temporary storage devices 5, some of the chip area employed for the temporary storage devices 5 is placed in an area of the spine 7 that is not located between the two memory- bank access devices 1 and 2. By reason of its decentralised position, this area is, in any case, capable of being utilised only for a few devices of the spine, and is consequently not decisive for the width of the spine. Consequently, as a result of this partitioning the width of the spine 7 employed by the temporary storage devices 5 can be reduced further. A further advantage of this arrangement embodiment of the temporary storage devices 5 is that the memory- bank access devices 1 and 2 are now supplied symmetrically from both sides by the temporary storage devices 5, as a result of which the timing response of the memory arrangement is simplified.
The temporary storage devices embodiments described above may be employed advantageously in conjunction with the partitioning, according embodiments, of the temporary storage devices also in the case of the readout of data from the memory banks 6. Thus, for example, temporary storage devices 5 that are arranged between memory- bank access devices 1 and 2 and an interface 4, which is configured for transmitting, coding and decoding read data, addressing data and command data, have read data written to them from the memory banks 6 via the memory- bank access devices 1 and 2 by reason of a read request. After that, a readout of the temporary storage devices 5 is possible in temporally independent manner via data packets that are coded and transmitted by the interface 4.
Furthermore, according to an embodiment, temporary storage devices temporarily store commands and command sequences that are executed in a manner temporally independent of the receiving of the commands or command sequences, in order, for example, to refresh memory banks or to provide read data.
As described above, the embodiments described above with reference to the figures may be each realized in a dedicated chip or any combination of the embodiments described above may be realized within one chip combining the functionality and characteristics of these embodiments. It is also understood that all the embodiments described above are considered to be comprised by the present invention as it is defined by the appended claims.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (25)

1. A memory arrangement comprising:
an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol;
at least two memory banks, each memory bank including at least one memory cell;
at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks; and
at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices, wherein each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
2. The memory arrangement according to claim 1, wherein the interface is configured to transmit serialized data packets, wherein the interface comprises:
a device configured to parallelize and synchronize received data packets; and
a device configured to serialize data packets to be sent.
3. The memory arrangement according to claim 1, wherein the interface is configured to transmit, code and/or decode write data, read data, addressing data, and command data.
4. The memory arrangement according to claim 1, wherein the memory arrangement is configured such that for each memory cell of the at least two memory banks, a defined memory cell is accessed only via precisely one of the at least two memory-bank access devices.
5. The memory arrangement according to claim 1, wherein the memory arrangement is configured such that memory cells arranged in various memory banks are accessed via only one of the at least two memory-bank access devices.
6. The memory arrangement according to claim 1, wherein the memory arrangement comprises an even number of memory banks and precisely two memory-bank access devices, wherein the memory arrangement is configured such that the memory cells pertaining to a first half of the memory banks are accessed via the first memory-bank access device, and the memory cells pertaining to a second half of the memory banks are accessed via the second memory-bank access device.
7. The memory arrangement according to claim 1, wherein the memory arrangement comprises precisely two temporary-storage devices, wherein:
a first of the temporary-storage devices is arranged in an area extending from a center between a first of the memory-bank access devices and a second of the memory-bank access devices in a direction of the first memory-bank access device; and
a second of the temporary-storage devices is arranged in an area extending from the center between the first memory-bank access device and the second memory-bank access device in a direction of the second memory-bank access device.
8. The memory arrangement according to claim 7, wherein the memory arrangement is configured such that the data to be transmitted between the interface and the memory cells of one of the memory banks that can be accessed via the first memory-bank access device are temporarily stored only in the first temporary-storage device, and the data to be transmitted between the interface and the memory cells of one of the memory banks that can be accessed via the second memory-bank access device are temporarily stored only in the second temporary-storage device.
9. The memory arrangement according to claim 1, wherein the memory arrangement comprises precisely four temporary-storage devices, wherein:
a first of the temporary-storage devices is arranged in an area extending from a first of the memory-bank access devices in a direction that extends contrary to a direction from the first memory-bank access device to a second of the memory-bank access devices;
a second of the temporary-storage devices is arranged in an area extending between a center between the first memory-bank access device and the second memory-bank access device and the first memory-bank access device;
a third of the temporary-storage devices is arranged in an area extending between the center between the first memory-bank access device and the second memory-bank access device and the second memory-bank access device; and
a fourth of the temporary-storage devices is arranged in an area extending from the second memory-bank access device in a direction that extends contrary to a direction from the second memory-bank access device to the first memory-bank access device.
10. The memory arrangement according to claim 9, wherein the memory arrangement is configured such that:
the data to be transmitted between the interface and memory cells of a memory bank that is accessed via the first memory-bank access device are temporarily stored only in the first and second temporary-storage devices, the data comprising a first data portion and a remaining data portion, wherein first data portion is temporarily stored in the first temporary-storage device and the remaining data portion is temporarily stored in the second temporary-storage device; and
the write data to be transmitted between the interface and memory cells of a memory bank that is accessed via the second memory-bank access device are temporarily stored only in the third and fourth temporary-storage devices, the data comprising a first data portion and a remaining data portion, wherein the first data portion is temporarily stored in the third temporary-storage device and the remaining data portion is temporarily stored in the fourth temporary-storage device.
11. The memory arrangement according to claim 1, wherein each of the at least two temporary-storage devices is arranged adjacent to one of the at least two memory-bank access devices.
12. The memory arrangement according to claim 1, wherein the interface, the at least two memory banks, the at least two memory-bank access devices, and the two temporary-storage devices are arranged on a common chip.
13. The memory arrangement according to claim 1, wherein the memory arrangement is a dynamic random access memory (DRAM) memory arrangement.
14. The memory arrangement according to claim 1, wherein:
the interface is configured to receive and decode write data, addressing data, and command data;
the at least two memory-bank access devices are configured to store write data in the at least two memory banks; and
the at least two temporary-storage devices are configured to temporarily storing write data that are being transmitted from the interface to the at least two memory-bank access devices.
15. The memory arrangement according to claim 1, wherein:
the interface is configured to transmit, code and/or decode read data, addressing data, and command data;
the at least two memory-bank access devices are configured to read out read data from the at least two memory banks; and
wherein the at least two temporary-storage devices are configured to temporarily store read data that are being transmitted from one of the at least two memory-bank access devices to the interface.
16. The memory arrangement according to claim 15, wherein the memory arrangement is a read only memory (ROM) memory arrangement.
17. A memory arrangement comprising:
an interface configured to transmit, code and/or decoding data in the form of data packets in accordance with a predefined protocol;
a first memory bank comprising at least one memory cell;
a second memory bank comprising at least one memory cell;
a first memory-bank access device configured to facilitate accessing data of the at least one memory cell of the first memory bank;
a second memory-bank access device configured to facilitate accessing data of the at least one memory cell of the second memory bank;
a first temporary-storage device connected to the interface and to the first memory-bank access device and configured to temporarily store data being transmitted between the interface and the first memory-bank access device, wherein the first temporary-storage device is arranged in an area extending from a center between the first memory-bank access devices and the second memory-bank access devices in the direction of the first memory-bank access device; and
a second temporary-storage device connected to the interface and to the second memory-bank access device and configured to temporarily store data being transmitted between the interface and the second memory-bank access device, wherein the second temporary-storage device is arranged in an area extending from the center between the first memory-bank access device and the second memory-bank access device in the direction of the second memory-bank access device,
wherein the data to be transmitted between the interface and the at least one memory cell of the first memory bank are temporarily stored only in the first temporary-storage device, and the data to be transmitted between the interface and the at least one memory cell of the second memory bank are temporarily stored only in the second temporary-storage device.
18. The memory arrangement according to claim 17, wherein the interface is configured to transmit serialized data packets, and the interface comprises:
a device configured to parallelize and synchronize received data packets; and
a device configured to serialize data packets to be sent.
19. The memory arrangement according to claim 17, wherein the interface is configured to transmit, code and/or decode write data, read data, addressing data, and command data.
20. The memory arrangement according to claim 17, wherein:
the first temporary-storage device is arranged adjacent to the first memory-bank access device; and
the second temporary-storage device is arranged adjacent to the second memory-bank access device.
21. A memory arrangement comprising:
an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol;
a first memory bank comprising at least one memory cell;
a second memory bank comprising at least one memory cell;
a first memory-bank access device configured to facilitate accessing data of the at least one memory cell of the first memory bank;
a second memory-bank access device configured to facilitate accessing data of the at least one memory cell of the second memory bank;
a first temporary-storage device connected to the interface and to the first memory-bank access device, configured to temporarily store data being transmitted between the interface and the first memory-bank access device, and arranged in an area extending from the first memory-bank access device in a direction that extends contrary to a direction from the first memory-bank access device to the second memory-bank access device;
a second temporary-storage device connected to the interface and to the first memory-bank access device, configured to temporarily store data being transmitted between the interface and the first memory-bank access device, and arranged in an area extending between the first memory-bank access device and a center between the first memory-bank access device and the second memory-bank access device;
wherein data to be transmitted between the interface and memory cells of the first memory bank are temporarily stored only in the first and second temporary-storage devices, with a first data portion being temporarily stored in the first temporary-storage device and a remaining data portion being temporarily stored in the second temporary-storage device;
a third temporary-storage device connected to the interface and to the second memory-bank access device, configured to temporarily store data being transmitted between the interface and the second memory-bank access device, and arranged in an area extending between the second memory-bank access device and the center between the first memory-bank access device and the second memory-bank access device;
a fourth temporary-storage device connected to the interface and to the second memory-bank access device, configured to temporarily store data being transmitted between the interface and the fourth memory-bank access device, and arranged in an area extending from the second memory-bank access device in a direction that extends contrary to a direction from the second memory-bank access device to the first memory-bank access device; and
wherein data to be transmitted between the interface and memory cells of the second memory bank are temporarily stored only in the third and fourth temporary-storage devices, with a first data portion being temporarily stored in the third temporary-storage device and a remaining data portion being temporarily stored in the fourth temporary-storage device.
22. The memory arrangement according to claim 21, wherein the interface is configured to transmit serialized data packets, and the interface comprises:
a device configured to parallelize and synchronize received data packets; and
a device configured to serialize data packets to be sent.
23. The memory arrangement according to claim 21, wherein:
the first temporary-storage device is arranged adjacent to the first memory-bank access device;
the second temporary-storage device is arranged adjacent to the first memory-bank access device;
the third temporary-storage device is arranged adjacent to the second memory-bank access device; and
the fourth temporary-storage device is arranged adjacent to the second memory-bank access device.
24. A memory arrangement comprising:
means for transmitting, coding and/or decoding data in the form of data packets in accordance with a predefined protocol;
a first memory bank comprising at least one memory cell;
a second memory bank comprising at least one memory cell;
first means for facilitating accessing data of the at least one memory cell of the first memory bank;
second means for facilitating accessing data of the at least one memory cell of the second memory bank;
first means for temporarily storing data to be transmitted between the interface and the first means for facilitating accessing data, wherein the data to be transmitted between the interface and the at least one memory cell of the first memory bank are temporarily stored only in the first means for temporarily storing data; and
second means for temporarily storing data to be transmitted between the interface and the second means for facilitating accessing data, wherein the data to be transmitted between the interface and the at least one memory cell of the second memory bank are temporarily stored only in the second means for temporarily storing data.
25. A computer system comprising:
a data processing unit; and
a memory arrangement connected to the data processing unit, wherein the memory arrangement comprises:
an interface configured to transmit, code and/or decode data in the form of data packets in accordance with a predefined protocol, wherein the memory arrangement is connected to the data processing unit via the interface;
at least two memory banks, each memory bank including at least one memory cell;
at least two memory-bank access devices configured to facilitate accessing the data of the at least one memory cell of each of the at least two memory banks; and
at least two temporary storage devices configured to temporarily store data being transmitted between the interface and the at least two memory-bank access devices, wherein each of the at least two temporary storage devices is connected to the interface and to one of the at least two memory-bank access devices.
US11/679,609 2006-02-27 2007-02-27 Memory arrangement Expired - Fee Related US7536528B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10089043B2 (en) 2013-03-15 2018-10-02 Micron Technology, Inc. Apparatus and methods for a distributed memory system including memory nodes

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9779057B2 (en) 2009-09-11 2017-10-03 Micron Technology, Inc. Autonomous memory architecture
US9779138B2 (en) 2013-08-13 2017-10-03 Micron Technology, Inc. Methods and systems for autonomous memory searching
US10003675B2 (en) 2013-12-02 2018-06-19 Micron Technology, Inc. Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898623A (en) 1997-10-09 1999-04-27 International Business Machines Corporation Input port switching protocol for a random access memory
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
US20040202027A1 (en) 2003-01-21 2004-10-14 Maksim Kuzmenka Buffer amplifier architecture for semiconductor memory circuits
US20050097264A1 (en) 2003-10-31 2005-05-05 Park Kwang-Soo Memory module with registers
US20050180255A1 (en) 1997-10-10 2005-08-18 Tsern Ely K. Memory device having a read pipeline and a delay locked loop
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US7418526B2 (en) * 2004-03-29 2008-08-26 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898623A (en) 1997-10-09 1999-04-27 International Business Machines Corporation Input port switching protocol for a random access memory
US20050180255A1 (en) 1997-10-10 2005-08-18 Tsern Ely K. Memory device having a read pipeline and a delay locked loop
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US20040202027A1 (en) 2003-01-21 2004-10-14 Maksim Kuzmenka Buffer amplifier architecture for semiconductor memory circuits
US20050097264A1 (en) 2003-10-31 2005-05-05 Park Kwang-Soo Memory module with registers
US7418526B2 (en) * 2004-03-29 2008-08-26 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Crisp, Richard, "High Bandwidth RDRAM Technology Reduces System Cost," IEEE Proceedings of COMPCON '96, pp. 365-377 (1996).

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10089043B2 (en) 2013-03-15 2018-10-02 Micron Technology, Inc. Apparatus and methods for a distributed memory system including memory nodes
US10761781B2 (en) 2013-03-15 2020-09-01 Micron Technology, Inc. Apparatus and methods for a distributed memory system including memory nodes

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