US7662670B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- US7662670B2 US7662670B2 US11/488,890 US48889006A US7662670B2 US 7662670 B2 US7662670 B2 US 7662670B2 US 48889006 A US48889006 A US 48889006A US 7662670 B2 US7662670 B2 US 7662670B2
- Authority
- US
- United States
- Prior art keywords
- wiring
- semiconductor wafer
- protection film
- forming
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Abstract
Description
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/488,890 US7662670B2 (en) | 2002-10-30 | 2006-07-19 | Manufacturing method of semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002315418 | 2002-10-30 | ||
JP2002-315418 | 2002-10-30 | ||
US10/696,581 US7101735B2 (en) | 2002-10-30 | 2003-10-30 | Manufacturing method of semiconductor device |
US11/488,890 US7662670B2 (en) | 2002-10-30 | 2006-07-19 | Manufacturing method of semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/696,581 Continuation-In-Part US7101735B2 (en) | 2002-10-30 | 2003-10-30 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070026639A1 US20070026639A1 (en) | 2007-02-01 |
US7662670B2 true US7662670B2 (en) | 2010-02-16 |
Family
ID=32089519
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/696,581 Expired - Lifetime US7101735B2 (en) | 2002-10-30 | 2003-10-30 | Manufacturing method of semiconductor device |
US11/488,890 Expired - Fee Related US7662670B2 (en) | 2002-10-30 | 2006-07-19 | Manufacturing method of semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/696,581 Expired - Lifetime US7101735B2 (en) | 2002-10-30 | 2003-10-30 | Manufacturing method of semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (2) | US7101735B2 (en) |
EP (1) | EP1416529B8 (en) |
JP (1) | JP5258807B2 (en) |
CN (2) | CN101064270B (en) |
DE (1) | DE60321873D1 (en) |
TW (1) | TWI227550B (en) |
Cited By (34)
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US20080083976A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20080083965A1 (en) * | 2006-10-10 | 2008-04-10 | Samsung Electro-Mechanics Co., Ltd. | Wafer level chip scale package of image sensor and manufacturing method thereof |
US20080303131A1 (en) * | 2007-06-11 | 2008-12-11 | Vertical Circuits, Inc. | Electrically interconnected stacked die assemblies |
US20090194154A1 (en) * | 2008-02-01 | 2009-08-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US20100270679A1 (en) * | 2006-10-17 | 2010-10-28 | Tessera, Inc. | Microelectronic packages fabricated at the wafer level and methods therefor |
US20110169139A1 (en) * | 2010-01-13 | 2011-07-14 | Chia-Sheng Lin | Chip package and fabrication method thereof |
US20110169159A1 (en) * | 2010-01-13 | 2011-07-14 | Chia-Sheng Lin | Chip package and fabrication method thereof |
US20110285025A1 (en) * | 2010-05-24 | 2011-11-24 | Yuping Gong | Wafer Level Chip Scale Package Method Using Clip Array |
US8349654B2 (en) | 2006-12-28 | 2013-01-08 | Tessera, Inc. | Method of fabricating stacked packages with bridging traces |
US8426957B2 (en) | 2006-10-10 | 2013-04-23 | Tessera, Inc. | Edge connect wafer level stacking |
US8466542B2 (en) | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
US8476774B2 (en) | 2006-10-10 | 2013-07-02 | Tessera, Inc. | Off-chip VIAS in stacked chips |
US8513794B2 (en) | 2007-08-09 | 2013-08-20 | Tessera, Inc. | Stacked assembly including plurality of stacked microelectronic elements |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US8680687B2 (en) | 2009-06-26 | 2014-03-25 | Invensas Corporation | Electrical interconnect for die stacked in zig-zag configuration |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
US8729690B2 (en) | 2004-04-13 | 2014-05-20 | Invensas Corporation | Assembly having stacked die mounted on substrate |
US8735262B2 (en) | 2011-10-24 | 2014-05-27 | Infineon Technologies Ag | Semiconductor device having a through contact and a manufacturing method therefor |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US8884403B2 (en) | 2008-06-19 | 2014-11-11 | Iinvensas Corporation | Semiconductor die array structure |
US8912661B2 (en) | 2009-11-04 | 2014-12-16 | Invensas Corporation | Stacked die assembly having reduced stress electrical interconnects |
US20150099357A1 (en) * | 2013-10-08 | 2015-04-09 | Xintec Inc. | Method of fabricating wafer-level chip package |
US9147583B2 (en) | 2009-10-27 | 2015-09-29 | Invensas Corporation | Selective die electrical insulation by additive process |
US9153517B2 (en) | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
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Also Published As
Publication number | Publication date |
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JP5258807B2 (en) | 2013-08-07 |
CN101064270A (en) | 2007-10-31 |
TW200411853A (en) | 2004-07-01 |
JP2010098337A (en) | 2010-04-30 |
US20070026639A1 (en) | 2007-02-01 |
TWI227550B (en) | 2005-02-01 |
US20040137723A1 (en) | 2004-07-15 |
US7101735B2 (en) | 2006-09-05 |
CN1296981C (en) | 2007-01-24 |
DE60321873D1 (en) | 2008-08-14 |
EP1416529B1 (en) | 2008-07-02 |
EP1416529A1 (en) | 2004-05-06 |
EP1416529B8 (en) | 2008-10-29 |
CN101064270B (en) | 2011-12-07 |
CN1512553A (en) | 2004-07-14 |
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