US7795091B2 - Method of forming a split gate memory device and apparatus - Google Patents
Method of forming a split gate memory device and apparatus Download PDFInfo
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- US7795091B2 US7795091B2 US12/112,664 US11266408A US7795091B2 US 7795091 B2 US7795091 B2 US 7795091B2 US 11266408 A US11266408 A US 11266408A US 7795091 B2 US7795091 B2 US 7795091B2
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- 239000007943 implant Substances 0.000 claims description 50
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- 239000002019 doping agent Substances 0.000 claims description 28
- 230000000903 blocking effect Effects 0.000 claims description 24
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 11
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- 230000015572 biosynthetic process Effects 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
Definitions
- FIGS. 1-17 illustrate in cross-sectional form a method for forming a split gate memory device in accordance with the present invention
- FIG. 3 Illustrated in FIG. 3 is further processing of semiconductor device 10 wherein a gate material layer 24 is deposited over the substrate 12 and onto each of the dielectric layer 14 and the dielectric layer 22 .
- the gate material layer 24 is a layer of polysilicon that is undoped. In other forms various materials which are conductive, or which are conductive when doped, may be used in lieu of polysilicon to implement the gate material layer 24 .
- FIG. 8 Illustrated in FIG. 8 is further processing of semiconductor device 10 wherein a mask (not shown) is provided over a portion of the ARC layer 42 where a control gate is desired to be located within the memory circuitry 13 . With the mask in place, all exposed portions of the ARC layer 42 , the gate material layer 40 and the discrete charge storage layer 36 are etched and removed. The resulting structure of FIG. 8 has a control gate 44 of N type conductivity that is formed from a remainder of the previously insitu doped N-type gate material layer 40 .
- the memory circuitry 13 thus has a memory cell having a select gate from gate material layer 24 that is doped with P conductivity and a control gate 44 that is doped with N conductivity.
- FIG. 13 Illustrated in FIG. 13 is further processing of semiconductor device 10 wherein a dopant is ion implanted into exposed regions of the substrate 12 .
- N-type dopants in the source/drain regions correspond to an N-channel memory device whereas P-type dopants in the source/drain regions correspond to a P-channel memory device.
- Deep source and drain implants are thereby performed to create a source implant region 58 and a drain implant region 60 within the other circuitry 11 . This implant also results in N-type doping of the gate 48 which is desired. Additionally formed are a source implant region 62 and a drain implant region 64 within the substrate 12 for the memory cell of the memory circuitry 13 .
- the resulting source and drain of the memory cell of memory circuitry 13 is now aligned with the overlying edges of the select gate 46 and the control gate 44 .
- the ARC layer 34 protects the underlying select gate 46 from the doping effects of the ion implantation used to form the source and drain extension implants.
- Illustrated in FIG. 16 is further processing of semiconductor device 10 wherein the ARC layer 42 is removed from above the control gate 44 that has N conductivity. Also, exposed portions of the ARC layer 34 is removed from above the select gate 46 that has P conductivity. An unexposed portion of ARC layer 34 that underlies the discrete charge storage layer 36 is left intact. A conventional etch is used to remove the exposed portions of the ARC layer 42 and ARC layer 34 .
- the threshold voltage of the control gate is higher than the threshold voltage of the select gate in the case where the work functions of the channel regions underlying the control gate and the select gate are similar.
- the work function of the select gate is lower than the work function of the channel below it and the work function of the control gate is higher than the channel below it for the case of a substrate that is doped N-type.
- the counter doped region is formed by implanting N-type dopant species for the first majority carrier type split-gate memory device.
- the counter doped region is configured to lower the work function of the channel region.
- the counter doped region is configured to raise the work function of the channel region.
- the select gate is formed by forming a layer of select gate dielectric over at least the first portion of the substrate. A layer of select gate material is formed overlying the layer of select gate dielectric. Dopant is implanted into the layer of select gate material, wherein the dopant comprises a conductivity type suitable for establishing the first work function.
- the control gate is defined in the layer of control gate material. Defining the control gate includes etching to remove the layer of control gate material and the discrete charge storage layer in at least a region not intended for use as the control gate. A portion of the control gate overlies the second portion of the substrate.
- the implant blocking layer is a nitride antireflective coating (ARC) layer.
- ARC nitride antireflective coating
- a portion of the control gate also overlies the first edge of the select gate.
- the select gate is formed by defining a second edge of the select gate.
- a control gate is formed having a second work function overlying a second portion of the substrate proximate the first portion.
- the first work function is greater than the second work function.
- the second majority carrier type split-gate memory device wherein the second majority carrier type comprises holes, the first work function is less than the second work function.
- a first current electrode is formed in the substrate.
- a second current electrode is formed in the substrate separated from the first current electrode by a channel underlying the control gate and select gate.
- the select gate is formed by forming an implant blocking layer overlying the layer of select gate material.
- a first edge of the select gate is defined in the layer of select gate material, wherein defining the first edge includes etching to remove the implant blocking layer, the layer of select gate material and the layer of select gate dielectric in at least a region overlying the second portion of the substrate intended for use with respect to the control gate.
- the control gate in one form is formed by forming a discrete charge storage layer overlying (i) the implant blocking layer, (ii) the layer of select gate material, (iii) the first edge of the select gate, and (iv) a surface of the substrate exposed by defining the first edge of the select gate.
- a layer of control gate material is formed overlying the discrete charge storage layer.
- the control gate is defined in the layer of control gate material by etching to remove the layer of control gate material and the discrete charge storage layer in at least a region not intended for use as the control gate. A portion of the control gate overlies the second portion of the substrate.
- a split-gate memory device having a select gate having a first work function overlying a first portion of a substrate.
- a control gate has a second work function overlying a second portion of the substrate proximate the first portion, wherein (i) for a first majority carrier type split-gate memory device, wherein the first majority carrier type comprises electrons, the first work function is greater than the second work function and (ii) for a second majority carrier type split-gate memory device, wherein the second majority carrier type comprises holes, the first work function is less than the second work function.
- a first current electrode in the substrate and a second current electrode in the substrate is separated from the first current electrode by a channel underlying the control gate and select gate.
Abstract
Description
Claims (16)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/112,664 US7795091B2 (en) | 2008-04-30 | 2008-04-30 | Method of forming a split gate memory device and apparatus |
JP2011507498A JP2011519489A (en) | 2008-04-30 | 2009-02-26 | Method and apparatus for forming split gate memory device |
PCT/US2009/035299 WO2009154813A2 (en) | 2008-04-30 | 2009-02-26 | Method of forming a split gate memory device and apparatus |
TW098107107A TW200947627A (en) | 2008-04-30 | 2009-03-05 | Method of forming a split gate memory device and apparatus |
Applications Claiming Priority (1)
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US12/112,664 US7795091B2 (en) | 2008-04-30 | 2008-04-30 | Method of forming a split gate memory device and apparatus |
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US20090273013A1 US20090273013A1 (en) | 2009-11-05 |
US7795091B2 true US7795091B2 (en) | 2010-09-14 |
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US12/112,664 Expired - Fee Related US7795091B2 (en) | 2008-04-30 | 2008-04-30 | Method of forming a split gate memory device and apparatus |
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US (1) | US7795091B2 (en) |
JP (1) | JP2011519489A (en) |
TW (1) | TW200947627A (en) |
WO (1) | WO2009154813A2 (en) |
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US20110207274A1 (en) * | 2010-02-22 | 2011-08-25 | Kang Sung-Taeg | Method for forming a split-gate memory cell |
US8524557B1 (en) | 2012-02-22 | 2013-09-03 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic |
US8530950B1 (en) * | 2012-05-31 | 2013-09-10 | Freescale Semiconductor, Inc. | Methods and structures for split gate memory |
US20130264633A1 (en) * | 2012-04-09 | 2013-10-10 | Mark D. Hall | Logic transistor and non-volatile memory cell integration |
US8658497B2 (en) | 2012-01-04 | 2014-02-25 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8669158B2 (en) | 2012-01-04 | 2014-03-11 | Mark D. Hall | Non-volatile memory (NVM) and logic integration |
US8716089B1 (en) | 2013-03-08 | 2014-05-06 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage |
US8728886B2 (en) | 2012-06-08 | 2014-05-20 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric |
US8741719B1 (en) | 2013-03-08 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique |
US8797800B1 (en) | 2013-04-02 | 2014-08-05 | Sandisk Technologies Inc. | Select gate materials having different work functions in non-volatile memory |
US8871598B1 (en) | 2013-07-31 | 2014-10-28 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
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Also Published As
Publication number | Publication date |
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TW200947627A (en) | 2009-11-16 |
WO2009154813A2 (en) | 2009-12-23 |
JP2011519489A (en) | 2011-07-07 |
US20090273013A1 (en) | 2009-11-05 |
WO2009154813A3 (en) | 2010-03-04 |
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