US8385476B2 - Digital phase locked loop - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
- H03C3/09—Modifications of modulator for regulating the mean frequency
- H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
- H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
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Abstract
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.
Description
This application claims the benefit of the filing date of copending provisional application U.S. Ser. No. 60/286,572, filed Apr. 25, 2001, entitled “Frequency Synthesizer Architecture of the Digital Radio Processor (v2.0)” to Staszewski et al.
Not Applicable
1. Technical Field
This invention relates in general to electronics and, more particularly, to a digital phase locked loop.
2. Description of the Related Art
A great reduction of the transistor features in recently developed deep-submicron CMOS processes shifts the design paradigm towards more digitally-intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of a number of devices used but rather in terms of the occupied silicon area, no matter what the actual circuit complexity.
Analog and RF circuits used in communication circuits, however, are not easily implemented in a deep-submicron CMOS process. For example, in Texas Instruments' CMOS process (C035) of 0.08 μm L-effective features a digital gate density of 150K equivalent (2-input NAND) gates per mm2. An average-size inductor for an integrated LC oscillator occupies about 0.5 mm2 of silicon area. A low-noise charge pump, or a low-distortion image-reject modulator, both good examples of classical RF transceiver components, occupy roughly about the same area, which could be traded for tens of thousands of digital gates.
Migrating to a digitally-intensive synthesizer architecture brings forth the following well-known advantages: (1) fast design turn-around cycle using automated CAD tools (VHDL or Verilog hardware-level description language, synthesis, auto-place and auto-route with timing-driven algorithms, parasitic backannotation and postlayout optimization), (2) much lower parameter variability than with analog circuits, (3) ease of testability, (4) lower silicon area and dissipated power that gets better with each CMOS technology advancement (also called a “process node”) and (5) excellent chances of first-time silicon success. Commercial analog circuits usually require several design iterations to meet marketing requirements.
There is a wide array of opportunities that integration presents. The most straightforward way would be to merge various digital sections into a single silicon die, such as DRAM or Flash memory embedded into DSP or controller. More difficult would be integrating the analog baseband with the digital baseband. Care must be taken here to avoid coupling of digital noise into the high-precision analog section. In addition, the low amount of voltage headroom challenges one to find new circuit and architecture solutions. Integrating the analog baseband into RF transceiver section presents a different set of challenges: the conventional Bi-CMOS RF process is tuned for high-speed operation with a number of available passive components and does not fundamentally stress high precision.
Sensible integration of diverse sections results in a number of advantages: (1) lower total silicon area—in a deep-submicron CMOS design, the silicon area is often bond-pad limited; consequently, it is beneficial to merge various functions on a single silicon die to maximize the core to bond-pad ratio, (2) lower component count and thus lower packaging cost, (3) power reduction—no need to drive large external inter-chip connections and (4) lower printed—circuit board (PCB) area, thus saving the precious “real estate.”
Deep-submicron CMOS processes present new integration opportunities on one hand, but make it extremely difficult to implement traditional analog circuits, on the other. One such problem involves the design of a digital phase locked loop (DPLL). A PLL loop is a fixed-point phase domain architecture whose purpose is to generate a stable RF signal at a desired frequency. The underlying frequency stability of the system is derived from a reference clock generated by a crystal oscillator, such as a temperature-compensated crystal oscillator (TCXO) used in mobile phones. Phase information between the output signal and the reference signal is used to update a controllable oscillator. This information is generated at an active edge of the reference clock. However, greater accuracy could be obtained by more frequent determinations of the phase information, leading to more frequent updates of the controllable oscillator.
Therefore, a need has arisen for a method and apparatus for a phase locked loop design that provides for increase accuracy in the output signal.
In a first aspect of the present invention, a phase locked loop circuit includes a controllable oscillator for generating an output signal of desired frequency, a first phase detection circuit for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The controllable oscillator is driven responsive to the outputs of the first and second phase detections circuits.
This aspect of the invention increases the timing updates for the phase-locked loop since both edges of the reference clock are used for phase detection.
In a second aspect of the present invention, a mobile communication device comprises a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock, circuitry for generating multiple clock signals of different frequencies synchronous to the carrier frequency output and digital baseband circuitry operating responsive to one or more of the multiple clock signals.
This aspect of the present invention allows for a plurality of clocks to be derived from the output of a frequency synthesizer. By reducing the number of phase-locked loop circuits use to generate clocks, unnecessary circuitry can be eliminated. Further, by providing a number of clocks synchronous to the RF carrier frequency, spurious noise throughout the mobile communication device can be controlled to reduce the effect on communications. An additional benefit is that complex circuitry for synchronizing the local reference signal to a master clock signal can be eliminated, and the carrier frequency can be synchronized to the master clock through minor adjustments to a phase error signal.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The present invention is best understood in relation to FIGS. 1-13 of the drawings, like numerals being used for like elements of the various drawings.
In general, the phase detector (and, hence, the controllable oscillator) operates responsive to an active edge of the FREF signal. For purposes of illustration throughout this specification, it will be assumed that the rising edge of FREF is the active edge; alternatively, the falling edge could be used as the active edge of FREF.
In many situations, it would be beneficial to compare the phases and update the output signal more often. One possible solution would be to clock the phase detector and controllable oscillator at both the rising and falling edges of FREF.
As shown in FIG. 1 b, however, clocking on both edges of the reference signal presents a problem. While the output of a crystal oscillator produces a signal with a fairly accurate 50% duty cycle (i.e., the time between a rising edge and the subsequent falling edge is exactly the same as the time between a falling edge and a subsequent rising edge), intervening circuitry can affect the duty cycle, such that the falling edge may occur within a range 20 in FIG. 1 b. Consequently, the falling edge of FREF cannot be used as a mid-point between rising edges of FREF.
As shown in FIG. 2 , the present invention uses a property of FREF to gain useful information from the falling edge of FREF. In FIG. 2 , dashed line 22 shows the ideal 50% duty cycle mark for the falling edge. While the actual falling edge, shown at line 24 may be offset from the ideal, the time period Tfall between actual falling edges 24 equals the time period Trise between rising edges. Thus, for each cycle, the actual falling edge 24 will be offset from the ideal 22 by a constant Δφ.
It would also be possible to compare the edges of FREF with the output CKV. In this case, both the rising edge and falling edge of FREF would be compared to a rising edge of CKV, if N (fCKV/fFREF) was an even integer. If N is an odd integer, two approaches could be used. In the first approach, rising edges of FREF would be compared to rising edges of CKV and falling edges of FREF would be compared to falling edges of CKV (it would also be possible to compare rising edges of FREF to falling edges of CKV and vice-versa). In the second embodiment, a half-phase adjustment φH could be added to φ2′ along with Δφ by the phase offset adder 36, such that φ2=φ2′+Δφ+φH.
FCW (frequency control word) is the ratio of the desired frequency of CKV divided by the frequency of FREF. The reference phase signal is an accumulation of FCW at the active edge of CKR, which is the retimed FREF clock. The FCW input to the reference accumulator 62 is used to establish the operating reference phase of the desired channel plus the modulation data.
The variable phase accumulator 66 comprises a counter 66 a, which increments on each active edge of CKV and a latch 66 b that latches the output of the counter at CKR.
The fractional phase circuit 64 determines a difference between an active edge of FREF and the next active edge of CKV, normalized to a fraction of a CKV clock cycle.
Operation of the circuit is best understood in relation to the timing diagram of FIG. 4 b, where an example of FCW=2.25 is used. In an actual circuit, however, FCW would typically be much higher. For purposes of illustration, FCW is a constant (i.e., no modulation) and there is no drift. As described above, the variable phase circuit 66 counts the CKV clocks and latches the count on the active (rising) edge of CKR. The PHV from the variable phase circuit 66 counts are provided above the CKV signal. Also at each active edge of CKR, the reference phase circuit 62 accumulates another FCW.
At any active edge of CKR, the preceding active edge of FREF may have occurred at a point less than one CKV clock cycle earlier (since CKR is retimed to CKV). This is shown by the dashed lines in FIG. 4 b. PHF measures this fractional part of a CKV cycle. As can be seen in FIG. 4 b, for the steady state situation, without drift or modulation, the addition of PHF and PHR will equal PHV and PHE will be zero.
The operation of the circuit is shown in FIG. 7 , which shows the Q(1 . . . L) values (L=10 in the illustrated embodiment) at the active edge of FREF. In the illustrated example, the falling edge of CKV that immediately precedes FREF is displaced by two inverter delays, while the rising edge of CKV that immediately precedes FREF is displaced by six inverter delays.
While FIG. 5 shows two fractional phase detectors 64 a and 64 b, the functions of the two devices could be combined into a single circuit that shares hardware, such as the string of inverters 92 and the psuedo-thermometer code edge detector 96.
Additional detail on the operation of time-to-digital converter 90 can be found in U.S. Ser. No. 09/608,317, now U.S. Pat. No. 6,429,693 filed Jun. 30, 2000, entitled “Digital Fractional Phase Detector” to Staszewski et al and in U.S. Ser. No. 09/967,275, now U.S. Pat. No. 6,593,773, filed Sep. 28, 2001, entitled “Power Saving Circuitry Using Predictive Logic” to Staszewski et al, both of which are incorporated by reference herein.
In operation, the controllable oscillator 42 updates the signal twice per FREF clock cycle, driven by the average of the sum of the most recent outputs of the phase detectors as shown by Table 1. As in the case of FIG. 4 a, it is assumed that phase detector 102 compares the rising edge of FREF with the rising edge of CKVD and phase detector 104 compares the falling edge of FREF with the falling edge of CKVD. It would also be possible to compare the edges of FREF with the output CKV. In this case, both the rising edge and falling edge of FREF could be compared to a rising edge of CKV, if N (fCKV/fFREF) was an even integer. If N is an odd integer, rising edges of FREF could be compared to rising edges of CKV and falling edges of FREF would be compared to falling edges of CKV (it would also be possible to compare rising edges of FREF to falling edges of CKV and vice-versa). Another possibility would b to add an offset φH, as described above.
TABLE 1 |
PHASE ERROR CALCULATION |
Clock cycle | φE | |
n (rising) | φ1(n) + φ2(n − 1) | |
n (falling) | φ1(n) + φ2(n) | |
n + 1 (rising) | φ1(n + 1) + φ2(n) | |
n + 1 (falling) | φ1(n + 1) + φ2(n + 1) | |
n + 2 (rising) | φ1(n + 2) + φ2(n + 1) | |
n + 2 (falling) | φ1(n + 2) + φ2(n + 2) | |
TABLE 2 |
PHASE ERROR CALCULATION |
Clock cycle | φE | |
n (rising) | φ1(n) + φ2(n − 1) | |
n + 1 (rising) | φ1(n + 1) + φ2(n) | |
n + 2 (rising) | φ1(n + 2) + φ2(n + 1) | |
This embodiment differs from the embodiment of FIG. 8 in that the phase error driving the controllable oscillator 42 is updated only once per FREF cycle, although phase error contains components of updates performed twice during the FREF signal.
Additionally, there may be several clocks in the digital baseband circuit 136 that run independently of the clocks in the RF transceiver 132. This can cause significant noise, especially if the RF transceiver circuit were to be fabricated on the same circuit as the digital baseband circuit.
In operation, the CKV signal is may be divided down by several frequency dividers 148 to provide suitable clock signals for devices in both the RF transceiver 132 and the digital baseband circuitry 136. For example, by generating a CKV having a frequency of 2.4 GHz, the signal could be divided to a clock of about 8 MHz for generating data samples for a Bluetooth application and could be divided to a clock of about 100 MHz for generating samples in an 802.11b application. Other divided clock frequencies could be used for purposes other the data symbol generation. Preferably, the frequency dividers divide by a power of two.
In operation, the data modulation circuit creates sample points based on the symbols received from the digital baseband circuit 136. In the prior art, a “chip clock” is used to generate these samples at a desired frequency. In general, the chip clock is a multiple of the reference clock and requires a clock generation circuitry, such as a PLL to generate a higher frequency clock from the reference clock. In the illustrated embodiment, however, a clock derived from the output of the DCO 146 (i.e., CKVD2) is used for the chip clock, by dividing the output of the DCO. A data modulation circuit of this type is disclosed in U.S. Ser. No. 10/001,448 to Staszewski et al, entitled “Transmit Filter”, filed Oct. 31, 2001, which is incorporated by reference herein. An apparent data rate can be adjusted by dynamically changing the oversampling ratio of the transmit filter.
Any number of clock frequencies could be generated from CKV. These clocks could be used in the various parts of a device, in particular in the digital baseband circuit 136 and throughout the RF transceiver 132, eliminating multiple clock generation circuits. Additionally, using clocks generated from CKV in both the baseband circuit 136 and in the RF transceiver 132 provides many significant advantages. For example, since the clocks in the two subsystems are interrelated, operations occurring in the digital baseband circuit 136 could be timed to cause the least possible spurious noise in the RF transceiver 132.
A value Δ, an integer indicating a relative position of the CKVD2 clock to the free-running FREF frequency reference, is passed back to the digital baseband circuit 136 where it may be used for synchronization, framing, timing adjustment of the fractional rate of the modulating data, and phase/frequency adjustment of the synthesized RF frequency with MCLK. FREF can now operate in a free-running mode (i.e., not adjusted by MCLK). The master clock MCLK synchronization circuit would now perform adjustment of the center frequency of the RF oscillator, rather than adjust FREF. Adjustments to the center frequency can be made by adjustments to φE. Since FREF is a very stable clock and since MCLK updates are infrequent, adjustments are very small and occur over long periods of time.
In FIGS. 12 and 13 , the phase detection circuits are clocked by a signal that is a division of CKV. Instead of using CKR, which is the FREF clock retimed to CKV clock (see FIG. 5 ), as the system clock, a power-of-two division (or any other division) of CKV could be used as the system clock. Comparison events in the phase detector would be triggered by the FREF clock in which the clock timing delay is obtained by time-to-digital converters (see FIG. 6 ) and the result used to perform phase value adjustment.
As can be seen in FIGS. 12 and 13 , some or all of the frequency dividers 148 are controlled by a modulus control (MC) signal. This signal is used to indicate a divisor. For example, for a divide-by-8/9 frequency divider, MC=8/9. MC could vary dynamically during operation of the device in order to obtain a fractional division ratio.
Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the Claims.
Claims (15)
1. A mobile communications device comprising:
a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock;
circuitry for generating multiple clock signals of different frequencies synchronous to said carrier frequency output;
digital baseband circuitry operating responsive to one or more of said multiple clock signals;
wherein said frequency synthesizer includes one or more phase detectors that perform timing updates with said local reference clock responsive to one of said multiple clock signals; and
wherein said one or more phase detectors provide information on phase differential between said local reference clock and one of said multiple clocks to said digital baseband circuitry.
2. The mobile communications device of claim 1 wherein said local reference clock runs independently of said master clock in the mobile communications device.
3. The mobile communications device of claim 1 wherein said circuitry for generating multiple clock signals comprises one or more frequency divider circuits.
4. The mobile communications device of claim 3 wherein said one or more frequency divider circuits are dynamically programmable with a divisor.
5. A method of processing mobile communications, comprising the steps of:
generating a carrier frequency output responsive to a local reference clock;
generating multiple clock signals of different frequencies synchronous to said carrier frequency output;
operating digital baseband circuitry responsive to one or more of said multiple clock signals;
wherein said step of generating a carrier frequency comprises the step of performing timing updates with said local reference clock responsive to one or more phase detectors coupled to one of said multiple clock signals; and
communicating information on phase differential between said local reference clock and one of said multiple clocks from said one or more phase detectors to said digital baseband circuitry.
6. The method of claim 5 wherein said step of generating multiple clock signals comprises the step of dividing modulated carrier frequency output using one or more frequency divider circuits.
7. The method of claim 6 wherein said dividing step includes the step of dynamically changing a divisor in said one or more frequency divider circuits.
8. A mobile communications device comprising:
a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock;
circuitry for generating a clock signal synchronous to said carrier frequency output;
digital baseband circuitry operating responsive to said clock signal;
wherein said frequency synthesizer includes one or more phase detectors that perform timing updates with said local reference clock responsive to said clock signal; and
wherein said one or more phase detectors provide information on phase differential between said local reference clock and said clock signal to said digital baseband circuitry.
9. The mobile communications device of claim 8 wherein said local reference clock runs independently of master clock in the mobile communications device.
10. The mobile communications device of claim 8 wherein said circuitry for generating said clock signal comprises one or more frequency divider circuits.
11. The mobile communications device of claim 10 wherein said one or more frequency divider circuits are dynamically programmable with a divisor.
12. A mobile communications device comprising:
a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock;
circuitry for generating a clock signal synchronous to said carrier frequency output;
digital baseband circuitry clocked on said clock signal;
wherein said frequency synthesizer includes one or more phase detectors that perform timing updates with said local reference clock responsive to said clock signal; and
wherein said one or more phase detectors provide information on phase differential between said local reference clock and said clock to said digital baseband circuitry.
13. The mobile communications device of claim 12 wherein said local reference clock runs independently of master clock in the mobile communications device.
14. The mobile communications device of claim 12 wherein said circuitry for generating a clock signal comprises one or more frequency divider circuits.
15. The mobile communications device of claim 14 wherein said one or more frequency divider circuits are dynamically programmable with a divisor.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/131,523 US8385476B2 (en) | 2001-04-25 | 2002-04-24 | Digital phase locked loop |
US13/710,691 US8742808B2 (en) | 2001-04-25 | 2012-12-11 | Digital phase locked loop |
US13/710,722 US20140010337A1 (en) | 2001-04-25 | 2012-12-11 | Digital phase locked loop |
US14/525,965 US9094184B2 (en) | 2001-04-25 | 2014-10-28 | First and second phase detectors and phase offset adder PLL |
US14/743,900 US9294108B2 (en) | 2001-04-25 | 2015-06-18 | RF circuit with DCO, state machine, latch, modulator, timing update |
US15/007,973 US9680487B2 (en) | 2001-04-25 | 2016-01-27 | RF circuit, DCO, frequency divider with three divided clock outputs |
US15/591,702 US9893735B2 (en) | 2001-04-25 | 2017-05-10 | Digital phase locked loop |
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US14/743,900 Expired - Fee Related US9294108B2 (en) | 2001-04-25 | 2015-06-18 | RF circuit with DCO, state machine, latch, modulator, timing update |
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US14/743,900 Expired - Fee Related US9294108B2 (en) | 2001-04-25 | 2015-06-18 | RF circuit with DCO, state machine, latch, modulator, timing update |
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2012
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2014
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2015
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2016
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Also Published As
Publication number | Publication date |
---|---|
US9680487B2 (en) | 2017-06-13 |
US9294108B2 (en) | 2016-03-22 |
US20170244417A1 (en) | 2017-08-24 |
US8742808B2 (en) | 2014-06-03 |
US20130093480A1 (en) | 2013-04-18 |
EP1261134A2 (en) | 2002-11-27 |
US20150043699A1 (en) | 2015-02-12 |
EP1261134A3 (en) | 2004-11-24 |
US9094184B2 (en) | 2015-07-28 |
US9893735B2 (en) | 2018-02-13 |
US20140010337A1 (en) | 2014-01-09 |
US20020191727A1 (en) | 2002-12-19 |
US20150288369A1 (en) | 2015-10-08 |
US20160142065A1 (en) | 2016-05-19 |
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