|Veröffentlichungsdatum||11. Juni 2013|
|Eingetragen||9. Apr. 2010|
|Prioritätsdatum||9. Apr. 2010|
|Auch veröffentlicht unter||US20110252220|
|Veröffentlichungsnummer||12757330, 757330, US 8464030 B2, US 8464030B2, US-B2-8464030, US8464030 B2, US8464030B2|
|Erfinder||Fadi Busaba, Brian Curran, Lee Eisen, Bruce Giamei, David Hutton|
|Ursprünglich Bevollmächtigter||International Business Machines Corporation|
|Zitat exportieren||BiBTeX, EndNote, RefMan|
|Patentzitate (54), Nichtpatentzitate (7), Referenziert von (1), Klassifizierungen (9), Juristische Ereignisse (2)|
|Externe Links: USPTO, USPTO-Zuordnung, Espacenet|
The present invention generally relates to microprocessors, and more particularly relates to managing variable length instructions.
Various conventional approaches for increasing IPC (Instruction per cycle) crack instructions into a simpler set of unit of operations (Uops). However, although these approaches crack the instructions into Uops, the cracking is generally not directed towards efficient use of the issue queues, Therefore, the issues queues can suffer in performance and issue bandwidth.
In one embodiment, a method for one of cracking and shortening computer executable instructions is disclosed. The method comprises receiving at least one instruction. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified based on the analyzing. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed based on the instruction type that has been identified. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operations based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed and the at least one instruction; and the at least one instruction is shortened based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed. The set of unit of operations is then executed.
In another embodiment, an information processing system for one of cracking and shortening computer executable instructions is disclosed. The information processing system comprising a memory and a processor communicatively coupled to the processor. The processor comprises an instruction decode unit. The instruction decode unit for receiving at least one instruction; analyzing the at least one instruction; and identifying, based on the analyzing, an instruction type associated with the at least one instruction. The instruction decode unit being further for analyzing, based on the instruction type that has been identified, at least one of a base field, an index field, one or more operands, and a mask field of the instruction. The processor further comprises a cracking unit and an instruction shortening unit. The processor for performing at least one of one organizing, via the cracking unit based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed, the at least one instruction into a set of unit of operations; and shortening, based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed, the at least one instruction. The processor being further for executing the set of unit of operations.
In yet another embodiment, a computer program product for one of cracking and shortening computer executable instructions is disclosed. The computer program product comprises a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method comprises receiving at least one instruction. The at least one instruction is analyzed. An instruction type associated with the at least one instruction is identified based on the analyzing. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed based on the instruction type that has been identified. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operations based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed and the at least one instruction; and the at least one instruction is shortened based on the at least one of the base field, the index field, the one or more operands, and the mask field of the instruction that have been analyzed. The set of unit of operations is then executed.
The accompanying figures where like reference numerals refer to identical or functionally similar elements throughout the separate views, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention, in which:
As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely examples of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure and function. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention.
The terms “a” or “an”, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. Plural and singular terms are the same unless expressly stated otherwise.
Also, one or more of the nodes 102, 104 comprises mass storage interface 140. The mass storage interface 140 is used to connect mass storage devices 142 to the node 102. One specific type of data storage device is a computer readable medium such as a Compact Disc (CD) drive, which may be used to store data to and read data from a CD 144 or Digital Versatile Disc (DVD). Another type of data storage device is a hard disk configured to support, for example, Journaled File System (JFS) type file system operations. In some embodiments, the various processing nodes 102 and 104 are able to be part of a processing cluster. The present invention is not limited to an SMP environment. Other architectures are applicable as well, and further embodiments of the present invention can also operate within a single system.
According to one embodiment,
The L1 Icache 206 provides loading of instruction streams in conjunction with an instruction fetch unit IFU 210, which prefetches instructions and may include speculative loading and branch prediction capabilities. These fetched instruction codes are decoded by an instruction decode unit (IDU) 212 into instruction processing data. Once decoded, the instructions are dispatched to an instruction sequencer unit (ISU) 214 and saved in the Issue Queue (IQ) 215. The ISU 214 controls sequencing of instructions issued to various execution units such as one or more fixed point units (FXU) 216 for executing general operations and one or more floating point units (FPU) 218 for executing floating point operations. The floating point unit(s) 218 can be a binary point floating unit 220, a decimal point floating unit 221, and/or the like. It should be noted that the FXU(s) 216, in one embodiment, comprises multiple FXU pipelines, which are copies of each other. The ISU 214 is also coupled to one or more load/store units (LSU) 230 via multiple LSU pipelines. These multiple LSU pipelines are treated as execution units for performing loads and stores and address generation for branches. Instruction stay in the issue queue waiting to be issued to the execution units depending on their age and on their dependencies. For example, instruction in the IQ are examined to determine their dependencies and to see whether they can be issued. Upon determining which instructions or Uops are ready for issue, the hardware selects the oldest instructions (Uops) among these instructions and then issues the selected instruction to execution units. The issue bandwidth depends on the number of execution available in the design.
A set of global completion tables (GCT) 222 residing within the ISU 214 track the instructions issued by ISU 214 via tags until the particular execution unit targeted by the instruction indicates the instructions have completed execution. The FXU 216 and FPU 218 are coupled to various resources such as general-purpose registers (GPR) 224 and floating point registers (FPR) 226. The GPR 224 and FPR 226 provide data value storage for data values loaded and stored from the L1 Dcache 204 by a load store unit (LSU) 230.
In one embodiment, the IDU 212 comprises a cracking unit 244. The cracking unit 244 organizes/breaks a complex instruction into simpler units. Stated differently, the cracking unit 244 organizes an instruction into a set of units of operation (Uops) that can be handled in parallel paths. The cracking unit 244 is discussed in greater detail below. In one embodiment, the IDU 212 also comprises an instruction shortening unit 248 that alters the execution of the instruction by, for example, reducing execution steps and/or execution pipes. The shortened instruction occupies less issue queue and GCT resources and improves the issue queue bandwidth. The instruction shortening unit 248 is discussed in greater detail below
Instruction Cracking and Shortening
As discussed above, a computer system typically comprises an instruction fetch part/unit, instruction decode unit instruction grouping and dispatching unit, instruction sequencing and issuing unit, execution units (Fixed Point, Load Store, Binary Floating Point Unit (BFU), Decimal Floating Point Unit, etc.) and instruction complete unit. Instruction decode refers to instructions being first decoded and understood. Information about the instruction's grouping, cracking, instruction characteristics such as load, store, and the like are decoded. At instruction dispatch (last in order point), information such as logical register number and type (GPR, FPR, AR, etc.), Condition Code read/write, Floating Point Control (FPC) read/write, Program Status Word (PSW) read/write, and the like is provided to the ISU.
The ISU maps the logical registers (e.g. GPR's and FPR's) specified by the instruction to physical copies that are used by execution units; sets dependency vectors among various instructions and cracked components (Uops) of instructions; and stores the dispatched instruction in an instruction queue. Instructions (or Uops) ready for issue are read from the instruction queue, ranked per execution unit and age, and then issued to execution units. For example, if two instructions are ready to issue to an FXU pipe0, only the oldest instruction is issued since each execution unit can only receive a single instruction.
Therefore, in addition to the general processing mechanisms discussed above with respect to
In one embodiment, the IFU 210 fetches an instruction from the Icache 206 and sends the instruction into the pipeline for decoding by the IDU 212. The IDU 212 decodes the instruction and identifies the instruction type such as, but not limited to, an RR-type branch instruction (e.g., Branch on Count Register (BCTR), Branch on Count Grande Register (BCTGR), Branch on Condition Register (BCR), and Branch and Save Register (BASR), and Branch and Link Register (BALR)); Load Address (LA)); Load Address Yonder (LAY), Load Address Extended (LAE) LAE, and Load Address Extended Yonder (LAEY) type instructions; shift/rotate type instructions (e.g., Rotate Left single Logical (RLL) and Rotate Left single Logical Grande (RLLG)); and Load and Test Register (LTR) and Load and Test Grande Register (LTGR) type instructions. The instruction analyzer 246 in the IDU 212 analyzes the identified instruction to determine the base field, index field, R1 and R2 operand field values as well as various other selected instruction text bits. The instruction cracking and shortening units 244, 248 based on these identified values, crack and/or shorten the instructions, as is discussed in greater detail below.
BCTR and BCTGR instructions are branch on count instructions. These instructions decrements one from operand R1 (GPR(R1)) and write the result back in GPR(R1). If the result of the decrement is not zero (i.e. GPR(R1)−1!=0) then the instruction branches to the address specified in operand R2 (contents of GPR(R2)). These instructions can also be used with the R2 field=0. This results in the instruction no longer being a branch instruction, it is more similar to a subtract instruction that does not change the condition code. Therefore, the instruction analyzer 246, in one embodiment, analyzes the R2 field at decode time to determine if the R2 field is 0. Instruction cracking/shortening is then performed based on this determination.
Uop 1 performs a GPR(R1)−1 operation and places the result back into GPR(R1). This operation decrements the contents of the GPR for R1 by 1 and sets it to a scratch CC (condition code). The scratch CC is read by Uop2 to determine if R1−1=0. Uop2 reads the branch target address from GPR(R2). Uop2 then determines, based on the value in the scratch CC, whether GPR(R1)−1=0. If GPR(R1)−1 does not equal to zero, then the branch to the target address is taken, otherwise the branch is not taken.
The following cases can occur with a BCR instruction: R2=0 or M1=0; R2!=0 and M1=F; and R2 !=0 and M1=1-E. With R2=0 or with M1=0, no operation is necessary. The issue queue does not need to be occupied. With R2 !=0 and M1=F, the instruction becomes an unconditional branch to a new instruction target. As a result, the BCR is not a condition code dependent operation. With R2!=0 and M1=1-E, a conditional branch is taken and this operation is condition code dependent.
In one embodiment, the instruction analyzer 246 analyzes the R2 and M1 fields of a BCR instruction. Based on the values of the R2 and M1 fields, the instruction shortening unit 248 shortens the BCR instruction.
If the instruction analyzer 246 determines that R2!=0 and M1=F then the operations shown in
If the instruction analyzer 246 determines that R2!=0 and M1 is between 1 and E (1110) then the operations shown in
In the above, example, the instruction can be shortened in two ways. For the case of R2=0 or M1=0, the instruction is not issued so an issue queue entry is saved and issue bandwidth is improved for not issuing the instruction. The second example of instruction shortening is for the case when R2!=0 and M1=F. In this case, the instruction is made not to be dependent on the CC, thus, allowing the instruction to have a chance to be issued earlier than the case when it is CC dependent. Issue bandwidth is improved by having more instructions issued in one cycle to the execution units. Instructions that are dependent on each other cannot be generally issued together since the result from one instruction is required for the execution of the other. By removing CC dependency, the BCR can then be issued with other CC updating instructions.
These instructions branch to a new target and save the current updated instruction address (IA) in the GPR of R1. If the R2=0 then these instructions no longer branch. However the instructions still perform the updated IA saving operation in the GPR of R1. In other words, the BASR and BALR instructions have two operands R1 and R2. These instructions save the current IA into R1. R2 includes the target of the branch. If R2=0 then there is not a branch. However, software uses this R2=0 scenario to save the instruction IA of the instruction following branch in a particular GPR.
Conventionally, the BASR and BALR instructions are normally cracked into 3 Uops. One of these Uops is used for the branching and the other two Uops are used for the IA saving operation. One or more embodiment of the present invention, on the other hand, utilizes the instruction analyzer 246 to determine when R2=0. As discussed above, when R2=0 these instructions are no longer branch instructions. Therefore, the cracking and instruction shortening units 244, 248 crack and shorten the instruction, respectively. For example, the instructions are only cracked into 2 Uops (as compared to 3 Uops) with the branching Uop removed, as shown in
It should be noted that the discussion above with respect to BASR and BALR instructions also applies to instructions such as Brand and Set Mode (BAS) and Branch and Save And Set Mode (BASSM) instructions. BSM/BASSM instructions also save the existing addressing mode and branch to a new addressing modes. Addressing modes is 2 bits in PSW (Program Status word) that specifies the addressing modes used for instruction fetching, operand accesses (loads or stores) and other address related function. Address mode can be either 24-bit, 31-bits and 64-bits addressing modes. If R2=0, then these ops no longer branch nor set addressing mode. Therefore instruction decoded shorten the instruction by removing the Uop(s) that performs the branches and setting the address modes.
Another type of instruction is a load address instruction.
As can be seen from
As can be seen from
These instructions add GPR(B2)+GPR(X2)+D2 and place the result back into GPR(R1). This operation is a 3-way add. An FXU can generally only perform a two way add. Therefore, conventional methods crack these instruction into 2 Uops. A first Uop1 performs the addition of B2+X2 and second Uop does the addition of D2. If X2=0 or if B2=0 then the contents of GR are not added, a 0 is added instead. If B2=0 then X2 and D2 are added. If B2=0 and X2=0 then D2 is stored in the GR.
In many performance critical cases sometimes either B2=0 or X2=0. In these situations, a 3-way is not required, but only a 2-way add is required. By having a 2-way add an LA or LAY instruction does not have to be cracked and can be issued or dispatched as a single operation. For example, the instruction analyzer 246 analyzes the instruction and determines that B2=0 or X2=0. Therefore, as shown in
When the instruction analyzer 246 analyzes an LA/LAY or an LAE/LAEY instruction and determines that B2 and X2 !=0 then the LA/LAY or LAE/LAEY instruction needs to perform a 3-way add operation. Therefore, the cracking unit 244 cracks the LA/LAY instruction into 2 Uops and cracks an LAE/LAEY instruction into 3 Uops, as shown in
Another type of instruction is a shift/rotate instruction such as RLL and RLLG instruction.
To begin, the instruction types such as shift, rotate and executed do not use the base field and do not use an operand to access cache memory. More specifically, Shift and rotate instructions have the shift amount specified in the lowest 6 bits of the addition of Base register and displacement fields (GPR(B2)+D2). In previous in-order implementations, the execution cycle (FXU shift/rotate) was after the AGEN (address generation) cycle and cache return. AGEN cycle is the cycle to calculate the address of the operands (Base+Index+displacement). In an out-of-order design where the execution unit is in parallel with AGEN cycle, the instruction is dual issued, where the first issue does the AGEN calculation and forms the rotate amounts and other controls needed to do the shift/rotate. The second issue, which is dependent on the results of the first issue, does the actual shift.
In one embodiment, the instruction analyzer 246 analyzes the B2 field during decoding to determine if B2=0 or another value. Depending on this value the instruction is either single issued or dual issued. For example, if B2!=0 the rotate/shift instruction is dual issued. In dual issued, the instruction is not cracked and it only occupies one entry in the issue queue. The first issue is an LSU issue. The LSU 230 performs the AGEN operation (GPR(B2)+D2). The lowest 6 bits of the AGEN result is used as the shift/rotate amount. The second issue is an FXU issue that is dependent on the LSU issue.
If B2=0, the contents of GPR-B2 is not used in the AGEN calculation and zeros are used instead. The rotate/shift amount can then be determined from the least significant bits of the displacement (instruction text bits 26:31). As a result, the instructions are single issued to the FXU 216 and the LSU issue is removed.
This above examples apply to all instructions that require AGEN functions. The AGEN issue can be bypassed when Base and Index fields are zeros for RX (Register-and-Indexed-Storage) type formats or when Base field is zero for RS (Register-and-Storage) formats. Example test data class ops are TCEB, TCDB, TCXB, TDCET, TDCDT, TDCXT, and the like. The dual vs. single issue is applied to all address generation usages when cache is not accessed. Examples are test data class BFU/DFU ops such as TCEB, SLDT, and the like.
Another instruction type is the Execute instructions (EX/EXRL).
The EX instruction as shown in
The instruction analyzer 246 analyzes the R1 field at decode time to determine if R1=0. If R1=0 the EX/EXRL instructions are not cracked and are dispatched as a single Uop, as shown in
If the instruction analyzer 246 determines that R1!=0 then the EX/EXRL instruction is cracked into 2 Uops, as shown in
Another type of instruction is a load and test instruction such as LTR and LTGR.
The instruction analyzer 246, in one embodiment, compares the R1 and R2 operands of an LTR/LTGR. Based on this comparison, the instruction shortening unit 248 shortens the instruction by removing the load component from the instruction. For example, when the instruction analyzer 246 determines that R1=R2 (i.e., the instruction is similar to a test instruction) the Uop only sets the CC based on the contents of R2, as shown in
Operational Flow Diagram
The IDU 214, via the instruction analyzer 246, at step 2910, also analyzes one or more of the instruction base field, index field, operands, and other instruction fields such as, but not limited to a mask field. These fields and their analysis have been discussed above in greater detail with respect to
Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Although various example embodiments of the present invention have been discussed in the context of a fully functional computer system, those of ordinary skill in the art will appreciate that various embodiments are capable of being distributed as a program product via CD or DVD, e.g. CD, CD ROM, or other form of recordable media, or via any type of electronic transmission mechanism.
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|9. Apr. 2010||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BUSABA, FADI;CURRAN, BRIAN;EISEN, LEE;AND OTHERS;REEL/FRAME:024210/0777
Effective date: 20100408
|15. Okt. 2016||FPAY||Fee payment|
Year of fee payment: 4