US8713235B2 - Low latency interrupt collector - Google Patents
Low latency interrupt collector Download PDFInfo
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- US8713235B2 US8713235B2 US13/098,898 US201113098898A US8713235B2 US 8713235 B2 US8713235 B2 US 8713235B2 US 201113098898 A US201113098898 A US 201113098898A US 8713235 B2 US8713235 B2 US 8713235B2
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 90
- 230000004044 response Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000004891 communication Methods 0.000 claims description 19
- 230000002457 bidirectional effect Effects 0.000 claims description 15
- 230000007704 transition Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Definitions
- Such devices often include a main processor and one or more other peripheral devices, such as sensors or transducers, that assist in providing the communication, or entertainment, or utility functions.
- peripheral devices often require the use of one or more general purpose inputs and/or outputs (I/O) of the main processor to communicate information about peripheral device status, such as, in the case of a sensor, the sensed information.
- I/O general purpose inputs and/or outputs
- the cost and/or ability of a mobile electronic device to provide certain communication, entertainment, or utility functions can be driven by the availability of general purpose I/O on the main processor.
- interrupts can be handled without using any processor general purpose I/O.
- Such an example can use a communication bus to poll the peripheral devices and service a peripheral device if an interrupt type condition exists. Although this type of system would reduce the number of general purpose I/O dedicated to receiving interrupts of the peripheral devices, interrupt latency, the time interval between the onset of the interrupt condition and the processor servicing the condition, can be unpredictable or unacceptable. Interrupt latency in such an example can depend on the speed of the communication bus and the number of peripheral devices polled. If such latency is too long, applications that depend on timely information from the peripheral devices may not be practical or provide useful utility.
- processor general purpose I/O can provide very low latency intervals.
- availability of such general purpose I/O can limit the number of available peripheral devices provided or can drive the cost of a highly equipped system higher than the market can bear.
- apparatus and methods disclosed herein can provide low latency response from a processor to a number of peripheral device interrupts. Certain examples can reduce the quantity of processor general purpose inputs and outputs configured to receive the peripheral device interrupts in comparison to systems where the peripheral device interrupts can be directly coupled to the processor.
- FIG. 1 illustrates generally an example system for reducing the number of processor general purpose I/O employed to service a plurality of peripheral devices.
- FIG. 2 illustrates generally an example low latency interrupt collector.
- FIG. 3 illustrates generally an example method for operating a low latency interrupt collector to reduce the use of processor general purpose I/O for receiving peripheral device interrupts.
- Electronic devices can be configured to run an ever expanding variety of applications. Certain applications depend on the electronic device having one or more particular peripheral devices, such as sensors, displays, transducers, etc.
- the peripheral devices can interrupt the operation of the electronic device processor to provide information to the processor.
- each peripheral device can exchange information with the electronic device processor using one or more general purpose I/Os of the electronic device processor.
- Such an interface can usually have a low latency interval between the time a peripheral device can provide or request new information and the time the processor is ready to accept or provide the new information.
- availability of such general purpose I/O can limit the number of available peripheral devices provided with a system or can drive the cost of a highly equipped system higher than the market can bear.
- the present inventor has recognized, among other things, that adding peripheral devices to interface with a device processor can limit the performance of the device, can add cost to the device, or can be difficult or prohibitive if additional general purpose inputs and/or outputs are not available on the processor.
- these issues can be solved using low latency interrupt collectors that can allow one or more additional peripheral devices to interface with a device processor without consuming additional general purpose I/O and without significantly increasing latency of the processor in response to an interrupt received from a peripheral device.
- the present inventor has also recognized, among other things, that the ability or cost to provide communication, including wireless communications, entertainment, or utility functions using an electronic device, can be related to many factors including the number of general purpose I/O available on a processor of the electronic device and the latency associated with servicing the peripheral devices used with the processor.
- peripheral devices can include, but are not limited to, multi- and single axis accelerometers, an electronic compass, a gyroscope, an ambient light sensor, a proximity sensor, a touchscreen, acoustic transducers, global positioning sensing devices, etc.
- This document provides apparatus and methods to collect interrupt requests from two or more peripheral devices, to interrupt an associated device processor, and to provide the processor with enough information to quickly service each interrupt.
- the apparatus and methods disclosed herein can accomplish the above functions using about the same amount of general purpose I/O employed for a single peripheral device directly coupled to an electronic device processor.
- FIG. 1 illustrates generally an example of a system 100 for reducing the number of processor general purpose I/Os employed to service a plurality of peripheral devices.
- the system 100 can include a processor 101 , a low latency interrupt collector (LLIC) 102 , and a number of peripheral devices 103 .
- the processor 101 can include a microprocessor, a micro controller, a processor for a portable electronic device (such as a portable media player, a personal digital assistant, or a baseband processor for a cell phone), or one or more other processors.
- the LLIC 102 can receive interrupt requests from the plurality of peripheral devices 103 and communicate interrupt information to the processor 101 using only a few general purpose I/O.
- the interrupt information can include a value corresponding to the identity of the requesting peripheral.
- the interrupt request information from a plurality of the peripheral devices 103 can be exchanged between the LLIC 102 and the processor 101 using two general purpose inputs and one general purpose output of the processor 101 .
- the interrupt request information from a plurality of the peripheral devices 103 can be exchanged between the LLIC 102 and the processor 101 using one bi-direction general purpose I/O (GP J ) and one general purpose input (GP J+1 ), of the processor 101 .
- the processor 101 can exchange information with each peripheral device, such as when a particular device provides an interrupt request, using a communication bus architecture 104 coupled between the processor 101 and each of the peripheral devices 103 .
- Examples of the communication bus architecture 104 can include, but are not limited to, inter-integrated circuit (I 2 C) bus architecture and system management bus (SMB) architecture.
- FIG. 2 illustrates generally an example of a low latency interrupt collector (LLIC) 202 .
- the LLIC 202 can be used to reduce the number of general purpose I/O employed to interface a plurality of peripheral devices to a processor, such as a baseband processor of a cell phone, for example.
- the LLIC 202 can include a number of interrupt request inputs (INT 0 , INT 1 , . . . , INT N ), logic 205 , inputs and outputs, ALM/CLK, INT 0-N , a parallel-to-serial converter 206 , and a counter 207 .
- the LLIC 202 can include a number of inputs (INT 0 , INT 1 , . . . , INT N ) configured to receive interrupt request signals from a number of peripheral devices.
- the peripheral devices can include, but are not limited to, multi- and single axis accelerometers, an electronic compass, a gyroscope, an ambient light sensor, a proximity sensor, a touchscreen, acoustic transducers, global position sensing devices, etc.
- Applications configured to run on electronic devices, such as cell phones, personal media players, personal digital assistants, or one or more other electronic devices can use peripheral devices to interact with a user, to control the execution of the application, or to provide information or feedback to the application.
- a peripheral device can issue an interrupt request when the status of the peripheral device has changed to a certain degree, or after a period of time.
- the interrupt can be used to signal a processor to exchange information with the peripheral device.
- issuing an interrupt can save processing power because the processor need only exchange information with the peripheral device when the peripheral device can provide or can receive new information, thus, the processor is not burdened with communicating with the peripheral device when peripheral information has not changed.
- the logic 205 can detect one or more changes in the status of the interrupt request inputs (INT 0 , INT 1 , . . . , INT N ). In an example, the logic 205 can provide an output 208 indicative of a change in received interrupt requests. In some examples, the output 208 indicates one or more interrupt requests transitioning from an inactive state to an active state. In an example, where an interrupt request transitions from a low logic level when inactive to a high logic level when active, the logic can include an “or” gate 209 coupled to the plurality of inputs. It is understood that other logic circuits are possible to indicate one or more interrupt requests transitioning from an inactive state to an active state without departing from the scope of the present subject matter.
- the logic 205 can include a latch 210 configured to hold an output indicative of a momentary state of the “or” gate, for example, until interrupt information can be passed to the processor.
- the latch 210 can hold the output 208 at an active level until the interrupt information is passed to the processor.
- the output 208 can be coupled to an input of the processor to indicate to the processor when one or more interrupt requests from the plurality of peripheral devices are active.
- the serial-to-parallel converter 206 can receive a request for interrupt information from the processor at an input (CLK) and provide the interrupt information at an output (OUT).
- the processor upon receiving an indication that an interrupt is active, can provide a series of clock signals to the serial-to-parallel converter 206 .
- the parallel-to-serial converter 206 can shift and provide at the output (OUT), in sequence, a bit indicative of the status of one of the plurality of interrupt requests.
- the parallel-to-serial converter 206 can shift and sequentially output the status of each of the N interrupt request inputs (INT 0 , INT 1 , . . . , INT N ) to an output (INT 0-N ) of the LLIC 202 coupled to a general purpose input of the processor.
- the processor can identify which peripheral devices have active interrupts and can then service the interrupts using, for example, a communication bus coupled to the peripheral devices.
- an interrupt request can be received as a pulse.
- the parallel-to-serial converter 206 can be configured such that each pulse interrupt is latched within the parallel-to-serial converter 206 .
- the parallel-to-serial converter 206 can receive reset information at an input (CLR) and can reset a register to capture each subsequent interrupt request pulse from the peripheral devices.
- CLR reset information at an input
- the logic level captured by the LLIC 202 as an active interrupt request can be programmable.
- the LLIC 202 can include a counter 207 .
- the counter 207 can receive the interrupt information request clock signal at an input (CLK). Upon receiving, for example, N clock signals, the counter 207 can provide reset information at an output (DONE) coupled to at least one of the parallel-to-serial converter 206 or the latch 210 , so as each can capture subsequent interrupt requests from the peripheral devices.
- the LLIC 202 can include an ALM/CLK bidirectional port 211 configured to provide an indication, or interrupt alarm (ALM), related to the status of the plurality of interrupt requests to the processor, and to receive the interrupt information request from the processor, such as a clock signal (CLK).
- ALM interrupt alarm
- CLK clock signal
- the output 208 can be allowed to float and thus be pulled to a high logic level, (e.g., Vcc such as by a pull-up resistor 212 ) indicating that there are no active interrupt requests.
- the latch 210 can pull the latch output (OUT) low (e.g., weakly).
- the low logic level at the ALM/CLK bi-direction port 211 can indicate to the processor that a peripheral device is ready to communicate.
- the processor can control (e.g., strongly) the logic level of the ALM/CLK bi-directional port 211 to provide an interrupt information request to the LLIC 202 , such as in the form of clock signals, for example.
- the counter 207 can provide reset information to the latch 210 and the ALM/CLK bi-direction port 211 can be pulled to a high logic level until a subsequent active interrupt request is received.
- the output 208 can be pulled to a low logic level using the latch 210 , indicating that there are no active interrupt requests.
- the latch 210 can let the latch output (OUT) float.
- the ALM/CLK bi-direction port 211 of the LLIC 202 can be pulled high using a pull-up resistor 212 coupled to the output 208 .
- the high logic level at the ALM/CLK bi-direction port 211 can indicate to the processor that a peripheral device is ready to communicate with the processor.
- the processor can control the logic level of the ALM/CLK bi-directional port 211 to provide an interrupt information request to the LLIC 202 , such as in the form of clock signals, for example.
- the counter 207 can provide reset information to the latch 210 and the ALM/CLK bi-direction port 211 can be pulled low until a subsequent active interrupt request is received.
- an LLIC 202 can be configured to receive up to eight interrupt requests from up to eight peripheral devices.
- the LLIC 202 can sequentially communicate eight bits to provide the interrupt information to the processor.
- the counter 207 can reset the parallel-to-serial converter 206 and the latch 210 .
- the LLIC 202 can be configured to receive other numbers of interrupt requests from other numbers of peripheral devices (e.g., more than eight).
- the LLIC 202 can include a level shift circuit 213 that can also be referred to as a translator circuit.
- the level shift circuit 213 can translate one or more interrupt request logic levels to the logic level of the LLIC 202 .
- the level shift circuit 213 can include one or more voltage inputs (V C0 , V C1 , V C2 , . . . , V CN ). Each voltage input (V C0 , V C1 , V C2 , . . . , V CN ) can be associated with one or more of the interrupt request inputs (INT 0 , INT 1 , . . . , INT N ).
- an interrupt request signal of a first peripheral device can be received at INT 1 and a voltage indicative of a high interrupt logic level of the first peripheral device can be received at V C1 .
- the level shift circuit 213 can translate the high logic level of the received interrupt request to the high logic level of the logic 205 or the parallel-to-serial shift register 206 .
- an interrupt request of a second peripheral device can be received at INT 2 and a voltage indicative of a high logic level of the second peripheral device can be received at V C2 .
- the level shift circuit 213 can translate the high logic levels of each of the received interrupt requests to the high logic level of the logic 205 or the parallel-to-serial shift register 206 , even if the high logic level of the first peripheral device is different than the high logic level of the second peripheral device.
- each interrupt request input (INT 0 , INT 1 , . . . , INT N ) can be associated with a level shift circuit voltage input (V C0 , V C1 , V C2 , . . . , V CN ).
- more than one interrupt request input (INT 0 , INT 1 , . . . , INT N ) can be associated to a particular level shift circuit voltage input (V C0 , V C1 , V C2 , . . . , V CN ).
- FIG. 3 illustrates generally an example of a method 300 for operating a low latency interrupt collector to reduce the use of processor general purpose I/O for receiving peripheral device interrupts.
- one or more interrupt requests from a plurality of interrupt request inputs of a low latency interrupt collector can be received.
- more than one interrupts can be received simultaneously at the interrupt request inputs.
- the interrupt request inputs can be coupled to one or more peripheral devices.
- a latch can latch an interrupt alarm output in response to one or more interrupt requests.
- the interrupt alarm is coupled to an input of a processor, such as a baseband processor.
- the low latency interrupt collector can receive a request to provide interrupt information.
- the interrupt information request can come from a processor, such as the processor receiving the interrupt alarm.
- the interrupt information request can be received on a bi-direction port configured to also provide the interrupt alarm to the processor.
- the low latency interrupt collector can provide interrupt information in response to the interrupt information request.
- providing the interrupt information can include converting a status of the plurality of interrupt request inputs to a serial output of interrupt information using a parallel-to-serial converter.
- the interrupt information can be used to identify one or more peripheral devices with active interrupt requests.
- receiving the interrupt information request can include receiving clock signals from the processor.
- providing the interrupt information can include counting the clock signals using a counter.
- the counter can provide reset information after receiving a predetermined threshold number of count signals.
- the predetermined threshold number of count signals can correspond to number of interrupt request inputs in the plurality of interrupt request inputs.
- the latch and parallel-to-serial converter can be reset, for example, using reset information received from the counter.
- a processor receiving the interrupt information can use the information to identify peripheral devices having an active interrupt.
- the processor can communicate with one or more of the peripheral devices over a communication bus to service the active interrupt requests.
- servicing an interrupt request can include exchanging information with a peripheral device, such as, but not limited to, receiving sensor information from the peripheral device, setting parameters of the peripheral device, or receiving sensor information from the peripheral device and setting parameters of the peripheral device.
- a system can include a mobile device processor, a plurality of peripheral devices, a plurality of inputs configured to simultaneously receive a plurality of interrupt requests from the plurality of peripheral devices, and control logic configured to provide an indication of at least one interrupt request received at the plurality of inputs to the mobile device processor and to provide interrupt information to the mobile device processor in response to a request from the mobile device processor.
- the system can be configured to reduce an overall number of general purpose inputs and outputs of a mobile device processor configured to receive peripheral device interrupts.
- the system of Example 1 optionally include a communication bus configured to provide communication between the mobile device processor and the plurality of peripheral devices.
- Example 3 the mobile device processor of any one or more of Examples 1-2 optionally includes a baseband processor for a wireless communication device.
- Example 4 the plurality of peripheral devices any one or more of Examples 1-3 optionally includes at least one of an accelerometer, an electronic compass, a gyroscope, an ambient light sensor, a proximity sensor, or a touchscreen.
- Example 5 the system of any one or more of Examples 1-4 optionally includes a bidirectional port configured to output the indication of the interrupt request.
- Example 6 the bidirectional port of any one or more of Examples 1-5 is optionally configured to receive the request from the mobile device processor, and the control logic is optionally configured to provide a value of the at least one interrupt request to the mobile device processor using an output.
- an apparatus can include a plurality of inputs configured to simultaneously receive a plurality of interrupt requests, and control logic configured to provide an indication of at least one interrupt request received at the plurality of inputs to a mobile device processor and to provide interrupt information to the mobile device processor in response to a request from the mobile device processor.
- Example 8 the apparatus of claim 7 optionally includes a bidirectional port configured to output the indication of the interrupt request.
- Example 9 the bidirectional port of any one or more of Examples 1-8 is optionally configured to receive the request from the mobile device processor, and the control logic is optionally configured to provide a value of the at least one interrupt request to the mobile device processor using an output.
- Example 10 the request from the mobile device processor of any one or more of Examples 1-9 optionally includes a clock signal, and the apparatus any one or more of Examples 1-9 optionally includes a converter configured to receive the clock signal and to sequentially shift the value of the at least one interrupt request to the mobile device processor using the output.
- Example 11 the apparatus of any one or more of Examples 1-10 optionally includes a counter configured to receive the clock signal, to increment in response to the clock signal, and to provide reset information to the converter after the counter reaches a predetermined threshold.
- control logic of any one or more of Examples 1-11 optionally includes an OR gate configured to receive the plurality of interrupt request.
- control logic of any one or more of Examples 1-12 is optionally configured to provide the indication of the at least one interrupt request to the mobile device processor using a bit signal, and the control logic of any one or more of Examples 1-12 optionally includes a latch configured to latch a state of the bit signal.
- a method can include simultaneously receiving a plurality of interrupt requests, providing an indication of at least one interrupt request of the received plurality of interrupt requests to a mobile device processor, receiving an interrupt information request from the mobile device processor, providing the interrupt information to the mobile device processor in response to the interrupt information request; receiving a clock signal at the bidirectional port in response to the bit signal, and sequentially shifting a value of an interrupt request of the plurality of interrupt request to a output in response to the received clock signal using a converter.
- Example 15 the providing the indication of any one or more of Examples 1-14 optionally includes outputting the indication of the at least one interrupt request at a bidirectional port.
- Example 16 the receiving the interrupt information request of any one or more of Examples 1-15 optionally includes receiving the interrupt information request from the mobile device processor at the bidirectional port.
- Example 17 the receiving the interrupt information request of any one or more of Examples 1-16 optionally includes receiving a clock signal from the mobile device processor at the bidirectional port.
- Example 18 the receiving the interrupt information request of any one or more of Examples 1-17 optionally includes receiving the clock signal at a parallel-to-serial converter, and the method of any one or more of Examples 1-17 optionally includes sequentially shifting a value representative of the at least one interrupt request to the mobile device processor using an output.
- Example 19 the receiving the interrupt information request of any one or more of Examples 1-18 optionally includes incrementing a counter using the clock signal, and providing reset information to the converter after the counter reaches a predetermined threshold.
- Example 20 the simultaneously receiving a plurality of interrupt requests of any one or more of Examples 1-19 optionally includes simultaneously receiving a plurality of interrupt requests from a plurality of peripheral devices, and the method of any one or more of Examples 1-19 optionally includes servicing a peripheral device corresponding to the at least one interrupt request using a serial communication bus coupled to at least a plurality of the plurality of peripheral devices.
- the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.”
- the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US13/098,898 US8713235B2 (en) | 2011-05-02 | 2011-05-02 | Low latency interrupt collector |
CN201210128679.3A CN102768648B (en) | 2011-05-02 | 2012-04-27 | Gatherer, the system with this gatherer and correlation technique are interrupted in low delay |
CN201220186575.3U CN202838316U (en) | 2011-05-02 | 2012-04-27 | System and device capable of reducing total quantity of input terminals and output terminals of mobile device processor |
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US13/098,898 US8713235B2 (en) | 2011-05-02 | 2011-05-02 | Low latency interrupt collector |
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US20120284442A1 US20120284442A1 (en) | 2012-11-08 |
US8713235B2 true US8713235B2 (en) | 2014-04-29 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102021104269A1 (en) | 2021-02-23 | 2022-08-25 | Infineon Technologies Ag | Controller, electronic component and electronic system |
DE102021104265A1 (en) | 2021-02-23 | 2022-08-25 | Infineon Technologies Ag | Controller, electronic component and electronic system |
Families Citing this family (6)
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CN104123179A (en) * | 2013-04-29 | 2014-10-29 | 敦南科技股份有限公司 | Method of interrupt control and electronic system using the same |
GB2521121A (en) * | 2013-11-07 | 2015-06-17 | St Microelectronics Res & Dev | A method and apparatus use with interrupts |
GB2537852B (en) | 2015-04-28 | 2019-07-17 | Advanced Risc Mach Ltd | Controlling transitions of devices between normal state and quiescent state |
GB2537855B (en) * | 2015-04-28 | 2018-10-24 | Advanced Risc Mach Ltd | Controlling transitions of devices between normal state and quiescent state |
DE102016212808A1 (en) * | 2016-07-13 | 2018-01-18 | Robert Bosch Gmbh | Interrupt request distributor and operating method therefor |
CN112711549B (en) * | 2021-01-15 | 2023-08-01 | 飞腾信息技术有限公司 | Interrupt request signal conversion system and method, and computing device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102021104269A1 (en) | 2021-02-23 | 2022-08-25 | Infineon Technologies Ag | Controller, electronic component and electronic system |
DE102021104265A1 (en) | 2021-02-23 | 2022-08-25 | Infineon Technologies Ag | Controller, electronic component and electronic system |
Also Published As
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CN102768648A (en) | 2012-11-07 |
CN202838316U (en) | 2013-03-27 |
CN102768648B (en) | 2015-11-18 |
US20120284442A1 (en) | 2012-11-08 |
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