US8895871B2 - Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller - Google Patents
Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller Download PDFInfo
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- US8895871B2 US8895871B2 US13/515,907 US201013515907A US8895871B2 US 8895871 B2 US8895871 B2 US 8895871B2 US 201013515907 A US201013515907 A US 201013515907A US 8895871 B2 US8895871 B2 US 8895871B2
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- circuit board
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- thermally conductive
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
Definitions
- the invention relates to a circuit board having a plurality of circuit board layers arranged one over the other.
- the usual structure for such integrated mechatronic controlling means consists of a ceramic substrate that includes the various electronic components of a central control unit.
- the ceramic substrate is connected to rigid or flexible circuit boards or pressed screens by means of bond connections (e.g., aluminum thick-wire bond connections).
- bond connections e.g., aluminum thick-wire bond connections.
- the entire electronic-component space with the populated circuit carrier is coated with a silicone gel in order to protect the bond connections, the strip conductors and the components from moisture and other environmental influences.
- an integrated mechatronic controlling means is used as a gearbox control module
- said module is accommodated in the gear oil pan so that it is completely surrounded by oil and electrically conductive contaminants contained in the oil.
- Said contaminants comprise contaminants that result from gear teeth abrasion, remnants of machining operations of manufacturing processes and/or from inadequate washing and cleaning processes of the gearbox casing and/or of the built-in components.
- a metallic, non-metallic or metallized casing cover is mounted onto a casing base plate of the gearbox control module and sealed hermetically.
- casingless semiconductor components are mainly used. Said components are mounted on the ceramic substrate (circuit carrier) using conductive adhesives and are electrically contacted towards the circuit carrier by gold and aluminum wire bonding.
- the ceramic circuit carriers are realized in the form of thick-film circuits or as LTCC (Low Temperature Cofired Ceramics). With both ceramic circuit carrier technologies, strip conductors are produced by screen printing using highly argentiferous pastes.
- multifunctional end surfaces can be realized on the strip conductors of the circuit carrier in subsequent plating processes by means of a sequence of films (e.g., nickel, palladium and gold). At the same time, said end surfaces are suitable for connecting techniques, such as soldering, gold or aluminum wire bonding, and using conductive silver adhesives.
- These two ceramic circuit carrier technologies are suitable for high operating temperatures in or on the gearbox.
- the ceramic circuit carriers are adhesively bonded on metallic base plates or casing parts by means of a thermally conductive adhesive.
- Chip-on-board Mounting the casingless semiconductor components on the circuit board by means of conductive silver adhesives and wire bonding is also referred to as chip-on-board (COB).
- COB chip-on-board
- the glob top material is a polymeric resin, typically an epoxy resin with fillers such as silicon oxide.
- the thermal expansion of the glob top material is adapted to the thermal expansion of the circuit board, wherein the glob top material has a high modulus of elasticity.
- Chip-on-board applications are designed for moderate reliability requirements and temperature requirements (e.g., between ⁇ 40° C. and 85° C.), whereas the typical operating-temperature range of gearbox controllers extends from ⁇ 40° C. to +160° C. and higher temperatures. No applications are known for such operating-temperature ranges.
- thermal vias The fact that heat is removed from the components by means of thermal vias is also known from the state of the art.
- the components casingless semiconductor components
- the components are conductively mounted, together with passive components, onto the surface of the circuit board by means of adhesive bonding or soldering.
- the component is electrically contacted to the circuit carrier by means of wire bonding.
- a standard circuit board technique multilayer technique uses thermal vias for facilitating the heat dissipation of the components, in particular of active components, said thermal vias being drilled mechanically.
- Thermal vias are used both for components that are accommodated in casings and for casingless components, wherein heat flows to the bottom of the circuit board via the thermal vias.
- a copper pad arranged on the bottom of the circuit board transfers the heat to a heat sink via the thermally conductive adhesive.
- DE 10 2007 032 535 A1 describes an electronic module having a casing cover and at least one multilayer circuit board as an electrical connection between the interior of the casing and components that are arranged outside the casing.
- the multilayer circuit board is a circuit carrier for electronic components of a central electronic control system. At the same time, it is a thermal connection to a base plate for an integrated mechatronic gearbox controller.
- the circuit board has vias for providing a thermal connection to the base plate and for providing an electronic connection to the components that are arranged outside the casing.
- An object of an embodiment of the invention is to provide a circuit board having a plurality of circuit board layers arranged one over the other, said circuit board being improved as compared to the state of the art, having improved functional properties, and being at the same time manufacturable with little effort and in an economical manner.
- the circuit board of an embodiment of the invention should meet high-temperature, chemical-stress and mechanical-stress requirements (in particular, as far as vehicle applications are concerned) better than the solutions that are known from the state of the art.
- another object of an embodiment of the invention is to provide a control unit for vehicle applications and a use of the control unit, said control unit being improved as compared to the state of the art.
- a circuit board comprises a plurality of circuit board layers arranged one over the other.
- the circuit board layers are each made of a base material, the glass transition temperature of which is greater than or equal to 170° C., and the circuit board layers each have at least one thermally conductive layer applied to the electrically insulating base material, wherein several vias extending in a z-direction perpendicularly to the circuit board layers are provided, which vias connect the thermally conductive layers of different circuit board layers in such a way that the vias and the thermally conductive layers of the circuit board layers form a thermally conductive bridge from a topmost circuit board layer to a bottommost circuit board layer, wherein the thermally conductive layers serve as electrical conductors at the same time.
- HDI High Density Interconnect
- a via (Vertical Interconnect Access) is a vertical plated hole that connects at least two circuit board layers of a multilayer circuit board to each other.
- Microvias are vias in the form of plated holes having a diameter of less than approximately 150 ⁇ m.
- a blind via is a via in the form of a plated blind hole that connects the topmost or the bottommost circuit board layer to at least one internal circuit board layer of a multilayer circuit board.
- a buried via is a via that is arranged in the interior of a multilayer circuit board and connects at least two internal circuit board layers to each other.
- Thermal vias are vias that are primarily used to improve the transfer of heat through a circuit board.
- Thermal vias are particularly used to remove heat from circuit boards on which heat-emitting active electrical components (e.g., casingless semiconductor components) are arranged.
- active electrical components e.g., casingless semiconductor components
- the vias act as thermal vias by means of which heat can be removed through the various circuit board layers
- the inventive realization of the circuit board advantageously results in the circuit board being designed for high operating temperatures and being suitable for integrated mechatronic applications.
- the base material is a glass-fiber reinforced plastic material that comprises ceramic particles. These base materials can be obtained easily and cost-effectively.
- Circuit carrier structures may be standardized in principle.
- larger circuit carrier geometries may be realized or very special shapes having roundings, corners and other features may be created.
- an overall or total surface area of all thermally conductive layers of at least one selected circuit board layer is larger than an overall or total surface area of all thermally conductive layers of a circuit board layer lying above the selected layer, wherein the thermally conductive bridge that is made up of the vias and the thermally conductive layers is widened or enlarged from at least one circuit board layer to an underlying circuit board layer since the overall surface area of all thermally conductive layers of at least one circuit board layer is larger than an overall surface area of all thermally conductive layers of a circuit board layer lying above it.
- the effective heat transfer area is increased advantageously and the thermal resistance of the circuit board is reduced since the thermal resistance is at least approximately proportional to the reciprocal value of the effective heat transfer area.
- circuit board provides that the size of the thermally-conductive-layer surfaces that extend perpendicularly to the z-direction increases monotonically from the topmost circuit board layer to the bottommost circuit board layer.
- a monotonic increase in the size of these surfaces means that in each case the size of the surfaces increases from one circuit board layer to a directly underlying circuit board layer or remains constant but does not decrease.
- some vias are first blind vias that connect at least one thermally conductive layer of the topmost circuit board layer to at least one thermally conductive layer of an underlying circuit board layer, thereby thermally contacting the topmost circuit board layer with an underlying circuit board layer in an advantageous manner.
- the first blind vias may be realized in the form of microvias, which is particularly advantageous for HDI circuit boards.
- some vias are preferably second blind vias that connect at least one thermally conductive layer of the bottommost circuit board layer to at least one thermally conductive layer of a circuit board layer lying above so that it is possible to conduct heat from the interior of the circuit board to the bottommost circuit board layer, via which the heat can be conducted to the outside.
- the second blind vias too may be realized in the form of microvias, which is again particularly advantageous for HDI circuit boards.
- some vias are preferably buried vias, each of them connecting thermally conductive layers of at least two different circuit board layers to each other, whereby it is possible to conduct the heat through the interior of the circuit board in an advantageous manner, wherein the arrangement, the size and the design of the buried vias of the circuit board geometry may be adapted.
- the first blind vias and/or the second blind vias and/or the buried vias are microvias so that as many vias as possible can be arranged in a small area.
- At least one via is formed as a sleeve-like via, i.e., as an enveloping hollow body.
- Forming vias as sleeve-like vias advantageously reduces the weight of the circuit board and reduces the amount of material required for manufacturing the circuit board and the corresponding material costs.
- HDI High Density Interconnect
- the thermally conductive layers of the circuit board layers and/or walls of the vias are made of copper. This results in the inventive circuit board being characterized by increased current-carrying capacity as against ceramic substrates that have electrical conductors imprinted in the form of pastes.
- the circuit board can be used for gearbox controllers.
- the circuit board is integrated in a control unit or device, wherein pumps or motors can be driven at increased currents ranging from 15 A to 50 A and higher on account of the high current-carrying capacity of the circuit board.
- the circuit boards have a particularly high current-carrying capacity since the thermally conductive layers and/or strip conductors are made of copper.
- the thermally conductive layers can be created particularly easily as copper layers having different layer thicknesses so that they can be adapted to the required use and to the required current-carrying capacity particularly easily, wherein copper layer thicknesses of 35 ⁇ m and 70 ⁇ m, but also greater copper layer thicknesses ranging from 200 ⁇ m to 400 ⁇ m, can be created and obtained, for example.
- the thermally conductive layers of the circuit board layers and/or the walls of the vias are advantageously plated with a multifunctional additional metallization layer having a sequence of films (e.g., nickel, palladium and gold) so that it is possible to populate the circuit board with casingless semiconductor components together with passive components (bare die population).
- a multifunctional additional metallization layer having a sequence of films (e.g., nickel, palladium and gold) so that it is possible to populate the circuit board with casingless semiconductor components together with passive components (bare die population).
- the outer copper surface of the thermally conductive layers and/or of the walls of the vias is plated with the additional metallization layer, wherein the additional metallization layer is at the same time suitable for mounting processes by means of soldering, adhesive bonding using conductive silver adhesives and connecting techniques, such as gold and/or aluminum wire bonding.
- High reliability ratings especially for the gold and/or aluminum wire bond connections, can be achieved by the described optimization of the manufacturing process of the circuit board and by the additional metallization of the outer layers of the circuit board.
- the circuit board may have at least one active electrical component arranged on the topmost circuit board layer and/or at least one passive electrical component arranged on the topmost circuit board layer, thereby enabling the thermally conductive bridge made up of the vias and the thermally conductive layers to be advantageously used to remove heat that is emitted by the at least one electrical component.
- a second thermally conductive adhesive layer is provided that firmly bonds the at least one active electrical component to the topmost circuit board layer so that the at least one active electrical component and/or passive electrical component is thermally conductively fixed to the topmost circuit board layer in a simple manner.
- the topmost circuit board layer preferably has a thermally conductive layer facing the at least one electrical component.
- the surface of said thermally conductive layer is larger than a surface of the at least one active electrical component facing it.
- the topmost circuit board layer has a thermally conductive layer adjacent to the at least one active electrical component, by means of which thermally conductive layer heat that is emitted by the at least one electrical component can be absorbed.
- this thermally conductive layer is larger than the surface of the at least one electrical component facing it, whereby heat that is emitted by the at least one electrical component is distributed over a larger surface area of this thermally conductive layer and the thermal capacity of the topmost circuit board layer is increased advantageously.
- a heat sink arranged under the bottommost circuit board layer and a first thermally conductive adhesive layer that firmly bonds the heat sink to the bottommost circuit board layer are provided.
- the thickness of the first thermally conductive adhesive layer must be as small as possible, in particular smaller than 100 ⁇ m. It is only possible to realize such layer thicknesses across the entire surface of the circuit board if the deflection of the circuit board is smaller than the thickness of the thermally conductive adhesive layer. This is achieved by specific layer construction and by layout optimization measures, such as evenly distributing the copper on all levels.
- the heat sink may be in the form of a heat conducting plate, e.g., a heat conducting plate made of aluminum.
- the heat sink is thermally conductively fixed to the bottommost circuit board layer in a simple manner.
- the circuit board is completely surrounded, on a side facing away from the heat sink, by a sealing material, and the at least one electrical component is arranged completely within the sealing material so that the entire circuit carrier is advantageously protected from external mechanical, thermal and chemical influences.
- the sealing material is a silicone gel and/or a silicone varnish so that a “soft seal” is formed.
- a soft seal is characterized by high thermal expansion and, at the same time, by a low modulus of elasticity. Therefore, it is suitable for the protection of the circuit carrier even at high temperatures.
- strip conductors preferably have a strip conductor width of at least 100 ⁇ m and/or dielectric layers have a layer thickness of at least 50 ⁇ m in order to achieve particularly good electrical, thermal and mechanical properties of the circuit carrier.
- reliability and lifetime requirements of the circuit board can be met by a specific adjustment of the basic circuit board layer structure, of the dimensioning of the strip conductor widths and of the distances between the strip conductors, of the dimensioning of the dielectric layer thicknesses between the copper layers and of the selection of the hole diameters of the vias.
- the circuit board and the control unit are optimized in such a way that particularly the structure of the circuit board layers, the selection of the circuit board material and the combination of the vias in the individual layers are selected in such a way that the transfer of heat from the components through the circuit board to the heat sink or to a carrier plate is particularly effective and the functioning of the circuit board is guaranteed even at high outside temperatures.
- very high (sometimes very specific) demands are made on the circuit board as a circuit carrier itself, but also on the population of the circuit carrier with casingless components.
- these requirements concern operating temperatures of more than 170° C. for very long operating times, high thermomechanical stress and cycle loads for the circuit carrier, the components and the junctions. Furthermore, very high demands are made on the reliability of the junctions between the electrical components and the circuit board, especially when bond connections are used. Moreover, the existing oil vapors must be prevented from influencing the operation of the control unit and the circuit board with the electrical components, which circuit board is integrated in the control unit. Furthermore, the circuit board must be resistant to high-frequency vibrations and be capable of carrying electric currents of up to 100 A or higher.
- FIG. 1 schematically shows a sectional view of an inventive control unit for the use as an integrated mechatronic gearbox controller
- FIG. 2 schematically shows a detail drawing of a part of the control unit according to FIG. 1 ;
- FIG. 3 schematically shows a perspective view of a copper skeleton of a multilayer circuit board with an active electrical component and several vias;
- FIG. 4 schematically shows a part of a longitudinal section through the circuit board shown in FIG. 3 ;
- FIG. 5 schematically shows a perspective view of a part of the circuit board skeleton shown in FIG. 3 with a first and a second blind via and portions of four buried vias.
- FIGS. 1 and 2 show an inventive control unit 1 for the use as an integrated mechatronic gearbox controller for a vehicle (not shown) in a sectional view and a detail drawing of a part of the control unit 1 .
- This so-called on-site electronic system can be created by the integration of the electronic control system and associated electronic components (e.g., sensors or valves) into the gearbox, wherein the electronic control system and the associated electronic components are not accommodated in a separate protected electronic-component space outside the gearbox.
- the electronic control system and the associated electronic components are accommodated in a casing 2 that in addition provides a shielding function.
- a heat sink 3 is provided for removing dissipated heat developing during the operation of the control unit 1 .
- the electronic control system and the associated electronic components comprise a multilayer circuit board 4 in the form of an HDI circuit board.
- the multilayer circuit board 4 comprises a plurality of circuit board layers arranged one over the other in a z-direction that are not explicitly shown and is thermally coupled to the heat sink 3 and fixed thereto by means of a first thermally conductive adhesive layer 5 , wherein the maximum deflection of the circuit board 4 is smaller than the layer thickness of the first thermally conductive adhesive layer 5 .
- active electrical components 6 in the form of semiconductors and passive electrical components 7 in the form of semiconductors are arranged that are fixed to the topmost layer of the circuit board 4 by means of a second thermally conductive adhesive layer 8 that is shown in greater detail in FIGS. 3 to 5 .
- the circuit board 4 is connected to a pressed screen 12 and flexible foil conductors 13 , 14 by means of bonding wires 9 to 11 , wherein the bonding wires 9 to 11 are aluminum or gold wire bond connections, in particular thick-wire bond connections.
- an electrically insulating sealing material 15 wherein the sealing material 15 is formed as a soft seal made of silicone gel, which soft seal is characterized by high thermal expansion and, at the same time, by a low modulus of elasticity so that it is suitable for the protection of the components of the control unit 1 even at high temperatures. Furthermore, the use of the sealing material 15 makes the use of casingless electrical components 6 , 7 possible.
- first blind vias 16 are provided in order to couple the topmost circuit board layer to the internal circuit board layers thermally and electrically.
- second blind vias 17 are provided in order to couple the bottommost circuit board layer to the internal circuit board layers thermally and electrically. Said first and second blind vias are plated blind holes.
- buried vias 18 are provided.
- the blind vias 16 , 17 and the buried vias 18 are used to improve the transfer of heat through the circuit board 4 , particularly to remove heat from the circuit board 4 on account of the heat-emitting active electrical components 6 .
- the circuit board layers each have at least one thermally conductive layer 19 to 24 .
- the thermally conductive layers 19 to 24 are shown in greater detail in FIG. 4 .
- the thermally conductive layers 19 to 24 of different circuit board layers are connected to each other by means of the blind vias 16 , 17 and the buried vias 18 in such a way that the blind vias 16 , 17 and the buried vias 18 as well as the thermally conductive layers 19 to 24 form a thermally conductive bridge from the topmost circuit board layer to the bottommost circuit board layer.
- the blind vias 16 , 17 and the buried vias 18 are used to improve vertical heat conduction.
- metallic inlays preferably copper inlays, may be used for heat removal (not shown).
- blind vias 16 , 17 and buried vias 18 for one connection are placed in parallel in the circuit board 4 .
- the blind vias 16 , 17 have a diameter of between 100 ⁇ m and 150 ⁇ m and the buried vias 18 have a diameter of at least 250 ⁇ m, i.e., at least the blind vias 16 , 17 are microvias that are preferably created by means of a laser.
- the multilayer circuit board 4 has a top outer circuit board layer with the blind vias 16 and a bottom outer circuit board layer with the blind vias 17 , i.e., one microvia layer each. Between the microvia layers, several intermediate layers, preferably four or six intermediate layers, are arranged in the center of the circuit board 4 , which intermediate layers are thermally connected to each other by means of the buried vias 18 .
- the circuit board layers are each made of a base material, the glass transition temperature of which is greater than or equal to 170° C.
- the base material is an electrically insulating material and the thermally conductive layers 19 to 24 are applied to the base material.
- the base material is a glass-fiber reinforced plastic material with ceramic particles added thereto. Furthermore, the base material is characterized by an extremely good cycle stability of more than 2,000 cycles between ⁇ 40° C. and +150° C. and by a very low thermal expansion. In order to achieve a thermal expansion in the z-direction of 30 ppm/K to 40 ppm/K, fillers, in particular ceramic particles, are added to the base material.
- the base material including the associated thermally conductive layer 19 to 24 has a layer thickness of at least 50 ⁇ m.
- the created strip conductors have strip conductor widths of at least 100 ⁇ m.
- the thermally conductive layers 19 to 24 and the walls 16 . 1 , 17 . 1 , 18 . 1 of the blind vias 16 , 17 and buried vias 18 are made of copper or coated with a copper layer. Said walls 16 . 1 , 17 . 1 , 18 . 1 are shown in greater detail in FIGS. 3 to 5 .
- the outer copper surface of the thermally conductive layers 19 to 24 is plated with an additional metallization layer in a manner not shown in greater detail.
- a sequence of films e.g., nickel, palladium and gold one after the other is deposited in a currentless process, for example.
- the processes for mounting the casingless electrical components onto the circuit board 4 (in particular soldering or adhesive bonding using conductive silver adhesives) and the processes for electrically contacting the electrical components 6 , 7 to the circuit board (preferably wire bonding techniques and/or flip-chip techniques for soldering) are made particularly reliable (or even made possible) by means of said additional or end metallization.
- wire bonding is performed by means of gold and/or aluminum wire.
- casingless active and passive electrical components 6 are used in the control unit 1 .
- Components that are accommodated in casings and that are soldered onto the circuit board 4 in order to be mechanically and electrically contacted thereto are not used since the heat they produce is poorly removed from them on account of the casing.
- the casingless active electrical components 6 are adhesively bonded onto the topmost circuit board layer by means of the second thermally conductive adhesive layer 8 that is made of conductive silver adhesive in particular.
- the electrical contact to the circuit board 4 is established by means of bonding wires 25 .
- FIG. 3 shows a perspective view of a copper skeleton of the circuit board 4 with six circuit board layers arranged one over the other, with an active electrical component 6 arranged on a topmost circuit board layer, and with several vias 16 , 17 , 18 .
- the circuit board 4 is an HDI circuit board.
- the circuit board layers each have a thermally conductive plane layer 19 to 24 .
- the thermally conductive layers 19 to 24 are arranged in planes that are parallel to each other and perpendicular to the z-direction.
- the thermally conductive layers 19 to 24 are each applied to the electrically insulating base material and made of copper.
- each circuit board layer is a glass-fiber reinforced epoxy resin with ceramic particles added thereto, wherein the selection of the respective glass-fiber reinforced epoxy resin may depend on the circuit board layer, whereby the epoxy resin used can be advantageously adapted to the position of the respective circuit board layer within the circuit board and/or to the use thereof.
- the electrically insulating base material fills the space between the thermally conductive layers 19 to 24 and the vias 16 , 17 , 18 and is not shown in FIG. 3 . Therefore, the part of the circuit board 4 shown in FIG. 3 is referred to as the copper skeleton of the circuit board 4 .
- the active electrical component 6 is a casingless semiconductor chip that emits heat during operation.
- the active electrical component 6 is firmly bonded to the topmost circuit board layer by means of the second thermally conductive adhesive layer 8 that is a conductive silver adhesive layer, for example.
- the heat sink 3 in the form of a heat conducting aluminum plate for absorbing heat from the circuit board 4 is arranged under the bottommost circuit board layer.
- the heat sink 3 is firmly bonded to the bottommost circuit board layer by means of the first thermally conductive adhesive layer 5 .
- the first thermally conductive adhesive layer 5 may be realized in the form of a silicone adhesive filled with ceramic particles, for example.
- FIG. 4 shows a part of a longitudinal section through the circuit board 4 shown in FIG. 3 .
- the topmost circuit board layer On its top side, the topmost circuit board layer has a first thermally conductive layer 19 facing a bottom of the active electrical component 6 .
- the surface of the first thermally conductive layer 19 is larger than the surface of the bottom of the active electrical component 6 .
- the first thermally conductive layer 19 is shown in segments, wherein each segment is a square and has a first blind via 16 in the form of a microvia arranged below the active electrical component 6 .
- the first blind vias 16 are blind holes extending through the first thermally conductive layer 19 to the second thermally conductive layer 20 of the second circuit board layer that is arranged below the topmost circuit board layer. Each first blind via 16 is rotationally symmetrically formed around the z-direction and slightly tapered towards the second thermally conductive layer 20 .
- the walls 16 . 1 of the first blind vias 16 are made of copper and connect the first thermally conductive layer 19 to the second thermally conductive layer 20 .
- each first blind via 16 has a diameter of approximately 150 ⁇ m at its upper end, and the first blind vias 16 are spaced approximately 500 ⁇ m apart, for example.
- the surface of the second thermally conductive layer 20 is larger than the surface of the first thermally conductive layer 19 , e.g., approximately twice as large.
- a third thermally conductive layer 21 of a third circuit board layer is arranged below the second thermally conductive layer 20 .
- a fourth thermally conductive layer 22 of a fourth circuit board layer is arranged below the third thermally conductive layer 21 .
- a fifth thermally conductive layer 23 of a fifth circuit board layer is arranged below the fourth thermally conductive layer 22 .
- the surfaces of the second, third, fourth and fifth thermally conductive layers 20 to 23 are the same size but may increase in size from top to bottom in other exemplary embodiments.
- the buried vias 18 extend from the second thermally conductive layer 20 to the fifth thermally conductive layer 23 .
- the buried vias 18 are cylindrical hollow bodies with walls 18 . 1 made of copper that each connect the second, third, fourth and fifth thermally conductive layers 20 to 23 to each other. In particular, they have a diameter of approximately 250 ⁇ m.
- the bottommost circuit board layer having on its bottom a sixth thermally conductive layer 24 facing the heat sink 3 is arranged below the fifth thermally conductive layer 23 .
- the sixth thermally conductive layer 24 is connected to the fifth thermally conductive layer 23 by means of the second blind vias 17 , wherein the design of the second blind vias 17 is the same as that of the first blind vias 16 , i.e., the second blind vias 17 are blind holes extending through the sixth thermally conductive layer 24 to the fifth thermally conductive layer 23 with walls 17 . 1 made of copper that connect the sixth thermally conductive layer 24 to the fifth thermally conductive layer 23 .
- the surface of the sixth thermally conductive layer 24 is larger than the surface of the fifth thermally conductive layer 23 , e.g., two to three times as large.
- the surface of the heat sink 3 facing the surface of the sixth thermally conductive layer 24 is at least as large as the surface of the sixth thermally conductive layer 24 .
- FIG. 5 shows a perspective view of a part of the skeleton of the circuit board 4 shown in FIG. 3 with the first blind vias 16 , the second blind vias 17 and portions of four buried vias 18 .
- FIG. 5 shows that the buried vias 18 are offset from the first and second blind vias 16 , 17 in the x-direction and in the y-direction.
- a specific structure of integrated gearbox controllers with multilayer (in particular HDI) circuit board solutions for extreme requirements can be realized by the described specific optimization of the circuit board technique, i.e., by the optimized materials, by the specific circuit board structure with an adapted dimensioning of the strip conductor widths, of the distances between the strip conductors, of the multifunctional end surface, of the dielectric layer thicknesses, by the optimized selection of the diameters of the vias 16 , 17 , 18 and of the bores required therefor as well as by the rugged design along with the use of the circuit board base materials.
Abstract
Description
- 1 control unit
- 2 casing
- 3 heat sink
- 4 circuit board
- 5 first thermally conductive adhesive layer
- 6 active electrical component
- 7 passive electrical component
- 8 second thermally conductive adhesive layer
- 9 bonding wire
- 10 bonding wire
- 11 bonding wire
- 12 pressed screen
- 13 foil conductor
- 14 foil conductor
- 15 sealing material
- 16 via, first blind via
- 16.1 wall
- 17 via, second blind via
- 17.1 wall
- 18 via, buried via
- 18.1 wall
- 19 thermally conductive layer
- 20 thermally conductive layer
- 21 thermally conductive layer
- 22 thermally conductive layer
- 23 thermally conductive layer
- 24 thermally conductive layer
- 25 bonding wire
Claims (20)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
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DE102009058914 | 2009-12-17 | ||
DE102009058915 | 2009-12-17 | ||
DE102009058915.5 | 2009-12-17 | ||
DE102009058915 | 2009-12-17 | ||
DE102009058914.7 | 2009-12-17 | ||
DE200910058914 DE102009058914A1 (en) | 2009-12-17 | 2009-12-17 | High density interconnect-multi layered printed circuit board, has upper and lower board layers with conducting layers, where total surface of conducting layer of upper layer is larger than total surface of conducting layer of lower layer |
PCT/DE2010/001209 WO2011072629A1 (en) | 2009-12-17 | 2010-10-15 | Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller |
Publications (2)
Publication Number | Publication Date |
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US20120287581A1 US20120287581A1 (en) | 2012-11-15 |
US8895871B2 true US8895871B2 (en) | 2014-11-25 |
Family
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US13/515,907 Active 2031-05-10 US8895871B2 (en) | 2009-12-17 | 2010-10-15 | Circuit board having a plurality of circuit board layers arranged one over the other having bare die mounting for use as a gearbox controller |
Country Status (5)
Country | Link |
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US (1) | US8895871B2 (en) |
EP (1) | EP2514282B1 (en) |
JP (1) | JP2013514674A (en) |
DE (1) | DE112010002548A5 (en) |
WO (1) | WO2011072629A1 (en) |
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DE102020202607A1 (en) * | 2020-02-28 | 2021-09-02 | Siemens Aktiengesellschaft | Electronic module, method for manufacturing an electronic module and industrial plant |
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US10893604B1 (en) | 2020-03-03 | 2021-01-12 | Goodrich Corporation | Potted printed circuit board module and methods thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2011072629A1 (en) | 2011-06-23 |
EP2514282B1 (en) | 2017-09-20 |
US20120287581A1 (en) | 2012-11-15 |
DE112010002548A5 (en) | 2012-08-23 |
JP2013514674A (en) | 2013-04-25 |
EP2514282A1 (en) | 2012-10-24 |
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