US9217772B2 - Systems and methods for characterizing devices - Google Patents

Systems and methods for characterizing devices Download PDF

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US9217772B2
US9217772B2 US13/562,485 US201213562485A US9217772B2 US 9217772 B2 US9217772 B2 US 9217772B2 US 201213562485 A US201213562485 A US 201213562485A US 9217772 B2 US9217772 B2 US 9217772B2
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test
instances
list
product device
specifications
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US20140040852A1 (en
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Kar Meng Thong
Alvin L. Calma
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Infineon Technologies AG
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. by varying supply voltage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/261Functional testing by simulating additional hardware, e.g. fault simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/263Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02TCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00Road transport of goods or passengers
    • Y02T10/80Technologies aiming to reduce greenhouse gasses emissions common to all road transportation technologies
    • Y02T10/82Elements for improving aerodynamics

Definitions

  • testing circuits can be time consuming and costly.
  • the benefits obtained by testing can be outweighed by the costs of performing the testing.
  • FIG. 1 is a block diagram illustrating an automatic test characterization system.
  • FIG. 2 is a block diagram illustrating a test flow generator system in accordance with an embodiment of the invention.
  • FIG. 4 is a block diagram illustrating a test data arrangement for a product device in accordance with an embodiment.
  • FIG. 5 is a block diagram illustrating a data processing system in accordance with an embodiment.
  • FIG. 6 is a flow diagram illustrating a method of performing characterization testing on a product device in accordance with an embodiment.
  • the present invention includes embodiments that provide automatic characterization of integrated circuits.
  • the embodiments include, for example, systems and methods for generating test flows and automatically testing integrated circuits and devices.
  • Circuits can encounter a variety of operating conditions during their lifetime.
  • the operating conditions or characteristics can include voltage inputs, power inputs, voltage values, DC levels, AC values, frequencies, temperature and the like. It can be difficult to design devices for all possible scenarios.
  • FIG. 1 is a block diagram illustrating an automatic characterization test system 100 in accordance with an embodiment.
  • the system 100 automatically tests and processes test data for an integrated circuit without requiring interactive input throughout the testing.
  • the system 100 includes a test development flow generator 102 , a characterization tool 104 , a product device 106 , and a data processing component 108 .
  • the product device 106 is an integrated circuit that has been fabricated according to specifications including design specifications and/or operating condition specifications. The specifications can include input signals, temperature conditions, power inputs, power variations, and the like. In one example, the product device 106 is an integrated circuit for automotive applications.
  • the characterization tool 104 is configured to selectively perform a variety of tests on integrated circuits.
  • the characterization tool 104 is configured to selective perform tests on the product device 106 .
  • the characterization tool 104 is configured to supply a variety of input signals and power signals, including but not limited to, Vdd, ground, bias voltages, varied frequencies, and the like.
  • the characterization tool 104 is also configured to subject the product device 106 to a variety of conditions, such as temperatures, pressures, humidity levels, and the like.
  • the characterization tool 104 is configured to obtain test data by measuring nodes and/or connections on the product device 106 .
  • the measurements can include output signals, output power levels, temperatures, and the like.
  • the test data can also include the applied input signals.
  • the characterization tool 104 includes probes and/or interconnects to provide the signals and obtain the measurements. These can include, for example, a socket to place an integrated circuit on.
  • the characterization tool 104 is controlled to perform the tests on the product device 106 .
  • the characterization tool 104 operates in response to a test flow, which specifies tests to perform and includes input values, power levels, timings, frequency values, and items to measure.
  • the data processing component 108 analyzes the test data and can automatically generate reports.
  • the data processing component 108 can provide the test data in raw form for further analysis. Additionally, the data processing component 108 can generate graphs or plots, compare different test instances with each other, identify faults, and the like.
  • the test development flow generator 102 develops the test flow utilized by the characterization tool 104 .
  • the test development flow generator 102 receives several inputs including the specifications for the device 106 , specific tests to perform (referred to as test instances), setups, and categories of testing. Based on the inputs, the test development flow generator 102 generates the test flow, which can encompass a wide variety and large number of test instances. This enables the wide variety and large number of test instances to be performed automatically without reconfiguring the characterization tool 104 in between. Further, user interaction is not required between tests.
  • FIG. 2 is a block diagram illustrating a test flow generator system 200 in accordance with an embodiment of the invention.
  • the system 200 generates a test flow that can be utilized by a characterization tool, such as described with regard to FIG. 1 .
  • the system 200 includes a test flow generator 202 , a user interface 212 and inputs or parameters including specifications 204 , test instances 206 , setups 208 and categories 210 .
  • the user interface 212 is configured to interactively obtain parameters for generating a test flow.
  • the parameters include the specifications 204 , the test instances 206 , the setups 208 and the categories 210 .
  • the user interface 212 can include lists and permit selection of one or more items in the lists in order to obtain the parameters.
  • the specifications 204 include specification values, also referred to as parameters or parameter values, that can be varied.
  • the values can include minimum, maximum values and step values.
  • the step values specify or determine the number of values to be tested for a range of values.
  • the values can specify DC or AC. Specification values can be removed if not needed. Variations in values can be specified as linear or non-linear and provided with a formula.
  • the specifications conform to ratings provided in a specification data sheet for a product device to be tested.
  • the specifications exceed ratings provided in the specification data sheet for the product to be tested. This can be done to identify areas where the product device exceeds the specification data sheet.
  • the test instances 206 include a list of test instances available for the product device according to the specifications 204 .
  • the user interface 212 generates or provides a list of available test instances according to the specifications 204 .
  • the test instances 206 can include, for example, increasing a supply voltage Vdd from a minimum value to a maximum value according to a step value.
  • the test instances 206 include increasing an input frequency from a minimum value to a maximum value according to a step value.
  • the setups 208 include a list of selected test instances to be performed on the product device.
  • the setups 208 include a list of available setups according to the specifications 204 and the test instances 206 .
  • the available setups can include, for example,
  • the setups 208 and the specifications 204 are provided to the test flow generator 202 as parameters for characterization.
  • the parameters are utilized by the test flow generator 202 to generate the test flow.
  • FIG. 3A is a block diagram illustrating a first portion 300 of a user interface in accordance with an embodiment.
  • the user interface facilitates obtaining parameters that can be utilized to generate a test flow for testing a product device with a characterization tool.
  • the user interface is provided as an example to facilitate understanding of the invention and this disclosure and can be utilized for component 212 of FIG. 2 .
  • the first portion 300 includes a parameter select input 302 , a max value input 304 , a min value input 306 , steps 308 , and a generated list of parameter values 310 .
  • the parameter select input 302 permits a user to select a parameter for testing.
  • the select input 302 is utilized to select a particular supply voltage (VDD33) for testing.
  • the input 302 may display a list of available parameters. Additionally, the input 302 may also permit entering parameters.
  • the max value input 304 permits specifying a maximum value for the selected parameter. In one example, the max value is set at 1.7 volts.
  • the min value input 306 permits specifying a minimum value for the selected parameter. In one example, the min value is set at 0.9 volts.
  • the steps input 308 permits specifying a number of steps between the max value and the min value. In one example, the steps are set to 10.
  • the specified steps are utilized to generate the list of parameter values 310 . In one example, the generated list includes 0.9, 0.98, 1.06, 1.14, . . . 1.7. The generated list specifies values that will be tested by the characterization tool.
  • the first portion 300 also includes a test instance select input 312 , a max value input 314 , a min value input 316 , steps 318 , and a generated list of test instances 320 .
  • the select input 312 permits a user to select a test instance for testing.
  • the input 312 is utilized to select a particular test instance for testing.
  • the input 312 may display a list of available instances. Additionally, the input 312 may also permit entering parameters.
  • the OK element 330 is activated to close the user interface, but saves any changes, for example, to the specifications 204 , test instances 206 , setups 208 and categories 210 , collectively the parameters for the test flow. Then, if this particular test flow is opened again, the previous settings are maintained.
  • the cancel element 332 exits the user interface without saving any changes. Thus, if a user made selections and didn't like them, the user could activate the cancel element 332 to effectively erase them.
  • the apply element 334 is similar to the OK element 330 , in that the apply element 334 saves changes when activated, however the apply element 334 keeps the user interface open.
  • the arrangement 400 is the output generated by a characterization tool performing tests in accordance with a test flow generated as described above.
  • the test flow includes the selected test instances and parameters involved to test specifications for a product device.
  • the arrangement 400 is specific to the product device.
  • the arrangement includes test values for three test instances, VDD13 vs VDD33 (2D), VDD13 vs tp (2D), and tp (1D)).
  • FIG. 5 is a block diagram illustrating a data processing system 500 in accordance with an embodiment.
  • the system 500 processes and analyzes test data to facilitate analysis.
  • the system 500 includes a test data arrangement 400 , a data processing component 508 , and analysis reports 504 for a product device.
  • the arrangement 400 is the output generated by a characterization tool performing tests in accordance with a test flow generated.
  • the test flow includes the selected test instances and parameters involved to test specifications for the product device.
  • the arrangement 400 includes a plurality of test instance data 402 .
  • Each includes test values particular to a selected test instance.
  • the test values can include, for example, file name, a plot (shmoo plot), setup (shmoo setup), test name, pattern name, data, user, job name, test mode, temperature, horizontal axis specs, vertical axis specs, site number, device number, and/or the like.
  • the data processing component 508 can be utilized in system 100 for the data processing component 108 , described above.
  • the data processing component 508 analyzes the test data and automatically generates analysis reports 504 .
  • the data processing component 508 can also provide the test data in raw form with the reports for further analysis. Additionally, the data processing component 508 can generate graphs or plots, compare different test instances with each other, identify faults, and the like.
  • the data processing component 508 includes a data cruncher in one example.
  • the data cruncher also referred to as a robustness data cruncher, facilitates viewing of test data.
  • the data cruncher can be utilized to compare data from varied test instances and/or test data from multiple product devices.
  • the analysis reports component 504 include one or more individual reports 502 .
  • the individual reports 502 include tests data and/or analysis for one or more test instances. Thus, the individual reports 502 can compare and contrast data from multiple test instances.
  • the individual reports 502 can include raw data, graphs, plots, and the like.
  • the individual reports 502 can also include pass/fail information by comparing test data with specifications for the product device.
  • the individual reports 502 can be generated automatically or in response to a user action, such as activation of a butt on a user interface.
  • the type and content of the individual reports 502 can be selected to include or exclude information and/or analysis.
  • the individual reports 502 are selected to provide only raw data.
  • the individual reports 502 have additional content selected to provide graphs, pass/fail information, analysis, and the like.
  • the analysis reports component 504 also includes a summary 506 .
  • the summary 506 includes qualitative and/or quantitative information about the product device.
  • the summary 506 can include graphs or plots and conveys an overall picture of the testing performed according to the test flow.
  • the summary 506 can include information on whether the device meets or exceeds requires specifications for the product device. Additionally, the summary 506 can identify areas or aspects of the device that require modification in order to meet the specifications for the product device.
  • the summary 506 can be provided to a user via a suitable mechanism.
  • the summary 506 can be printed, displayed on a screen, saved to a file, and the like.
  • the summary 506 is saved in HTML format.
  • the summary 506 is stored in XML formal.
  • a summary 506 includes test instances performed, plots analyzed, plots failing, plots or items with insufficient margin, plots with sufficient margin, duration of test, margin percentage or margin amount, values tested or input, ranges, and date of testing.
  • the margin is a percentage or amount of margin required from threshold or limit values.
  • FIG. 6 is a flow diagram illustrating a method 600 of performing characterization testing on a product device in accordance with an embodiment.
  • the method 600 can be utilized to identify characteristics of the product device, such as failure to comply with device or operational specifications.
  • the method 600 begins at block 602 , wherein specifications for a product device are obtained.
  • the specifications include designs and/or design specifications for which the product device was designed or fabricated.
  • the specifications can include, for example, input signals, temperature conditions, power inputs, power variations, and the like.
  • the product device is typically an integrated circuit. In one example, the integrated circuit is for automotive applications and is required by its specifications to operate in a relatively wide variety of temperature conditions, power inputs, power variations, and the like.
  • a list of test instances for a characterization tool is obtained at block 604 .
  • the list of test instances includes tests, such as power, frequency, and temperature tests, that the characterization tool is capable of performing. In one example, the list is limited to only those tests applicable to the product device. In one example, one of the test instances is an output as a variation of frequency and a supply voltage.
  • the selected test instances can be obtained in a variety of suitable ways.
  • Selectable setups according to devices can be available to guide the selections. For example, one or more setups particular to automotive integrated circuits can identify or pre-select a portion of the available test instances.
  • Test ranges or values are assigned to the test instances according to the specifications at block 608 .
  • the test ranges can include max values, min values, and step values for variable parameters and test conditions.
  • the test ranges are typically set according to the specifications so as to determine whether the product device meets or exceeds the specifications.
  • a test flow is generated at block 610 according to the assigned test ranges and the selected test instances.
  • the test flow is generated by combining the test instances in a suitable order, including repeating selected test instances with varied test ranges.
  • test data can be analyzed and/or aggregated to generate reports and the like regarding the characterization.
  • the test data is compared with the specifications to determine whether the product device meets the specifications.
  • the system includes a specifications component, a test instances component, a test setups component, and a categories component.
  • the specifications component is configured to have a list of parameter values that can be varied.
  • the test instances component is configured to have a list of test instances available for a product device.
  • the test setups component is configured to have a list of available setups according to the list of test instances and the specifications values.
  • the categories component is configured to have a list of selectable categories derived from the setups and the test instances.
  • the user interface is configured to generate selected test instances from the list of available test instances and selected parameters.
  • the test flow generator s configured to provide a test flow according to the selected test instances and the selected parameters.
  • Yet another embodiment includes a method of characterizing a device, such as an integrated circuit.
  • Specifications are obtained for a product device.
  • the specifications can include design specifications and/or operating requirement specifications.
  • a list of available test instances are obtained for a characterization tool.
  • Test instances are selected from the list of available test instances according to the specifications for the product device.
  • Test ranges are assigned for the test instances according to the specifications.
  • a test flow is generated according to the assigned test ranges and the selected test instances.
  • the product device is characterized by the characterization tool according to the generated test flow.

Abstract

A device characterization system includes a characterization tool and a test flow development generator. The characterization tool is configured to perform testing on a product device according to a test flow and generate test data. The characterization tool includes a list of available test instances that can be performed. The test flow development generator is configured to automatically generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances.

Description

BACKGROUND OF THE INVENTION
Circuits are integral components of modern devices ranging from cellular phones to automotive vehicles. Circuits are included in almost all devices. Circuits perform functions such as communications, control systems, and the like.
Circuit design is the process of designing circuits that can be utilized in devices. The process begins with identifying requirements or specifications for the circuit. The specifications can include voltage outputs, temperature range, operating environment, and the like. Once specifications are established, schematic diagrams are generated that meet the specifications. Simulations can then be performed to verify operation of the circuit design. Once verified, layouts and materials can be identified that are needed to implement the circuit design. Prototypes can then be built and tested for proper operation. A final design is then created from the preliminary layouts and circuit design. The final design includes methods of construction, materials, and the like. Further testing can be performed until final approval is obtained.
However, testing circuits can be time consuming and costly. The benefits obtained by testing can be outweighed by the costs of performing the testing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating an automatic test characterization system.
FIG. 2 is a block diagram illustrating a test flow generator system in accordance with an embodiment of the invention.
FIG. 3A is a block diagram illustrating a first portion of a user interface in accordance with an embodiment.
FIG. 3B is a block diagram illustrating a second portion of the user interface shown in FIG. 3A in accordance with an embodiment.
FIG. 4 is a block diagram illustrating a test data arrangement for a product device in accordance with an embodiment.
FIG. 5 is a block diagram illustrating a data processing system in accordance with an embodiment.
FIG. 6 is a flow diagram illustrating a method of performing characterization testing on a product device in accordance with an embodiment.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.
The present invention includes embodiments that provide automatic characterization of integrated circuits. The embodiments include, for example, systems and methods for generating test flows and automatically testing integrated circuits and devices.
Circuits can encounter a variety of operating conditions during their lifetime. The operating conditions or characteristics can include voltage inputs, power inputs, voltage values, DC levels, AC values, frequencies, temperature and the like. It can be difficult to design devices for all possible scenarios.
FIG. 1 is a block diagram illustrating an automatic characterization test system 100 in accordance with an embodiment. The system 100 automatically tests and processes test data for an integrated circuit without requiring interactive input throughout the testing.
The system 100 includes a test development flow generator 102, a characterization tool 104, a product device 106, and a data processing component 108. The product device 106 is an integrated circuit that has been fabricated according to specifications including design specifications and/or operating condition specifications. The specifications can include input signals, temperature conditions, power inputs, power variations, and the like. In one example, the product device 106 is an integrated circuit for automotive applications.
The characterization tool 104 is configured to selectively perform a variety of tests on integrated circuits. Here, the characterization tool 104 is configured to selective perform tests on the product device 106. The characterization tool 104 is configured to supply a variety of input signals and power signals, including but not limited to, Vdd, ground, bias voltages, varied frequencies, and the like. The characterization tool 104 is also configured to subject the product device 106 to a variety of conditions, such as temperatures, pressures, humidity levels, and the like.
The characterization tool 104 is configured to obtain test data by measuring nodes and/or connections on the product device 106. The measurements can include output signals, output power levels, temperatures, and the like. The test data can also include the applied input signals.
The characterization tool 104 includes probes and/or interconnects to provide the signals and obtain the measurements. These can include, for example, a socket to place an integrated circuit on.
The characterization tool 104 is controlled to perform the tests on the product device 106. The characterization tool 104 operates in response to a test flow, which specifies tests to perform and includes input values, power levels, timings, frequency values, and items to measure.
The data processing component 108 analyzes the test data and can automatically generate reports. The data processing component 108 can provide the test data in raw form for further analysis. Additionally, the data processing component 108 can generate graphs or plots, compare different test instances with each other, identify faults, and the like.
The test development flow generator 102 develops the test flow utilized by the characterization tool 104. The test development flow generator 102 receives several inputs including the specifications for the device 106, specific tests to perform (referred to as test instances), setups, and categories of testing. Based on the inputs, the test development flow generator 102 generates the test flow, which can encompass a wide variety and large number of test instances. This enables the wide variety and large number of test instances to be performed automatically without reconfiguring the characterization tool 104 in between. Further, user interaction is not required between tests.
In contrast, conventional mechanisms require a user to specify input values and timings for each particular test to be performed. Further, data from the varied tests is difficult to aggregate and analyze. As a result, circuit designers and developers may forego performing and/or analyzing tests and results due to the costs involved.
FIG. 2 is a block diagram illustrating a test flow generator system 200 in accordance with an embodiment of the invention. The system 200 generates a test flow that can be utilized by a characterization tool, such as described with regard to FIG. 1.
The system 200 includes a test flow generator 202, a user interface 212 and inputs or parameters including specifications 204, test instances 206, setups 208 and categories 210. The user interface 212 is configured to interactively obtain parameters for generating a test flow. The parameters include the specifications 204, the test instances 206, the setups 208 and the categories 210. The user interface 212 can include lists and permit selection of one or more items in the lists in order to obtain the parameters.
The specifications 204 include specification values, also referred to as parameters or parameter values, that can be varied. The values can include minimum, maximum values and step values. The step values specify or determine the number of values to be tested for a range of values. The values can specify DC or AC. Specification values can be removed if not needed. Variations in values can be specified as linear or non-linear and provided with a formula.
In one example, the specifications conform to ratings provided in a specification data sheet for a product device to be tested. In another example, the specifications exceed ratings provided in the specification data sheet for the product to be tested. This can be done to identify areas where the product device exceeds the specification data sheet.
The test instances 206 include a list of test instances available for the product device according to the specifications 204. In one example, the user interface 212 generates or provides a list of available test instances according to the specifications 204. The test instances 206 can include, for example, increasing a supply voltage Vdd from a minimum value to a maximum value according to a step value. In another example, the test instances 206 include increasing an input frequency from a minimum value to a maximum value according to a step value.
Then, one or more test instances from the list are selected and become the setups 208. The setups 208 include a list of selected test instances to be performed on the product device.
The setups 208 include a list of available setups according to the specifications 204 and the test instances 206. The available setups can include, for example,
The categories 210 integrate the setups 208 with the test instances 206 according to categories. The categories 210 include a list of available categories. Selection of a category from the list alters available test instances 206.
The setups 208 and the specifications 204 are provided to the test flow generator 202 as parameters for characterization. The parameters are utilized by the test flow generator 202 to generate the test flow.
FIG. 3A is a block diagram illustrating a first portion 300 of a user interface in accordance with an embodiment. The user interface facilitates obtaining parameters that can be utilized to generate a test flow for testing a product device with a characterization tool. The user interface is provided as an example to facilitate understanding of the invention and this disclosure and can be utilized for component 212 of FIG. 2.
The first portion 300 includes a parameter select input 302, a max value input 304, a min value input 306, steps 308, and a generated list of parameter values 310. The parameter select input 302 permits a user to select a parameter for testing. In one example, the select input 302 is utilized to select a particular supply voltage (VDD33) for testing. The input 302 may display a list of available parameters. Additionally, the input 302 may also permit entering parameters.
The max value input 304 permits specifying a maximum value for the selected parameter. In one example, the max value is set at 1.7 volts. The min value input 306 permits specifying a minimum value for the selected parameter. In one example, the min value is set at 0.9 volts. The steps input 308 permits specifying a number of steps between the max value and the min value. In one example, the steps are set to 10. The specified steps are utilized to generate the list of parameter values 310. In one example, the generated list includes 0.9, 0.98, 1.06, 1.14, . . . 1.7. The generated list specifies values that will be tested by the characterization tool.
The first portion 300 also includes a test instance select input 312, a max value input 314, a min value input 316, steps 318, and a generated list of test instances 320. The select input 312 permits a user to select a test instance for testing. In one example, the input 312 is utilized to select a particular test instance for testing. The input 312 may display a list of available instances. Additionally, the input 312 may also permit entering parameters.
The max value input 314 permits specifying a maximum value for the selected test instance. In one example, the max value is set at 4.25. The min value input 316 permits specifying a minimum value for the selected parameter. In one example, the min value is set at 2.5. The steps input 318 permits specifying a number of steps between the max value and the min value. In one example, the steps are set to 10. The specified steps are utilized to generate the list of instance values 320. In one example, the generated list includes 2.5, 2.68, 2.85, 3.02, . . . 4.25. The generated list specifies values that will be tested by the characterization tool.
FIG. 3B is a block diagram illustrating a second portion 301 of the user interface shown in FIG. 3A in accordance with an embodiment. The user interface facilitates obtaining parameters that can be utilized to generate a test flow for testing a product device with a characterization tool. The user interface is provided as an example to facilitate understanding of the invention and this disclosure and can be utilized for component 212 of FIG. 2.
The portion 301 of the user interface includes an OK element 330, a cancel element 332, an apply element 334, and a transform element 336. These elements control generation of a test flow from the selected parameters and selected test instances.
The OK element 330 is activated to close the user interface, but saves any changes, for example, to the specifications 204, test instances 206, setups 208 and categories 210, collectively the parameters for the test flow. Then, if this particular test flow is opened again, the previous settings are maintained.
The cancel element 332 exits the user interface without saving any changes. Thus, if a user made selections and didn't like them, the user could activate the cancel element 332 to effectively erase them.
The apply element 334 is similar to the OK element 330, in that the apply element 334 saves changes when activated, however the apply element 334 keeps the user interface open.
The transform element 336 transforms the selections into a test flow, such as a robustness test, when activated. A test instance sheet is generated that includes the selected test instances and selected parameters and values. The test instance sheet upon completion of the transformation is utilized for the test flow for the product device to be characterized. Once complete, the characterization tool can be activated to perform the test flow.
FIG. 4 is a block diagram illustrating a test data arrangement 400 for a product device in accordance with an embodiment. The arrangement 400 is provided as an example of a suitable arrangement in accordance with the invention.
The arrangement 400 is the output generated by a characterization tool performing tests in accordance with a test flow generated as described above. The test flow includes the selected test instances and parameters involved to test specifications for a product device. Thus, the arrangement 400 is specific to the product device.
In this example, the arrangement 400 includes a plurality of test instance data 402. Each includes test values particular to a selected test instance. The test values can include, for example, file name, a plot (shmoo plot), setup (shmoo setup), test name, pattern name, data, user, job name, test mode, temperature, horizontal axis specs, vertical axis specs, site number, device number, and/or the like.
In one example, the arrangement includes test values for three test instances, VDD13 vs VDD33 (2D), VDD13 vs tp (2D), and tp (1D)).
FIG. 5 is a block diagram illustrating a data processing system 500 in accordance with an embodiment. The system 500 processes and analyzes test data to facilitate analysis.
The system 500 includes a test data arrangement 400, a data processing component 508, and analysis reports 504 for a product device. The arrangement 400 is the output generated by a characterization tool performing tests in accordance with a test flow generated. The test flow includes the selected test instances and parameters involved to test specifications for the product device.
In this example, the arrangement 400 includes a plurality of test instance data 402. Each includes test values particular to a selected test instance. The test values can include, for example, file name, a plot (shmoo plot), setup (shmoo setup), test name, pattern name, data, user, job name, test mode, temperature, horizontal axis specs, vertical axis specs, site number, device number, and/or the like.
The data processing component 508 can be utilized in system 100 for the data processing component 108, described above. The data processing component 508 analyzes the test data and automatically generates analysis reports 504. The data processing component 508 can also provide the test data in raw form with the reports for further analysis. Additionally, the data processing component 508 can generate graphs or plots, compare different test instances with each other, identify faults, and the like.
The data processing component 508 includes a data cruncher in one example. The data cruncher, also referred to as a robustness data cruncher, facilitates viewing of test data. The data cruncher can be utilized to compare data from varied test instances and/or test data from multiple product devices.
The analysis reports component 504 include one or more individual reports 502. The individual reports 502 include tests data and/or analysis for one or more test instances. Thus, the individual reports 502 can compare and contrast data from multiple test instances.
The individual reports 502 can include raw data, graphs, plots, and the like. The individual reports 502 can also include pass/fail information by comparing test data with specifications for the product device.
The individual reports 502 can be generated automatically or in response to a user action, such as activation of a butt on a user interface. The type and content of the individual reports 502 can be selected to include or exclude information and/or analysis. Thus, in one example, the individual reports 502 are selected to provide only raw data. In another example, the individual reports 502 have additional content selected to provide graphs, pass/fail information, analysis, and the like.
The analysis reports component 504 also includes a summary 506. The summary 506 includes qualitative and/or quantitative information about the product device. The summary 506 can include graphs or plots and conveys an overall picture of the testing performed according to the test flow. The summary 506 can include information on whether the device meets or exceeds requires specifications for the product device. Additionally, the summary 506 can identify areas or aspects of the device that require modification in order to meet the specifications for the product device.
The summary 506 can be generated in response to a user action, such as activation of a button on a user interface, or can be generated automatically. In one example, the summary 506 includes a list of all test instances performed, parameters used, ranges of values for the parameters, test flow duration, values that passed, values that didn't pass, plots passed with margin, and the like.
The summary 506 can be provided to a user via a suitable mechanism. Thus, for example, the summary 506 can be printed, displayed on a screen, saved to a file, and the like. In one example, the summary 506 is saved in HTML format. In another example, the summary 506 is stored in XML formal.
In one example, a summary 506 includes test instances performed, plots analyzed, plots failing, plots or items with insufficient margin, plots with sufficient margin, duration of test, margin percentage or margin amount, values tested or input, ranges, and date of testing. The margin is a percentage or amount of margin required from threshold or limit values.
FIG. 6 is a flow diagram illustrating a method 600 of performing characterization testing on a product device in accordance with an embodiment. The method 600 can be utilized to identify characteristics of the product device, such as failure to comply with device or operational specifications.
The method 600 begins at block 602, wherein specifications for a product device are obtained. The specifications include designs and/or design specifications for which the product device was designed or fabricated. The specifications can include, for example, input signals, temperature conditions, power inputs, power variations, and the like. The product device is typically an integrated circuit. In one example, the integrated circuit is for automotive applications and is required by its specifications to operate in a relatively wide variety of temperature conditions, power inputs, power variations, and the like.
A list of test instances for a characterization tool is obtained at block 604. The list of test instances includes tests, such as power, frequency, and temperature tests, that the characterization tool is capable of performing. In one example, the list is limited to only those tests applicable to the product device. In one example, one of the test instances is an output as a variation of frequency and a supply voltage.
Test instances from the list of available test instances are selected at block 606 according to the specifications. The selected test instances represent or include test instances that measure or determine whether the product device meets the specifications. The selected test instances are typically a subset of the list of available test instances.
The selected test instances can be obtained in a variety of suitable ways. Selectable setups according to devices can be available to guide the selections. For example, one or more setups particular to automotive integrated circuits can identify or pre-select a portion of the available test instances.
Test ranges or values are assigned to the test instances according to the specifications at block 608. The test ranges can include max values, min values, and step values for variable parameters and test conditions. The test ranges are typically set according to the specifications so as to determine whether the product device meets or exceeds the specifications.
A test flow is generated at block 610 according to the assigned test ranges and the selected test instances. The test flow is generated by combining the test instances in a suitable order, including repeating selected test instances with varied test ranges.
The product device is automatically characterized at block 612 according to the generated test flow. A characterization tool, such as described above, is utilized to automatically characterize the product device by performing the tests. The characterization tool obtains test data, which includes measurements and the like for each of the test instances.
The test data can be analyzed and/or aggregated to generate reports and the like regarding the characterization. In one example, the test data is compared with the specifications to determine whether the product device meets the specifications.
While method 600 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
It is appreciated that the claimed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter (e.g., the circuits or systems shown in FIGS. 1-5, etc., are non-limiting examples of circuits or devices that may be used to implement method 600, and variations thereof).
One embodiment relates to a device characterization system. The device characterization system includes a characterization tool and a test flow development generator. The characterization tool is configured to perform testing on a product device according to a test flow and generate test data. The characterization tool includes a list of available test instances that can be performed. The test flow development generator is configured to automatically generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances.
Another embodiment relates to a test flow generation system. The system includes a specifications component, a test instances component, a test setups component, and a categories component. The specifications component is configured to have a list of parameter values that can be varied. The test instances component is configured to have a list of test instances available for a product device. The test setups component is configured to have a list of available setups according to the list of test instances and the specifications values. The categories component is configured to have a list of selectable categories derived from the setups and the test instances. The user interface is configured to generate selected test instances from the list of available test instances and selected parameters. The test flow generator s configured to provide a test flow according to the selected test instances and the selected parameters.
Yet another embodiment includes a method of characterizing a device, such as an integrated circuit. Specifications are obtained for a product device. The specifications can include design specifications and/or operating requirement specifications. A list of available test instances are obtained for a characterization tool. Test instances are selected from the list of available test instances according to the specifications for the product device. Test ranges are assigned for the test instances according to the specifications. A test flow is generated according to the assigned test ranges and the selected test instances. The product device is characterized by the characterization tool according to the generated test flow.
In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.

Claims (17)

What is claimed is:
1. A device characterization system comprising:
a characterization tool configured to perform testing on a product device according to a test flow and to generate test data, wherein the characterization tool includes a list of available test instances, wherein the list of available test instances are specific tests performable by the characterization tool and is altered by a selected category, wherein the characterization tool is an apparatus;
a test flow development generator configured to generate the test flow according to device specifications for the product device and selected test instances of the list of available test instances and to identify the selected test instances as only those tests applicable to the product device based on the device specifications:
wherein the characterization tool includes an interface configured to identify the selected category from a plurality of categories and identify the selected test instances from a modified list of available test instances, wherein the modified list of available test instances is altered from the list of available test instances according to the selected category; and
a data processing component configured to generate an analysis report based on the generated test data from the characterization tool and other product device data, wherein the analysis report identifies whether the product device meets the device specification.
2. The system of claim 1, further comprising a data processing component configured to receive the test data.
3. The system of claim 2, wherein the data processing component is configured to generate reports from the test data.
4. The system of claim 2, wherein the data processing component is configured to selectively analyze the test data.
5. The system of claim 4, wherein the data processing component is configured to generate a summary report that includes pass/fail information for the product device.
6. The system of claim 1, wherein the product device is an integrated circuit utilized for automotive applications.
7. The system of claim 1, wherein the selected test instances include test ranges that specify one or more properties of the product device to be tested and a range of input values.
8. The system of claim 1, wherein the list of available test instances includes test instances that specify temperature conditions.
9. The system of claim 1, wherein at least one of the list of available test instances tests supply voltage variations.
10. The system of claim 1, wherein the characterization tool is configured to supply a plurality of input signals including power signals according to the test flow.
11. The system of claim 1, wherein the characterization tool is configured to subject the product device to environmental conditions including temperature and pressure according to the test flow.
12. The system of claim 1, wherein the characterization tool is configured to obtain at least a portion of the test data by measuring nodes and connections on the product device.
13. The system of claim 1, wherein the test flow development generator is configured to receive specifications, test instances, setups, and categories.
14. The system of claim 1, wherein the test flow development generator is configured to combine the selected test instances to generate the test flow.
15. A method of characterizing a device, the method comprising:
obtaining specifications for a product device;
obtaining a list of test instances performable by a characterization tool, using a test flow generator apparatus, wherein obtaining the list of test instances includes selecting parameters and generating instance values for the list of test instances;
selecting a category from a plurality of categories and altering the list of test instances according to the selected category;
selecting test instances of the list of test instances applicable to the product device according to the specifications for the product device;
assigning test ranges for the selected test instances according to the specifications; and
generating a test flow according to the assigned test ranges and the selected test instances; and generating test data for the product device according to the generated test flow and generating an analysis report based on the generated test data, wherein the analysis report identifies whether the product device meets the device specification.
16. The method of claim 15, further comprising automatically characterizing the product device according to the test flow.
17. The method of claim 15, wherein selecting the test instances comprises selecting setups of testing.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11686761B1 (en) * 2021-12-09 2023-06-27 Nanya Technology Corporation Method and non-transitory computer-readable medium for performing multiple tests on a device under test

Citations (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4379259A (en) * 1980-03-12 1983-04-05 National Semiconductor Corporation Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber
US4656632A (en) * 1983-11-25 1987-04-07 Giordano Associates, Inc. System for automatic testing of circuits and systems
US20010010091A1 (en) * 1999-06-08 2001-07-26 Amos Noy Method and apparatus for maximizing test coverage
US6327686B1 (en) * 1999-04-22 2001-12-04 Compaq Computer Corporation Method for analyzing manufacturing test pattern coverage of critical delay circuit paths
US6378092B1 (en) 1999-10-15 2002-04-23 Hewlett-Packard Company Integrated circuit testing
US6546507B1 (en) * 1999-08-31 2003-04-08 Sun Microsystems, Inc. Method and apparatus for operational envelope testing of busses to identify halt limits
US6564347B1 (en) * 1999-07-29 2003-05-13 Intel Corporation Method and apparatus for testing an integrated circuit using an on-chip logic analyzer unit
US20030093737A1 (en) * 2001-11-13 2003-05-15 Michael Purtell Event based test system having improved semiconductor characterization map
US6574760B1 (en) * 1998-11-03 2003-06-03 Texas Instruments Incorporated Testing method and apparatus assuring semiconductor device quality and reliability
US20040183559A1 (en) * 2003-02-26 2004-09-23 Frederick Ware Method and apparatus for test and characterization of semiconductor components
US20040183578A1 (en) * 2003-03-21 2004-09-23 Kian Chong Mixed signal delay locked loop characterization engine
US6832182B1 (en) * 1999-04-08 2004-12-14 Transim Technology Corporation Circuit simulator
US6847853B1 (en) * 1997-11-06 2005-01-25 Vlt, Inc. Fabrication rules based automated design and manufacturing system and method
US20050154550A1 (en) * 2003-02-14 2005-07-14 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US20060010348A1 (en) * 2004-07-09 2006-01-12 Bylund Stefan E Method and apparatus for capture and formalization of system requirements and their transformation to test instructions
US7017094B2 (en) * 2002-11-26 2006-03-21 International Business Machines Corporation Performance built-in self test system for a device and a method of use
US7051301B2 (en) * 2003-10-01 2006-05-23 Hewlett-Packard Development Company, L.P. System and method for building a test case including a summary of instructions
US7100133B1 (en) * 2000-06-23 2006-08-29 Koninklijke Philips Electronics N.V Computer system and method to dynamically generate system on a chip description files and verification information
US7103860B2 (en) * 2002-01-25 2006-09-05 Logicvision, Inc. Verification of embedded test structures in circuit designs
US20060242503A1 (en) 2005-04-21 2006-10-26 Matsushita Electric Industrial Co., Ltd. Integrated circuit test system
US7184917B2 (en) * 2003-02-14 2007-02-27 Advantest America R&D Center, Inc. Method and system for controlling interchangeable components in a modular test system
US7197417B2 (en) * 2003-02-14 2007-03-27 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US7225372B2 (en) * 2000-11-30 2007-05-29 Renesas Technology Corp & Hitachi Ulsi Systems Co., Ltd. Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
US7286951B2 (en) * 2002-05-09 2007-10-23 Agilent Technologies, Inc. Externally controllable electronic test program
US20080016396A1 (en) * 2003-02-14 2008-01-17 Advantest Corporation Test emulator, test module emulator and record medium storing program therein
US7366951B2 (en) * 2002-05-24 2008-04-29 Fujitsu, Limited Method and apparatus for test program generation based on an instruction set description of a processor
US20080115029A1 (en) * 2006-10-25 2008-05-15 International Business Machines Corporation iterative test generation and diagnostic method based on modeled and unmodeled faults
US7400995B2 (en) * 2003-07-30 2008-07-15 Infineon Technologies Ag Device and method for testing integrated circuits
US20080262778A1 (en) * 2007-04-23 2008-10-23 Advantest Corporation Recording medium, test apparatus and program
US7467364B2 (en) * 2003-11-12 2008-12-16 International Business Machines Corporation Database mining method and computer readable medium carrying instructions for coverage analysis of functional verification of integrated circuit designs
US7506286B2 (en) * 1999-11-30 2009-03-17 Synopsys, Inc. Method and system for debugging an electronic system
US20090119542A1 (en) * 2007-11-05 2009-05-07 Advantest Corporation System, method, and program product for simulating test equipment
US7644324B2 (en) * 2006-06-26 2010-01-05 Yokogawa Electric Corporation Semiconductor memory tester
US7647219B2 (en) * 2005-07-11 2010-01-12 Texas Instruments Incorporated Event-driven test framework
US20100023294A1 (en) * 2008-07-28 2010-01-28 Credence Systems Corporation Automated test system and method
US20100049495A1 (en) * 2006-10-04 2010-02-25 Kenneth Francken Method and apparatus for the simultaneous multi-level and/or multi-simulator design optimization of electronic circuits
US7693676B1 (en) * 2006-09-08 2010-04-06 Cadence Design Systems, Inc. Low power scan test for integrated circuits
US7810004B2 (en) * 2006-04-06 2010-10-05 Infineon Technologies Ag Integrated circuit having a subordinate test interface
US7836416B2 (en) * 2000-11-28 2010-11-16 Synopsys, Inc. Hardware-based HDL code coverage and design analysis
US7870523B1 (en) * 2006-06-15 2011-01-11 Cadence Design Systems, Inc. System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction
US7979759B2 (en) * 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US7996742B2 (en) * 2007-11-08 2011-08-09 Infineon Technologies Ag Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement
US8099271B2 (en) * 1999-11-30 2012-01-17 Synopsys, Inc. Design instrumentation circuitry
US8155907B1 (en) * 2009-06-08 2012-04-10 Xilinx, Inc. Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product
US8185788B2 (en) * 2005-09-01 2012-05-22 Infineon Technologies Ag Semiconductor device test system with test interface means
US20120229145A1 (en) * 2011-03-10 2012-09-13 Infineon Technologies Ag Detection of Pre-Catastrophic, Stress Induced Leakage Current Conditions for Dielectric Layers
US20120260129A1 (en) * 2011-04-06 2012-10-11 Mosaic, Inc. Software testing supporting high reuse of test data
US8370784B2 (en) * 2010-07-13 2013-02-05 Algotochip Corporation Automatic optimal integrated circuit generator from algorithms and specification
US8375344B1 (en) * 2010-06-25 2013-02-12 Cadence Design Systems, Inc. Method and system for determining configurations
US8381051B2 (en) * 2010-04-23 2013-02-19 Stmicroelectronics International N.V. Testing of multi-clock domains
US8413088B1 (en) * 2007-06-07 2013-04-02 Cadence Design Systems, Inc. Verification plans to merging design verification metrics
US20130124932A1 (en) * 2011-11-14 2013-05-16 Lsi Corporation Solid-State Disk Manufacturing Self Test
US8516322B1 (en) * 2009-09-28 2013-08-20 Altera Corporation Automatic test pattern generation system for programmable logic devices
US20140013294A1 (en) * 2011-03-28 2014-01-09 Freescale Semiconductor, Inc Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product
US8650020B1 (en) * 2009-01-30 2014-02-11 Xilinx, Inc. Modeling second order effects for simulating transistor behavior
US8661397B2 (en) * 2009-01-15 2014-02-25 Electronic Warfare Associates, Inc. Systems and methods of implementing remote boundary scan features
US8726203B1 (en) * 2013-04-25 2014-05-13 Cydesign, Inc. System and method for generating virtual test benches
US20140310693A1 (en) * 2013-04-16 2014-10-16 Advantest Corporation Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing
US20140324378A1 (en) * 2013-04-30 2014-10-30 Advantest Corporation Automated generation of a test class pre-header from an interactive graphical user interface

Patent Citations (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4379259A (en) * 1980-03-12 1983-04-05 National Semiconductor Corporation Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber
US4656632A (en) * 1983-11-25 1987-04-07 Giordano Associates, Inc. System for automatic testing of circuits and systems
US6847853B1 (en) * 1997-11-06 2005-01-25 Vlt, Inc. Fabrication rules based automated design and manufacturing system and method
US6574760B1 (en) * 1998-11-03 2003-06-03 Texas Instruments Incorporated Testing method and apparatus assuring semiconductor device quality and reliability
US6832182B1 (en) * 1999-04-08 2004-12-14 Transim Technology Corporation Circuit simulator
US6327686B1 (en) * 1999-04-22 2001-12-04 Compaq Computer Corporation Method for analyzing manufacturing test pattern coverage of critical delay circuit paths
US20010010091A1 (en) * 1999-06-08 2001-07-26 Amos Noy Method and apparatus for maximizing test coverage
US7114111B2 (en) * 1999-06-08 2006-09-26 Cadence Design (Isreal) Ii Ltd. Method and apparatus for maximizing test coverage
US6564347B1 (en) * 1999-07-29 2003-05-13 Intel Corporation Method and apparatus for testing an integrated circuit using an on-chip logic analyzer unit
US6546507B1 (en) * 1999-08-31 2003-04-08 Sun Microsystems, Inc. Method and apparatus for operational envelope testing of busses to identify halt limits
US6378092B1 (en) 1999-10-15 2002-04-23 Hewlett-Packard Company Integrated circuit testing
US7506286B2 (en) * 1999-11-30 2009-03-17 Synopsys, Inc. Method and system for debugging an electronic system
US8099271B2 (en) * 1999-11-30 2012-01-17 Synopsys, Inc. Design instrumentation circuitry
US7100133B1 (en) * 2000-06-23 2006-08-29 Koninklijke Philips Electronics N.V Computer system and method to dynamically generate system on a chip description files and verification information
US7836416B2 (en) * 2000-11-28 2010-11-16 Synopsys, Inc. Hardware-based HDL code coverage and design analysis
US7225372B2 (en) * 2000-11-30 2007-05-29 Renesas Technology Corp & Hitachi Ulsi Systems Co., Ltd. Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
US20030093737A1 (en) * 2001-11-13 2003-05-15 Michael Purtell Event based test system having improved semiconductor characterization map
US7103860B2 (en) * 2002-01-25 2006-09-05 Logicvision, Inc. Verification of embedded test structures in circuit designs
US7286951B2 (en) * 2002-05-09 2007-10-23 Agilent Technologies, Inc. Externally controllable electronic test program
US7366951B2 (en) * 2002-05-24 2008-04-29 Fujitsu, Limited Method and apparatus for test program generation based on an instruction set description of a processor
US7017094B2 (en) * 2002-11-26 2006-03-21 International Business Machines Corporation Performance built-in self test system for a device and a method of use
US8255198B2 (en) * 2003-02-14 2012-08-28 Advantest Corporation Method and structure to develop a test program for semiconductor integrated circuits
US7197417B2 (en) * 2003-02-14 2007-03-27 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US7209851B2 (en) * 2003-02-14 2007-04-24 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US7184917B2 (en) * 2003-02-14 2007-02-27 Advantest America R&D Center, Inc. Method and system for controlling interchangeable components in a modular test system
US20080016396A1 (en) * 2003-02-14 2008-01-17 Advantest Corporation Test emulator, test module emulator and record medium storing program therein
US20050154550A1 (en) * 2003-02-14 2005-07-14 Advantest America R&D Center, Inc. Method and structure to develop a test program for semiconductor integrated circuits
US20040183559A1 (en) * 2003-02-26 2004-09-23 Frederick Ware Method and apparatus for test and characterization of semiconductor components
US20040183578A1 (en) * 2003-03-21 2004-09-23 Kian Chong Mixed signal delay locked loop characterization engine
US7400995B2 (en) * 2003-07-30 2008-07-15 Infineon Technologies Ag Device and method for testing integrated circuits
US7051301B2 (en) * 2003-10-01 2006-05-23 Hewlett-Packard Development Company, L.P. System and method for building a test case including a summary of instructions
US7467364B2 (en) * 2003-11-12 2008-12-16 International Business Machines Corporation Database mining method and computer readable medium carrying instructions for coverage analysis of functional verification of integrated circuit designs
US20060010348A1 (en) * 2004-07-09 2006-01-12 Bylund Stefan E Method and apparatus for capture and formalization of system requirements and their transformation to test instructions
US20060242503A1 (en) 2005-04-21 2006-10-26 Matsushita Electric Industrial Co., Ltd. Integrated circuit test system
US7647219B2 (en) * 2005-07-11 2010-01-12 Texas Instruments Incorporated Event-driven test framework
US8185788B2 (en) * 2005-09-01 2012-05-22 Infineon Technologies Ag Semiconductor device test system with test interface means
US7810004B2 (en) * 2006-04-06 2010-10-05 Infineon Technologies Ag Integrated circuit having a subordinate test interface
US7870523B1 (en) * 2006-06-15 2011-01-11 Cadence Design Systems, Inc. System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction
US7644324B2 (en) * 2006-06-26 2010-01-05 Yokogawa Electric Corporation Semiconductor memory tester
US7693676B1 (en) * 2006-09-08 2010-04-06 Cadence Design Systems, Inc. Low power scan test for integrated circuits
US20100049495A1 (en) * 2006-10-04 2010-02-25 Kenneth Francken Method and apparatus for the simultaneous multi-level and/or multi-simulator design optimization of electronic circuits
US20080115029A1 (en) * 2006-10-25 2008-05-15 International Business Machines Corporation iterative test generation and diagnostic method based on modeled and unmodeled faults
US20080262778A1 (en) * 2007-04-23 2008-10-23 Advantest Corporation Recording medium, test apparatus and program
US8413088B1 (en) * 2007-06-07 2013-04-02 Cadence Design Systems, Inc. Verification plans to merging design verification metrics
US20090119542A1 (en) * 2007-11-05 2009-05-07 Advantest Corporation System, method, and program product for simulating test equipment
US7996742B2 (en) * 2007-11-08 2011-08-09 Infineon Technologies Ag Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement
US20100023294A1 (en) * 2008-07-28 2010-01-28 Credence Systems Corporation Automated test system and method
US7979759B2 (en) * 2009-01-08 2011-07-12 International Business Machines Corporation Test and bring-up of an enhanced cascade interconnect memory system
US8661397B2 (en) * 2009-01-15 2014-02-25 Electronic Warfare Associates, Inc. Systems and methods of implementing remote boundary scan features
US8650020B1 (en) * 2009-01-30 2014-02-11 Xilinx, Inc. Modeling second order effects for simulating transistor behavior
US8155907B1 (en) * 2009-06-08 2012-04-10 Xilinx, Inc. Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product
US8516322B1 (en) * 2009-09-28 2013-08-20 Altera Corporation Automatic test pattern generation system for programmable logic devices
US8381051B2 (en) * 2010-04-23 2013-02-19 Stmicroelectronics International N.V. Testing of multi-clock domains
US8375344B1 (en) * 2010-06-25 2013-02-12 Cadence Design Systems, Inc. Method and system for determining configurations
US8370784B2 (en) * 2010-07-13 2013-02-05 Algotochip Corporation Automatic optimal integrated circuit generator from algorithms and specification
US20120229145A1 (en) * 2011-03-10 2012-09-13 Infineon Technologies Ag Detection of Pre-Catastrophic, Stress Induced Leakage Current Conditions for Dielectric Layers
US20140013294A1 (en) * 2011-03-28 2014-01-09 Freescale Semiconductor, Inc Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product
US20120260129A1 (en) * 2011-04-06 2012-10-11 Mosaic, Inc. Software testing supporting high reuse of test data
US20130124932A1 (en) * 2011-11-14 2013-05-16 Lsi Corporation Solid-State Disk Manufacturing Self Test
US20140310693A1 (en) * 2013-04-16 2014-10-16 Advantest Corporation Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing
US8726203B1 (en) * 2013-04-25 2014-05-13 Cydesign, Inc. System and method for generating virtual test benches
US20140324378A1 (en) * 2013-04-30 2014-10-30 Advantest Corporation Automated generation of a test class pre-header from an interactive graphical user interface

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