US9270507B2 - Stacked comparator topology for multi-level signaling - Google Patents
Stacked comparator topology for multi-level signaling Download PDFInfo
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- US9270507B2 US9270507B2 US14/162,648 US201414162648A US9270507B2 US 9270507 B2 US9270507 B2 US 9270507B2 US 201414162648 A US201414162648 A US 201414162648A US 9270507 B2 US9270507 B2 US 9270507B2
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- 230000011664 signaling Effects 0.000 title abstract description 23
- 230000005669 field effect Effects 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/066—Multilevel decisions, not including self-organising maps
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Definitions
- the following description relates to multi-level signaling and more particularly to a low-power, high-speed system and method for receiving a signal employing multi-level signaling.
- the signal When a digital signal is transmitted across a data bus using two levels, i.e., binary signaling, the signal switches between two values, representing a binary 0 or 1, respectively.
- the voltage on a conductor such as a wire or a printed wiring board trace, may be driven to a first value to signify a binary 0 and to a second value to signify a binary 1.
- Data may be sent across a bus at a higher data throughput, for a given clock rate, using multi-level signaling.
- multi-level signaling which may be referred to as four-level pulse amplitude modulation (PAM-4)
- the voltage on conductor may take one of four values.
- PAM-4 receiver the received signal may then be converted, for each of the four voltage values, to a pair of bits, with a first value corresponding to binary 00, a second value corresponding to binary 01, a third value corresponding to binary 10, and a fourth value corresponding to binary 11, respectively.
- the correspondence between the voltage levels and pairs of bits may be different, or another parallel signaling scheme, such as one-hot encoding, or inverse one-hot encoding, may be used.
- a multi-level receiver which receives a multi-level signal as input and produces parallel binary signals as output, may be constructed with multiple comparators in parallel, which may be identical except for the threshold voltage to which each is connected. One input of each comparator may be connected to the received signal V in , and the other input may be connected to a threshold voltage.
- Each comparator in such a multi-level receiver may be composed of a differential pair of transistors, with each transistor being connected to a resistor and to a shared current source.
- the current flowing through one of the resistors and one of the transistors in such a differential pair, and through the current source dissipates power, and if there are several such comparators in a receiver then several times as much power is dissipated.
- Power consumption may be reduced by operating the comparators in a sequential comparison mode in which only one comparator is active at any given time, but this approach, while reducing power consumption, also reduces the speed at which the receiver is capable of operating, resulting in slower data transmission and, accordingly, a loss of at least some of the benefits of using multi-level signaling.
- a plurality of comparators each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption.
- FETs field-effect transistors
- a system for receiving a multi-level signal including: a system input connection; a first differential pair and a second differential pair; each of the first differential pair and the second differential pair including a first switch and a second switch, each of the first switch and the second switch including a first switching terminal, a second switching terminal, and a control terminal, the second switching terminal of the first switch connected to the second switching terminal of the second switch, the control terminal of the first switch of the first differential pair connected to the system input connection, the control terminal of the first switch of the second differential pair connected to the system input connection, the first terminal of the second switch of the first differential, pair connected to: the second switching terminal of the first switch of the second differential pair; and the second switching terminal of the second switch of the second differential pair.
- At least one of the first switch or the second switch is a semiconductor switch.
- At least one the first switch or the second switch is a field effect transistor (FET).
- FET field effect transistor
- At least one the first switch or the second switch is a bipolar junction transistor (BJT).
- BJT bipolar junction transistor
- control terminal of the second switch of the first differential pair is connected to a voltage source at a first threshold voltage
- control terminal of the first switch of the second differential pair is connected to a voltage source at a second threshold voltage
- the first threshold voltage is greater than the second threshold voltage.
- the multi-level signal includes three adjacent levels, the first threshold voltage is half-way between a first adjacent pair of levels of the three adjacent levels, and the second threshold voltage is half-way between a second adjacent pair of levels of the three adjacent levels.
- the second switching terminal of the first switch of the first differential pair and the second switching terminal of the second switch of the first differential pair are connected to a first terminal of a current source; and the second terminal of the current source is connected to a first power supply connection.
- the first power supply connection is a ground connection of a power supply.
- the first switching terminal of the first switch of the first differential pair is connected to: a first system output connection; and a first terminal of a first load element; the first switching terminal of the first switch of the second differential pair is connected to: a second system output connection; and a first terminal of a second load element; a second terminal of the first load element is connected to a second power supply connection; and a second terminal of the second load element is connected to the second power supply connection.
- the second power supply connection is a positive connection of a power supply.
- At least one the first switch or the second switch is a semiconductor switch.
- At least one the first switch or the second switch is a field effect transistor (FET).
- FET field effect transistor
- At least one the first switch or the second switch is a bipolar junction transistor (BJT).
- BJT bipolar junction transistor
- control terminal of the second switch of the first differential pair is connected to a voltage source at a first threshold voltage
- control terminal of the first switch of the second differential pair is connected to a voltage source at a second threshold voltage
- the second threshold voltage is greater than the first threshold voltage
- the multi-level signal includes three adjacent levels, and the first threshold voltage is half-way between a first adjacent pair of levels of the three adjacent levels; and the second threshold voltage is half-way between a second adjacent pair of levels of the three adjacent levels.
- At least one of the first load element or the second load element is a resistor.
- At least one of the first load element or the second load element is a third switch
- the third switch includes a first switching terminal, a second switching terminal, and a control terminal, the control terminal of the third switch being connected to the first terminal of the third switch.
- the system includes a source terminal, a drain terminal, and a gate terminal, the drain terminal being the first switching terminal of the third switch, the source terminal being the second switching terminal of the third switch, and the gate being the control terminal of the third switch.
- FIG. 1A is a set of three eye diagrams illustrating binary data transmission at a first clock rate and at a second clock rate, and multi-level data transmission at the first clock rate;
- FIG. 1B is a hybrid block-schematic diagram of a related art multi-level receiver
- FIG. 2 is a schematic diagram of a level detector according to an embodiment of the present invention.
- FIG. 3 is a schematic diagram of a level detector in a first state of operation according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of a level detector in a second state of operation according to an embodiment of the present invention.
- FIG. 5 is a schematic diagram of a level detector in a third state of operation according to an embodiment of the present invention.
- FIG. 6 is a schematic diagram of a level detector in a fourth state of operation according to an embodiment of the present invention.
- FIG. 7 is a truth table illustrating inputs and outputs of an embodiment of the present invention.
- FIG. 8 is a display employing a multi-level transmitter and a multi-level receiver according to an embodiment of the present invention.
- FIG. 1A shows three eye diagrams, representing the transmission of digital data on an analog signal.
- a first eye diagram 110 shows data transmitted in a two-level or binary signaling scheme at a first clock rate and a first data rate.
- the system may be operated at a higher clock rate, i.e., with transitions spaced more closely in time, as illustrated in eye diagram 115 , or multi-level signaling may be used, as illustrated in eye diagram 120 .
- the eye diagram 120 shows four-level signaling, as may be used in PAM-4, for example.
- the voltage on a signal conductor may take four values of increasing voltage, i.e., a first value, a second value, a third value, and a fourth value, which are referred to herein as V 0 , V 1 , V 2 , and V 3 .
- a level detector may be used to distinguish between these for voltages, by comparing the received voltage to different threshold voltages.
- three threshold voltages may be used to receive PAM-4.
- the threshold voltages are referred to as V Th,H , V Th,M , and V Th,L , respectively, and may be selected so that each is approximately half-way between two adjacent levels of the multi-level signaling scheme.
- the threshold voltage V Th,L may be half-way between the first voltage value V 0 and the second voltage value V 1
- the threshold voltage V Th,M may be half-way between the second voltage value V 1 and the third voltage value V 2
- the threshold voltage V Th,H may be half-way between the third voltage value V 2 and the fourth voltage value V 3 .
- a multi-level receiver may include optional gain and equalization circuitry 125 , a level detector composed of a set of comparators 130 , 135 , 140 , and a decoder 145 .
- the output of the level detector may be a parallel digital signal with one-hot encoding, i.e., a parallel set of signals of which at most one represents a binary “1”, i.e., logic high, at any time.
- the decoder 145 may then convert the one-hot signal into a more compact binary signal.
- the receiver may receive four-level signaling such as PAM-4, the comparators may generate 3-line one-hot encoding at an intermediate bus 150 , and the decoder may convert data on the 3-line one-hot bus to, e.g., data on a 2-bit parallel bus 152 .
- Each of the comparators 130 , 135 , 140 may be formed as a differential pair of field-effect transistors (FETs) 155 , with the sources of the two FETs connected together at a point referred to as the source connection 160 , a current source 162 connected between the source connection 160 and ground, and the drain of each FET connected by a drain resistor 165 to the positive terminal of a power supply, which may also be referred to as Vcc.
- FETs field-effect transistors
- Each comparator has two inputs, one of which is connected to the input V in of the receiver, and one of which is connected to a threshold voltage; the threshold voltages are referred to as V Th,H , V Th,M , and V Th,L , respectively, and may be selected so that each is approximately half-way between two adjacent levels of the multi-level signaling scheme, as illustrated in eye diagram 120 of FIG. 1A .
- a multi-level receiver may be constructed by stacking comparators, as illustrated in an example with three comparators 130 , 135 , 140 , suitable for use in a PAM-4 receiver.
- Each comparator includes a first FET 210 and a second FET 215 configured as a differential pair with sources connected together at a source connection 160 .
- One input of each comparator is connected to the receiver input V in , and the other input of each comparator is connected to a threshold voltage, i.e., to V Th,H , V Th,M , or V Th,L .
- the source connection of the first comparator 130 is connected to one terminal of a current source 220 , the other terminal of which is connected to ground.
- the drain connection of the first FET 210 of each of the comparators 130 , 135 , 140 is connected through a resistor, i.e., a respective one of the resistors 230 , 235 , 240 , to Vcc.
- the drain connection of the second FET 215 of the first comparator 130 and the drain connection of the second comparator 135 are connected to the source connection 160 of the second comparator 135 and to the source connection of the third comparator 140 , respectively, and the drain connection of the second FET 215 of the third comparator 130 is connected to Vcc.
- inverted one-hot encoding refers to an encoding scheme on a parallel bus, in which at most one of the lines represents a binary “0”, i.e., logic low, at any time.
- each differential pair need not be FETs, but may be bipolar junction transistors, or other switches.
- a switch used in a differential pair may have a control terminal, a first switching terminal, and a second switching terminal.
- the base may be the control terminal and the collector and emitter may be the first and second switching terminal respectively, or the second and first switching terminal, respectively.
- the gate may be the control terminal and the drain and source may be the first and second switching terminal respectively, or the second and first switching terminal, respectively.
- the switches may be P-channel FETs instead of N-channel FETs as illustrated in FIG. 2 , or NPN or PNP transistors. If transistors are used for the switches, then, depending on the type of transistors used (e.g., NPN or PNP) the circuit may be inverted with respect to polarity, i.e., the resistors 230 , 235 , 240 may be connected to ground instead of Vcc, and the current source may be connected to Vcc.
- resistors are shown as the load elements between the drain connections of the first FETs 210 and Vcc, the invention is not thereby limited. Other elements may be used as load elements.
- a FET configured as a two-terminal device by connecting the gate and drain together may be used as a load element, for example.
- each of the three outputs V O,H , V O,M , and V O,L is at a voltage of Vcc, customarily representing logic high or binary “1”, when the first FET 210 of the corresponding comparator is switched off, and at a voltage near ground, customarily representing logic low or binary “0”, when the first FET 210 of the corresponding comparator is switched on.
- Vcc voltage of Vcc
- the encoding on the parallel bus formed by V O,H , V O,M , and V O,L is inverted one-hot encoding.
- V in exceeds V Th,H
- the first FET 210 of the first comparator 130 is switched on, i.e., it conducts from drain to source, and the second FET 215 of the first comparator 130 is switched off.
- the principal current path from Vcc to ground is through the first resistor 230 , through the first FET 210 of the first comparator 130 , as indicated by the arrow representing the current path 310 , and through the current source 220 .
- the output V O,H is low and the other two outputs, V O,M , and V O,L , are high.
- V in is greater than V Th,M , but is less than V Th,H , as it is when the received input is approximately equal to the voltage value V 2 , the first FET 210 of the first comparator 130 is switched off, and the second FET 215 of the first comparator 130 is switched on, because V in is less than V Th,H .
- the first FET 210 of the second comparator 135 is switched on, and the second FET 215 of the second comparator 135 is switched off, because V in exceeds V Th,M .
- V in is greater than V Th,L but is less than V Th,M
- the first FET 210 of the first comparator 130 is switched off, and the second FET 215 of the first comparator 130 is switched on, because V in is less than V Th,H .
- the first FET 210 of the second comparator 135 is switched off, and the second FET 215 of the second comparator 135 is switched on, because V in is less than V Th,M .
- the first FET 210 of the third comparator 140 is switched on, and the second FET 215 of the third comparator 140 is switched off, because V in exceeds V Th,L .
- the principal current path from Vcc to ground is through the third resistor 240 , through the first FET 210 of the third comparator 140 , as indicated by the arrow representing the current path 510 , through the second FET 215 of the second comparator 135 , through the second FET 215 of the first comparator 130 , and through the current source 220 .
- the output V O,L is low and the other two outputs, V O,H , and V O,M , are high.
- the first FET 210 of the first comparator 130 is switched off, and the second FET 215 of the first comparator 130 is switched on, because V in is less than V Th,H .
- the first FET 210 of the second comparator 135 is switched off, and the second FET 215 of the second comparator 135 is switched on, because V in is less than V Th,M .
- the first FET 210 of the third comparator 135 is switched off, and the second FET 215 of the third comparator 135 is switched on, because V in is less than V Th,L .
- the truth table of FIG. 7 summarizes the behavior of the embodiment of FIG. 2 .
- V in is less than V Th,L , all three outputs, V O,L , V O,M , and V O,H , are high.
- V in is greater than V Th,L , and less than V Th,M , V O,L , is low, and V O,M , and V O,H are high.
- V in is greater than V Th,M , and less than V Th,H , V O,M , is low, and V O,L , and V O,H are high.
- V in is greater than V Th,H , V O,H is low, and V O,L , and V O,M , are high.
- a digital display 810 such as an organic light emitting diode display or a liquid crystal display in a television or a cell phone, includes a multi-level transmitter 820 transmitting data to a multi-level receiver 830 .
- the multi-level receiver 830 may contain a level detector constructed according to an embodiment of the present invention.
- the present invention may be employed to transmit data between components of a display, the invention is not thereby limited, and it may be used in other applications in which data is transmitted from a transmitter to a receiver.
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US14/162,648 US9270507B2 (en) | 2013-04-22 | 2014-01-23 | Stacked comparator topology for multi-level signaling |
EP14165517.5A EP2797272B1 (en) | 2013-04-22 | 2014-04-22 | Stacked comparator topology for multi-level signaling |
CN201410161902.3A CN104113309B (en) | 2013-04-22 | 2014-04-22 | Stack comparator topology for multilevel signalling |
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US201361814759P | 2013-04-22 | 2013-04-22 | |
US14/162,648 US9270507B2 (en) | 2013-04-22 | 2014-01-23 | Stacked comparator topology for multi-level signaling |
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US20140314172A1 US20140314172A1 (en) | 2014-10-23 |
US9270507B2 true US9270507B2 (en) | 2016-02-23 |
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Citations (7)
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US5793816A (en) | 1993-12-10 | 1998-08-11 | International Business Machines Corporation | Method of transferring data between subsystems of a computer system |
US6377073B1 (en) | 1999-11-30 | 2002-04-23 | Texas Instruments Incorporated | Structure and method for reduction of power consumption in integrated circuit logic |
US20050201491A1 (en) * | 2004-03-09 | 2005-09-15 | Jason Wei | System and method for selecting optimal data transition types for clock and data recovery |
KR100699448B1 (en) | 2005-12-08 | 2007-03-28 | 한국전자통신연구원 | High-Credibility Flip-Flop and Mult-Threshold CMOS Latch Circuit Having Low Sub-Threshold Leakage Current |
US20080174343A1 (en) | 2007-01-18 | 2008-07-24 | Cha Young-Su | Data receiver and data receiving method |
KR20100027191A (en) | 2007-07-02 | 2010-03-10 | 마이크론 테크놀로지, 인크. | Fractional-rate decision feedback equalization useful in a data transmission system |
KR101188781B1 (en) | 2010-12-07 | 2012-10-10 | 삼성전자주식회사 | Low power latch device using threshold voltage scaling or using a stack structure of transistors |
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FR2868629B1 (en) * | 2004-04-05 | 2006-08-25 | Atmel Corp | DIFFERENTIAL THRESHOLD VOLTAGE DETECTOR |
TW200908553A (en) * | 2007-08-07 | 2009-02-16 | Univ Chung Yuan Christian | Multi-level comparator for fix power consumption |
JP2009231954A (en) * | 2008-03-19 | 2009-10-08 | Fujitsu Ltd | Multivalue signal receiver |
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2014
- 2014-01-23 US US14/162,648 patent/US9270507B2/en not_active Expired - Fee Related
- 2014-04-22 EP EP14165517.5A patent/EP2797272B1/en active Active
- 2014-04-22 CN CN201410161902.3A patent/CN104113309B/en active Active
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Publication number | Publication date |
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EP2797272B1 (en) | 2018-01-31 |
EP2797272A1 (en) | 2014-10-29 |
US20140314172A1 (en) | 2014-10-23 |
CN104113309A (en) | 2014-10-22 |
CN104113309B (en) | 2019-01-08 |
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