US9548357B2 - Shallow trench isolation structure with sigma cavity - Google Patents

Shallow trench isolation structure with sigma cavity Download PDF

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US9548357B2
US9548357B2 US14/716,696 US201514716696A US9548357B2 US 9548357 B2 US9548357 B2 US 9548357B2 US 201514716696 A US201514716696 A US 201514716696A US 9548357 B2 US9548357 B2 US 9548357B2
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dielectric layer
cavity
oxide
semiconductor structure
semiconductor substrate
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HaoCheng Tsai
Min-Hwa Chi
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GlobalFoundries US Inc
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Definitions

  • the present invention relates generally to semiconductor fabrication, and more particularly, to shallow trench isolation structures and methods of fabrication.
  • Transistors are commonly used in the integrated circuits (ICs).
  • ICs integrated circuits
  • carrier mobility e.g., electrons or holes
  • strain engineering has been applied since the 90 nm complementary metal-oxide semiconductor (CMOS) node.
  • CMOS complementary metal-oxide semiconductor
  • inducing a tensile strain in the channel of n-type transistors improves electron mobility while a compressive strain in the channel of p-type transistors improves hole mobility.
  • CMOS complementary metal-oxide semiconductor
  • CMOS complementary metal-oxide semiconductor
  • inducing a tensile strain in the channel of n-type transistors improves electron mobility while a compressive strain in the channel of p-type transistors improves hole mobility.
  • Various techniques have been proposed to induce the desired stress in the channel region of transistors.
  • transistors are scaled to smaller dimensions, there is a need for higher carrier mobility for
  • Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication.
  • the shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section.
  • the lower region is filled with a first material having good gap fill properties.
  • the sigma cavity is filled with a second material having good stress-inducing properties.
  • source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure.
  • the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.
  • embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a cavity formed in the semiconductor substrate, the cavity comprising an upper region and a lower region, wherein the upper region comprises a sigma cavity, and the lower region comprises a substantially rectangular cavity; a first dielectric layer disposed in the lower region; and a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate.
  • embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a transistor disposed on the semiconductor substrate, the transistor comprising a source/drain region and a gate; a shallow trench isolation structure disposed adjacent to the source/drain region, the shallow trench isolation structure comprising: a cavity formed in the semiconductor substrate, the cavity comprising an upper region and a lower region, wherein the upper region comprises a sigma cavity, and the lower region comprises a substantially rectangular cavity; a first dielectric layer disposed in the lower region; and a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate.
  • embodiments of the present invention provide a method of making a semiconductor structure, comprising: performing a first anisotropic etch in a semiconductor substrate to form a cavity; performing a sigma etch on the cavity to form an upper region of the cavity; performing a second anisotropic etch to form a lower region of the cavity; filling the lower region of the cavity with a first material; filling the upper region of the cavity with a second material; and planarizing the second material to a level flush with a top surface of the semiconductor substrate.
  • FIG. 1 is a semiconductor structure at a starting point for embodiments of the present invention.
  • FIG. 2 is a semiconductor structure after a subsequent process step of forming a sigma cavity in an upper region of a shallow trench isolation cavity in accordance with embodiments of the present invention.
  • FIG. 3 is a semiconductor structure after a subsequent process step of forming a lower region of a shallow trench isolation cavity in accordance with embodiments of the present invention.
  • FIG. 4 is a semiconductor structure after a subsequent process step of depositing a first fill material.
  • FIG. 5 is a semiconductor structure after a subsequent process step of recessing the first fill material.
  • FIG. 6 is a semiconductor structure after a subsequent process step of depositing a second fill material.
  • FIG. 7 is a semiconductor structure after a subsequent process step of recessing the second fill material.
  • FIG. 8 is a semiconductor structure including three fill materials in accordance with alternative illustrative embodiments.
  • FIG. 9 is a semiconductor structure in accordance with embodiments of the present invention including a transistor.
  • FIG. 10 is a semiconductor structure in accordance with alternative embodiments of the present invention including a transistor.
  • FIG. 11 is a flowchart indicating process steps for embodiments of the present invention.
  • first element such as a first structure, e.g., a first layer
  • second element such as a second structure, e.g. a second layer
  • intervening elements such as an interface structure, e.g. interface layer
  • FIG. 1 is a semiconductor structure 100 at a starting point for embodiments of the present invention.
  • Semiconductor structure 100 includes a substrate 102 and a shallow trench isolation (STI) cavity 104 disposed in the substrate 102 .
  • substrate 102 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, or another suitable substrate.
  • a protective layer 106 is deposited over the substrate 102 .
  • protective layer 106 may include a nitride such as silicon nitride (SiN), often referred to as hard mask.
  • FIG. 2 is semiconductor structure 100 after a subsequent process step of forming a sigma cavity 108 in an upper region 111 (see FIG. 3 ) of the shallow trench isolation cavity 104 in accordance with embodiments of the present invention.
  • Sigma cavity 108 is formed as a result of, for example, employing a fast etch-rate on the bottom surface which has a crystalline plane of (100) of cavity 104 by anisotropic wet-etching (e.g., utilizing tetramethylammonium hydroxide (TMAH), ammonium hydroxide, and/or potassium hydroxide).
  • TMAH tetramethylammonium hydroxide
  • ammonium hydroxide and/or potassium hydroxide
  • FIG. 3 is semiconductor structure 100 after a subsequent process step of forming a substantially rectangular cavity 112 in lower region 113 of a shallow trench isolation cavity 104 in accordance with embodiments of the present invention.
  • rectangular cavity 112 may have a slight taper (not shown) as a result of vertical anisotropic plasma etching (e.g. Cl-chemistry based plasma etching).
  • FIG. 4 is a semiconductor structure 100 after a subsequent process step of depositing a first fill layer 114 .
  • the first fill layer 114 may be a dielectric.
  • the first fill layer 114 may include spin-on dielectric, spin-on glass, or flowable oxide or another dielectric deposited by CVD (chemical vapor deposition) methods.
  • the first fill layer 114 preferably has a superior capability of gap-fill as the trench cavity has a small top critical dimension (CD) and depth (i.e., the largest aspect ratio).
  • CD critical dimension
  • SOD spin-on dielectric
  • the high density plasma (HDP) CVD oxide, HARP (high-aspect-ratio process) oxide, or enhanced high-aspect-ratio process (eHARP) oxide has reduced capability to gap-fill the trench (with small CD and large aspect ratio) but increased residual stress.
  • FIG. 5 is a semiconductor structure 100 after a subsequent process step of recessing the first fill layer 114 .
  • the recessing can be achieved a by hydrofluoric (HF) etch, or (SiCoNi) process, or CMP, or a combination of these.
  • FIG. 6 is a semiconductor structure 100 after a subsequent process step of depositing a second fill layer 116 .
  • the second fill layer 116 may include high density plasma (HDP) CVD oxide, silicon oxide, or HARP oxide.
  • the depositing may be achieved by other chemical vapor deposition (CVD) methods.
  • the second fill layer 116 does not require strong gap fill properties as needed with first fill layer 114 (see FIG. 5 ) because the aspect ratio of the upper region 111 is reduced.
  • FIG. 7 is a semiconductor structure 100 after a subsequent process step of recessing the second fill layer 116 .
  • the recessing causes the second dielectric fill layer 116 to be exposed and planar with a top surface of protective layer 106 .
  • the recessing may be performed by chemical mechanical polishing (CMP).
  • the semiconductor structure includes a semiconductor substrate 102 ; a cavity 104 formed in the semiconductor substrate, the cavity 104 including an upper region 111 and a lower region 113 , wherein the upper region includes a sigma cavity 108 , and the lower region 113 includes a substantially rectangular cavity 112 ; a first dielectric layer 114 disposed in the lower region; and a second dielectric layer 116 disposed in the upper region, wherein the second dielectric layer 114 is planar with a top surface of a protective layer 106 over the substrate 102 .
  • the cavity 104 has a depth D 1 .
  • D 1 may range from about 100 nanometers to about 300 nanometers.
  • the width of cavity 104 is continuously scaled to less than ⁇ 30 nm-50 nm at advanced complementary metal-oxide semiconductor (CMOS) node (e.g., 20 nm).
  • CMOS complementary metal-oxide semiconductor
  • Each of tips 110 a and 110 b has an angle A. In embodiments, A may be 109.4 degrees.
  • the tips are disposed at a distance D 2 below the top surface of the substrate 109 .
  • Each of the tips 110 a and 110 b serves as a concentrator of the residual stress in the upper portion 111 of STI trench cavity 104 and can re-direct the stress laterally into the Si with peak stress positioned at a distance of D 2 below the top surface of the substrate 109 (i.e., the position of the inversion charge carriers in the transistor channel).
  • D 2 ranges from about 6 nanometers to about 8 nanometers.
  • FIG. 8 is a semiconductor structure 200 including three fill layers in accordance with alternative illustrative embodiments.
  • Semiconductor structure 200 includes a semiconductor substrate 202 ; a STI cavity 204 formed in the semiconductor substrate 202 , the cavity 204 comprising an upper region 211 and a lower region 213 , wherein the upper region 211 comprises a sigma cavity 208 , and the lower region 213 comprises a substantially rectangular cavity 212 .
  • three layers are disposed in the cavity 204 for the more advanced cavity 204 with small top CD and depth (as compared to the two layers of the embodiment of FIG. 7 ).
  • dielectric layer 215 is deposited into cavity 204 , followed by dielectric layer 214 above dielectric layer 215 , and then dielectric layer 216 is deposited above dielectric layer 214 .
  • a protective layer 206 is the hard mask layer over the substrate 202 .
  • protective layer 206 may include a nitride such as silicon nitride (SiN). All other method steps to form the semiconductor structure of this embodiment are similar to those of FIGS. 1-7 .
  • the layer 214 may include a CVD oxide; the layer 216 may include a HARP oxide; and the layer 215 may include a flowable oxide, spin-on glass, or spin-on dielectric.
  • the dielectric layers are progressively easier to fill in the trench cavity 214 (i.e., the aspect ratio of cavity is progressively reduced toward the deposition of the last layer 216 ).
  • the last (i.e., top) layer 216 for gap-fill can use the HDP method with the highest mechanical hardness and strain, though the least gap-fill capability.
  • This embodiment is designed for an advanced STI cavity with smaller top CD and deeper depth (than FIG. 7 ) for future generations of CMOS.
  • the STI trench filling can be more than three layers at the cost of process complexity.
  • the tips serve as a concentrator and re-direct the residual stress in the upper portion of STI trench laterally into the substrate with peak stress positioned at the same level of the inversion carriers in the transistor channel.
  • FIG. 9 is a semiconductor structure 300 in accordance with embodiments of the present invention including a transistor.
  • Semiconductor structure 300 includes a semiconductor substrate 302 and transistor 320 disposed on the semiconductor substrate 302 .
  • the transistor 320 includes a gate stack 324 and source/drain regions 322 a - b without stressor material.
  • the gate stack 324 includes a gate 330 over a gate dielectric 332 , such as silicon oxide, hafnium oxide, or zirconium oxide, and spacers 334 a and 334 b at each side of the gate 330 and gate dielectric 332 .
  • the spacers can include a nitride or oxide such as silicon nitride or silicon oxide.
  • a shallow trench isolation structure is disposed adjacent to the source/drain region 322 a .
  • the shallow trench isolation structure includes a cavity 304 formed in the semiconductor substrate 302 , the STI cavity 304 comprising an upper region 311 and a lower region 313 .
  • the upper region comprises a sigma cavity 308
  • the lower region 313 comprises a substantially rectangular cavity 312 .
  • a first dielectric layer 314 is disposed in the lower region 313
  • a second dielectric layer 316 is disposed in the upper region 311 , and is planar with a top surface of the substrate 302 .
  • the first dielectric layer comprises a spin-on dielectric, spin-on-glass, or flowable CVD oxide
  • the second dielectric layer comprises a high density plasma (HDP) oxide and/or silicon nitride.
  • HDP high density plasma
  • FIG. 10 is a semiconductor structure in accordance with alternative embodiments of the present invention including a transistor.
  • Semiconductor structure 400 includes a semiconductor substrate 402 and transistor 420 disposed on the semiconductor substrate 402 .
  • the transistor 420 includes a gate stack 424 and source/drain region 422 a - b including stressor material 450 .
  • the gate stack 424 includes a gate 430 over a gate dielectric 432 , such as silicon oxide, hafnium oxide, or zirconium oxide, and spacers 434 a and 434 b at each side of the gate 430 and gate dielectric 432 .
  • the spacers can include a nitride or oxide such as silicon nitride or silicon oxide.
  • a shallow trench isolation structure is disposed adjacent to the source/drain region 422 a .
  • the shallow trench isolation structure includes a cavity 404 formed in the semiconductor substrate 402 , the STI cavity 404 comprising an upper region 411 and a lower region 413 .
  • the upper region comprises a sigma cavity 408
  • the lower region 413 comprises a substantially rectangular cavity 412 .
  • a first dielectric layer 414 is disposed in the lower region 413
  • a second dielectric layer 416 is disposed in the upper region 411 , and is planar with a top surface of the substrate 402 .
  • the source/drain region 422 a - b further includes a compressive stress material and the second dielectric layer 416 includes a compressive stress material.
  • the source/drain regions 422 a - b further include a tensile stress material and the second dielectric layer 416 includes a compressive stress material.
  • the source/drain regions 422 a - b further comprise a tensile stress material and the second dielectric layer 416 includes a tensile stress material.
  • the source/drain region 422 further includes a compressive stress material and the second dielectric layer 416 includes a tensile stress material.
  • Embodiments of the present invention may be used with PFET (p-type field effect transistor) or NFET (n-type field effect transistor) devices.
  • stressor material 450 may be comprised of silicon germanium for compressive stress.
  • stressor material 450 may be comprised of silicon phosphorus, silicon carbon, or silicon carbon phosphorus for tensile stress.
  • the upper fill material (second dielectric layer 416 ) and stressor material 450 may be of similar or opposite stress types (tensile or compressive). This allows tuning of the channel stress to accommodate design flexibility.
  • FIG. 11 is a flowchart indicating process steps for embodiments of the present invention.
  • a first etch in a semiconductor substrate is performed to form a cavity.
  • the etch may be an anisotropic etch such as a reactive ion etch (RIE).
  • RIE reactive ion etch
  • a sigma etch is performed on the cavity to form an upper region of the cavity.
  • the etch may be performed with a wet etch process utilizing, e.g., tetramethylammonium hydroxide (TMAH), ammoniumhydroxide, and/or potassium hydroxide (KOH).
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • the etch may be an anisotropic etch such as a reactive ion etch.
  • the lower region of the cavity is filled with a first dielectric material.
  • the filling may be achieved by chemical vapor deposition.
  • the first material may be spin-on-dielectric, spin-on glass, and/or flowable oxide.
  • the first material is recessed.
  • the recessing may be achieved by chemical mechanical planarizing (CMP) first and followed by reactive ion etching (RIE) or selective wet etch process.
  • CMP chemical mechanical planarizing
  • RIE reactive ion etching
  • the upper region of the cavity is filled with a second material. This filling may be performed by various CVD methods.
  • the second material may be HDP oxide or SiN for stronger residual stress.
  • the second material may be planarized to a level flush with a top surface of the semiconductor substrate.
  • the planarization may be achieved by chemical mechanical polish (CMP).

Abstract

Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of co-pending application Ser. No. 14/334,953 filed Jul. 18, 2014.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication, and more particularly, to shallow trench isolation structures and methods of fabrication.
BACKGROUND OF THE INVENTION
Transistors are commonly used in the integrated circuits (ICs). Today's transistors with scaled critical dimensions (CD) demand higher carrier mobility for device performance. To improve carrier mobility (e.g., electrons or holes), strain engineering has been applied since the 90 nm complementary metal-oxide semiconductor (CMOS) node. Generally, inducing a tensile strain in the channel of n-type transistors improves electron mobility while a compressive strain in the channel of p-type transistors improves hole mobility. Various techniques have been proposed to induce the desired stress in the channel region of transistors. As transistors are scaled to smaller dimensions, there is a need for higher carrier mobility for switching speeds. Thus, stress/strain engineering has become increasingly important in recent years. It is therefore desirable to have improvements in the inducement and control of stressors for transistors.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.
In a first aspect, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a cavity formed in the semiconductor substrate, the cavity comprising an upper region and a lower region, wherein the upper region comprises a sigma cavity, and the lower region comprises a substantially rectangular cavity; a first dielectric layer disposed in the lower region; and a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate.
In a second aspect, embodiments of the present invention provide a semiconductor structure, comprising: a semiconductor substrate; a transistor disposed on the semiconductor substrate, the transistor comprising a source/drain region and a gate; a shallow trench isolation structure disposed adjacent to the source/drain region, the shallow trench isolation structure comprising: a cavity formed in the semiconductor substrate, the cavity comprising an upper region and a lower region, wherein the upper region comprises a sigma cavity, and the lower region comprises a substantially rectangular cavity; a first dielectric layer disposed in the lower region; and a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate.
In a third aspect, embodiments of the present invention provide a method of making a semiconductor structure, comprising: performing a first anisotropic etch in a semiconductor substrate to form a cavity; performing a sigma etch on the cavity to form an upper region of the cavity; performing a second anisotropic etch to form a lower region of the cavity; filling the lower region of the cavity with a first material; filling the upper region of the cavity with a second material; and planarizing the second material to a level flush with a top surface of the semiconductor substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.
Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines, which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
FIG. 1 is a semiconductor structure at a starting point for embodiments of the present invention.
FIG. 2 is a semiconductor structure after a subsequent process step of forming a sigma cavity in an upper region of a shallow trench isolation cavity in accordance with embodiments of the present invention.
FIG. 3 is a semiconductor structure after a subsequent process step of forming a lower region of a shallow trench isolation cavity in accordance with embodiments of the present invention.
FIG. 4 is a semiconductor structure after a subsequent process step of depositing a first fill material.
FIG. 5 is a semiconductor structure after a subsequent process step of recessing the first fill material.
FIG. 6 is a semiconductor structure after a subsequent process step of depositing a second fill material.
FIG. 7 is a semiconductor structure after a subsequent process step of recessing the second fill material.
FIG. 8 is a semiconductor structure including three fill materials in accordance with alternative illustrative embodiments.
FIG. 9 is a semiconductor structure in accordance with embodiments of the present invention including a transistor.
FIG. 10 is a semiconductor structure in accordance with alternative embodiments of the present invention including a transistor.
FIG. 11 is a flowchart indicating process steps for embodiments of the present invention.
 DETAILED DESCRIPTION
Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, are interchangeable and specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” “some embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments”, “in some embodiments”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. It will be understood that one skilled in the art may cross embodiments by “mixing and matching” one or more features of one embodiment with one or more features of another embodiment.
The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
FIG. 1 is a semiconductor structure 100 at a starting point for embodiments of the present invention. Semiconductor structure 100 includes a substrate 102 and a shallow trench isolation (STI) cavity 104 disposed in the substrate 102. In embodiments, substrate 102 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, or another suitable substrate. A protective layer 106 is deposited over the substrate 102. In embodiments, protective layer 106 may include a nitride such as silicon nitride (SiN), often referred to as hard mask.
Referring now to FIGS. 2 and 3, STI cavity 104 is further extended to include a sigma cavity and a substantially rectangular lower region. FIG. 2 is semiconductor structure 100 after a subsequent process step of forming a sigma cavity 108 in an upper region 111 (see FIG. 3) of the shallow trench isolation cavity 104 in accordance with embodiments of the present invention. Sigma cavity 108 is formed as a result of, for example, employing a fast etch-rate on the bottom surface which has a crystalline plane of (100) of cavity 104 by anisotropic wet-etching (e.g., utilizing tetramethylammonium hydroxide (TMAH), ammonium hydroxide, and/or potassium hydroxide). The characteristic “sigma” shape of the sidewall is outlined by the slower etch-rate on the surfaces which have a crystalline plane of (111). Tips of the sigma cavity 108 are shown at 110 a and 110 b. FIG. 3 is semiconductor structure 100 after a subsequent process step of forming a substantially rectangular cavity 112 in lower region 113 of a shallow trench isolation cavity 104 in accordance with embodiments of the present invention. In embodiments, rectangular cavity 112 may have a slight taper (not shown) as a result of vertical anisotropic plasma etching (e.g. Cl-chemistry based plasma etching).
FIG. 4 is a semiconductor structure 100 after a subsequent process step of depositing a first fill layer 114. In embodiments, the first fill layer 114 may be a dielectric. In embodiments, the first fill layer 114 may include spin-on dielectric, spin-on glass, or flowable oxide or another dielectric deposited by CVD (chemical vapor deposition) methods. The first fill layer 114 preferably has a superior capability of gap-fill as the trench cavity has a small top critical dimension (CD) and depth (i.e., the largest aspect ratio). Spin-on-glass (SOG) or spin-on dielectric (SOD) has the easiest (best) capability to gap-fill the trench (with small CD and high aspect ratio) and a reduced residual stress in contrast to CVD or plasma enhanced CVD methods. In the opposite manner, the high density plasma (HDP) CVD oxide, HARP (high-aspect-ratio process) oxide, or enhanced high-aspect-ratio process (eHARP) oxide has reduced capability to gap-fill the trench (with small CD and large aspect ratio) but increased residual stress.
FIG. 5 is a semiconductor structure 100 after a subsequent process step of recessing the first fill layer 114. In embodiments, the recessing can be achieved a by hydrofluoric (HF) etch, or (SiCoNi) process, or CMP, or a combination of these.
FIG. 6 is a semiconductor structure 100 after a subsequent process step of depositing a second fill layer 116. In embodiments, the second fill layer 116 may include high density plasma (HDP) CVD oxide, silicon oxide, or HARP oxide. In embodiments, the depositing may be achieved by other chemical vapor deposition (CVD) methods. The second fill layer 116 does not require strong gap fill properties as needed with first fill layer 114 (see FIG. 5) because the aspect ratio of the upper region 111 is reduced.
FIG. 7 is a semiconductor structure 100 after a subsequent process step of recessing the second fill layer 116. The recessing causes the second dielectric fill layer 116 to be exposed and planar with a top surface of protective layer 106. In embodiments, the recessing may be performed by chemical mechanical polishing (CMP).
As shown in FIG. 7, the disclosed method results in a semiconductor structure 100 in accordance with embodiments of the present invention. The semiconductor structure includes a semiconductor substrate 102; a cavity 104 formed in the semiconductor substrate, the cavity 104 including an upper region 111 and a lower region 113, wherein the upper region includes a sigma cavity 108, and the lower region 113 includes a substantially rectangular cavity 112; a first dielectric layer 114 disposed in the lower region; and a second dielectric layer 116 disposed in the upper region, wherein the second dielectric layer 114 is planar with a top surface of a protective layer 106 over the substrate 102. The cavity 104 has a depth D1. In embodiments, D1 may range from about 100 nanometers to about 300 nanometers. The width of cavity 104 is continuously scaled to less than ˜30 nm-50 nm at advanced complementary metal-oxide semiconductor (CMOS) node (e.g., 20 nm). Each of tips 110 a and 110 b (see FIG. 3) has an angle A. In embodiments, A may be 109.4 degrees. The tips are disposed at a distance D2 below the top surface of the substrate 109. Each of the tips 110 a and 110 b serves as a concentrator of the residual stress in the upper portion 111 of STI trench cavity 104 and can re-direct the stress laterally into the Si with peak stress positioned at a distance of D2 below the top surface of the substrate 109 (i.e., the position of the inversion charge carriers in the transistor channel). In embodiments, D2 ranges from about 6 nanometers to about 8 nanometers.
FIG. 8 is a semiconductor structure 200 including three fill layers in accordance with alternative illustrative embodiments. Semiconductor structure 200 includes a semiconductor substrate 202; a STI cavity 204 formed in the semiconductor substrate 202, the cavity 204 comprising an upper region 211 and a lower region 213, wherein the upper region 211 comprises a sigma cavity 208, and the lower region 213 comprises a substantially rectangular cavity 212. In this embodiment, three layers are disposed in the cavity 204 for the more advanced cavity 204 with small top CD and depth (as compared to the two layers of the embodiment of FIG. 7). Accordingly, dielectric layer 215 is deposited into cavity 204, followed by dielectric layer 214 above dielectric layer 215, and then dielectric layer 216 is deposited above dielectric layer 214. A protective layer 206 is the hard mask layer over the substrate 202. In embodiments, protective layer 206 may include a nitride such as silicon nitride (SiN). All other method steps to form the semiconductor structure of this embodiment are similar to those of FIGS. 1-7. In embodiments, the layer 214 may include a CVD oxide; the layer 216 may include a HARP oxide; and the layer 215 may include a flowable oxide, spin-on glass, or spin-on dielectric. Note that the dielectric layers are progressively easier to fill in the trench cavity 214 (i.e., the aspect ratio of cavity is progressively reduced toward the deposition of the last layer 216). Thus, the last (i.e., top) layer 216 for gap-fill can use the HDP method with the highest mechanical hardness and strain, though the least gap-fill capability. This embodiment is designed for an advanced STI cavity with smaller top CD and deeper depth (than FIG. 7) for future generations of CMOS. Certainly, the STI trench filling can be more than three layers at the cost of process complexity. The tips serve as a concentrator and re-direct the residual stress in the upper portion of STI trench laterally into the substrate with peak stress positioned at the same level of the inversion carriers in the transistor channel.
FIG. 9 is a semiconductor structure 300 in accordance with embodiments of the present invention including a transistor. Semiconductor structure 300 includes a semiconductor substrate 302 and transistor 320 disposed on the semiconductor substrate 302. The transistor 320 includes a gate stack 324 and source/drain regions 322 a-b without stressor material. The gate stack 324 includes a gate 330 over a gate dielectric 332, such as silicon oxide, hafnium oxide, or zirconium oxide, and spacers 334 a and 334 b at each side of the gate 330 and gate dielectric 332. In embodiments, the spacers can include a nitride or oxide such as silicon nitride or silicon oxide. A shallow trench isolation structure is disposed adjacent to the source/drain region 322 a. The shallow trench isolation structure includes a cavity 304 formed in the semiconductor substrate 302, the STI cavity 304 comprising an upper region 311 and a lower region 313. The upper region comprises a sigma cavity 308, and the lower region 313 comprises a substantially rectangular cavity 312. A first dielectric layer 314 is disposed in the lower region 313, and a second dielectric layer 316 is disposed in the upper region 311, and is planar with a top surface of the substrate 302. In embodiments, the first dielectric layer comprises a spin-on dielectric, spin-on-glass, or flowable CVD oxide, and the second dielectric layer comprises a high density plasma (HDP) oxide and/or silicon nitride.
FIG. 10 is a semiconductor structure in accordance with alternative embodiments of the present invention including a transistor. Semiconductor structure 400 includes a semiconductor substrate 402 and transistor 420 disposed on the semiconductor substrate 402. The transistor 420 includes a gate stack 424 and source/drain region 422 a-b including stressor material 450. The gate stack 424 includes a gate 430 over a gate dielectric 432, such as silicon oxide, hafnium oxide, or zirconium oxide, and spacers 434 a and 434 b at each side of the gate 430 and gate dielectric 432. In embodiments, the spacers can include a nitride or oxide such as silicon nitride or silicon oxide. A shallow trench isolation structure is disposed adjacent to the source/drain region 422 a. The shallow trench isolation structure includes a cavity 404 formed in the semiconductor substrate 402, the STI cavity 404 comprising an upper region 411 and a lower region 413. The upper region comprises a sigma cavity 408, and the lower region 413 comprises a substantially rectangular cavity 412. A first dielectric layer 414 is disposed in the lower region 413, and a second dielectric layer 416 is disposed in the upper region 411, and is planar with a top surface of the substrate 402. In embodiments, the source/drain region 422 a-b further includes a compressive stress material and the second dielectric layer 416 includes a compressive stress material. In other embodiments, the source/drain regions 422 a-b further include a tensile stress material and the second dielectric layer 416 includes a compressive stress material. In still other embodiments, the source/drain regions 422 a-b further comprise a tensile stress material and the second dielectric layer 416 includes a tensile stress material. In still yet other embodiments, the source/drain region 422 further includes a compressive stress material and the second dielectric layer 416 includes a tensile stress material. Embodiments of the present invention may be used with PFET (p-type field effect transistor) or NFET (n-type field effect transistor) devices. For a PFET device, stressor material 450 may be comprised of silicon germanium for compressive stress. For an NFET device, stressor material 450 may be comprised of silicon phosphorus, silicon carbon, or silicon carbon phosphorus for tensile stress. In embodiments, the upper fill material (second dielectric layer 416) and stressor material 450 may be of similar or opposite stress types (tensile or compressive). This allows tuning of the channel stress to accommodate design flexibility.
FIG. 11 is a flowchart indicating process steps for embodiments of the present invention. At 502, a first etch in a semiconductor substrate is performed to form a cavity. The etch may be an anisotropic etch such as a reactive ion etch (RIE). At 504, a sigma etch is performed on the cavity to form an upper region of the cavity. The etch may be performed with a wet etch process utilizing, e.g., tetramethylammonium hydroxide (TMAH), ammoniumhydroxide, and/or potassium hydroxide (KOH). At 506, a second reactive ion etch is performed to form a lower region of the cavity with desired depth. The etch may be an anisotropic etch such as a reactive ion etch. At 508, the lower region of the cavity is filled with a first dielectric material. The filling may be achieved by chemical vapor deposition. The first material may be spin-on-dielectric, spin-on glass, and/or flowable oxide. At 510, the first material is recessed. The recessing may be achieved by chemical mechanical planarizing (CMP) first and followed by reactive ion etching (RIE) or selective wet etch process. At 512, the upper region of the cavity is filled with a second material. This filling may be performed by various CVD methods. The second material may be HDP oxide or SiN for stronger residual stress. At 514, the second material may be planarized to a level flush with a top surface of the semiconductor substrate. The planarization may be achieved by chemical mechanical polish (CMP).
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Moreover, in particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.

Claims (19)

What is claimed is:
1. A semiconductor structure, comprising:
a semiconductor substrate;
a cavity formed in the semiconductor substrate, the cavity comprising a sigma cavity in an upper region, and a lower region, wherein the lower region comprises a substantially rectangular cavity;
a first dielectric layer disposed in the lower region;
a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate;
a third dielectric layer disposed below the first dielectric layer; and
at least one additional dielectric layer disposed below the third dielectric layer.
2. The semiconductor structure of claim 1, wherein the first dielectric layer comprises at least one of a spin-on dielectric, spin-on glass, or flowable chemical vapor deposition (CVD) oxide.
3. The semiconductor structure of claim 1, wherein the second dielectric layer comprises high density plasma oxide.
4. The semiconductor structure of claim 1, wherein the second dielectric layer comprises silicon nitride.
5. The semiconductor structure of claim 1, wherein:
the first dielectric layer comprises a CVD oxide;
the second dielectric layer comprises a high density plasma (HDP) oxide or high-aspect-ratio process (HARP) oxide; and
the third dielectric layer comprises at least one of a spin-on dielectric, spin-on glass, and a flowable CVD oxide.
6. The semiconductor structure of claim 1, wherein the sigma cavity comprises a tip that is disposed at a distance below the top surface of the semiconductor substrate ranging from about 6 nanometers to about 8 nanometers.
7. The semiconductor structure of claim 6, wherein the cavity has a depth ranging from about 100 nanometers to about 300 nanometers.
8. A semiconductor structure, comprising:
a semiconductor substrate;
a transistor disposed on the semiconductor substrate, the transistor comprising a source/drain region and a gate;
a shallow trench isolation structure disposed adjacent to the source/drain region, the shallow trench isolation structure comprising:
a cavity formed in the semiconductor substrate, the cavity comprising a sigma cavity in an upper region, and a lower region, wherein the lower region comprises a substantially rectangular cavity;
a first dielectric layer disposed in the lower region;
a second dielectric layer disposed in the upper region, wherein the second dielectric layer is planar with a top surface of the semiconductor substrate;
a third dielectric layer disposed below the first dielectric layer; and
at least one additional dielectric layer disposed below the third dielectric layer.
9. The semiconductor structure of claim 8, wherein the first dielectric layer comprises at least one of a spin-on dielectric, spin-on glass, and a flowable oxide.
10. The semiconductor structure of claim 8, wherein the second dielectric layer comprises at least one of a high density plasma oxide and a high-aspect-ratio process (HARP) oxide.
11. The semiconductor structure of claim 8, wherein the second dielectric layer comprises silicon nitride.
12. The semiconductor structure of claim 8, wherein:
the first dielectric layer comprises a chemical vapor deposition (CVD) oxide;
the second dielectric layer comprises at least one of a high density plasma (HDP) oxide and a high-aspect-ratio process (HARP) oxide; and
the third dielectric layer comprises at least one of a spin-on dielectric, spin-on glass, and a flowable oxide.
13. The semiconductor structure of claim 8, wherein:
the source/drain region further comprises a compressive stress material; and
the second dielectric layer comprises a compressive stress material.
14. The semiconductor structure of claim 8, wherein:
the source/drain region further comprises a tensile stress material; and
the second dielectric layer comprises a compressive stress material.
15. The semiconductor structure of claim 8, wherein:
the source/drain region further comprises a tensile stress material; and
the second dielectric layer comprises a tensile stress material.
16. The semiconductor structure of claim 8, wherein:
the source/drain region further comprises a compressive stress material; and
the second dielectric layer comprises a tensile stress material.
17. A method of making a semiconductor structure, comprising:
performing a first anisotropic etch in a semiconductor substrate to form a cavity;
performing an etch on the cavity to form a cavity formed in the semiconductor substrate, the cavity comprising an upper region of the cavity;
performing a second anisotropic etch to form a lower region of the cavity;
filling the lower region of the cavity with a first material;
filling the upper region of the cavity with a second material; and
planarizing the second material to a level flush with a top surface of the semiconductor substrate.
18. The method of claim 17, wherein performing a sigma etch comprises performing an etch using tetramethylammonium hydroxide.
19. The method of claim 17, wherein:
filling the lower region of the cavity with a first material comprises filling the lower region with at least one of a spin-on glass, spin-on dielectric, and a flowable oxide; and
filling the upper region of the cavity with a second material comprises filling the upper region of the cavity with at least one of a high density plasma oxide and a high-aspect-ratio process (HARP) oxide.
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