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Patente

VeröffentlichungsnummerUSD403334 S
PublikationstypErteilung
Anmeldenummer29/082,713
Veröffentlichungsdatum29. Dez. 1998
Eingetragen27. Jan. 1998
Veröffentlichungsnummer082713, 29082713, US D403334 S, US D403334S, US-S-D403334, USD403334 S, USD403334S
ErfinderJose Luis Gonzalez, David Bruce Jordan, Andrew William Tudhope
Ursprünglich BevollmächtigterSemiconductor Equipment Technology, Inc
Externe Links: USPTO, USPTO-Zuordnung, Espacenet
Shield and cover for target of sputter coating apparatus
US D403334 S
Bilder(4)
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Ansprüche
  1. The ornamental design for a shield and cover for target of sputter coating apparatus, as shown and described.
Beschreibung

FIG. 1 is a perspective view of a shield and cover for target of sputter coating apparatus embodying the design of the invention;

FIG. 2 is a top plan view of the shield and cover for target of sputter coating apparatus of FIG. 1;

FIG. 3 is a bottom plan view of the shield and cover for target of sputter coating apparatus of FIG. 1;

FIG. 4 is a side elevation view of the shield and cover for target of sputter coating apparatus as seen from the bottom of FIG. 2;

FIG. 5 is a side elevation view of the shield and cover for target of sputter coating apparatus as seen from the top of FIG. 2;

FIG. 6 is a side elevation view of the shield and cover for target of sputter coating apparatus as seen from the left side of FIG. 2;

FIG. 7 is a side elevation view of the shield and cover for target of sputter coating apparatus as seen from the right side of FIG. 2;

FIG. 8 is a cross-sectional view of the shield and cover for target of sputter coating apparatus taken along the line 8--8 of FIG. 2; and,

FIG. 9 is a cross-sectional view of the shield and cover for target of sputter coating apparatus taken along the line 9--9 of FIG. 2.

Referenziert von
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US709774412. Juni 200329. Aug. 2006Applied Materials, Inc.Method and apparatus for controlling darkspace gap in a chamber
US7952373 *23. Okt. 200631. Mai 2011Verigy (Singapore) Pte. Ltd.Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
Klassifizierungen
US-KlassifikationD15/138