USRE26780E - Electronic diode matrix decoder circuits - Google Patents

Description

7% 7}? h 74 b e :3 $21 3 D 84 90 I g I Feb. 3, 1970 J. J. KLINIKOWSKI Re. 26,780

ELECTRONIC DIODE MATRIX DECODER CIRCUITS Original Filed March 23, 1964 170 3? wi rs y 25' C (I80 E b INVENTOR. JAMES J. KL! Nl KOWSKI A T TOR/V5 V United States Patent 26,780 ELECTRONIC DIODE MATRIX DECODER CIRCUITS James J. Klinikowski, Lehigh County, Pa., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Original No. 3,309,695, dated Mar. 14, 1967, Ser. No. 353,845, Mar. 23, 1964. Application for reissue Mar. 12, 1969, Ser. No. 806,747

Int. Cl. G06f /00 U.S. Cl. 340347 7 Claims Matter enclosed in heavy brackets appears In the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE A signal decoder circuit including five pairs of display switching devices coupled to decimal numerical display means and two control switching devices, each of which controls the operation of five of the display switching devices. Binary-coded decimal signal bits are coupled through an array of AND gates and a diode matrix to the display switching devices and to the control switching devices. The circuit processes each combination of input signal bits and causes one control switching device to select and operate one display switching device which operates the decimal display means corresponding to the particular combination of signal bits.

This invention relates to electronic decoder circuits and, particularly to a diode matrix decoder circuit usable to convert several ditferent binary codes to decimal code.

Electronic decoder circuits using diode matrices are known for converting binary-coded decimal signals to pure decimal signals. However, none of these circuits is what may be termed a universal" circuit, that is, these circuits cannot be used to decode signals of more than one code system Without relatively elaborate modification of the diode matrix and associated circuitry for each code system.

Accordingly, the objects of the present invention are directed toward the provision of an improved electronic decoder circuit using a relatively simple diode matrix and adaptable to decode signals in several different code systems without modification of the diode matrix.

A circuit embodying the invention is particularly useful for decoding biquinary code systems and includes, in brief, five pairs of transistors connected together in biquinary fashion, that is, in two groups of five, with one transistor of each pair connected in a group. In addition, a separate auxiliary control transistor is provided to control the operation of each group of five transistors. All of the transistors, including the control transistors, are coupled to a diode matrix in which the diodes are interconnected to provide a plurality of AND gates. A plurality of input terminals are coupled to the AND gates and the signal bits of various binary-coded signals are adapted to be coupled in proper order to selected ones of these terminals so that the proper decimal output is provided for each code input.

In the drawing, the single figure is a schematic representation of a decoder circuit embodying the invention.

A circuit 10 embodying the invention includes five pairs of transistors including the pairs and 20', 21 and 21', 22 and 22', 23 and 23', 24 and 24'. In addition, the circuit includes a pair of control transistors 25 and 25'. Each transistor includes base, emitter, and collector electrodes b, e, and c, respectively. The control transistor 25 has its output or collector electrode coupled through lead ice 30 to the emitter electrode of one transistor of each pair, for example, transistors 20 to 24. Similarly, the collector or output electrode of control transistor 25 is coupled by lead 34 to the emitter electrode of each of the other transistors of each pair.

The collector or output electrode of each transistor 20 to 24 and 20' to 24 is connected to one of the glow cathodes 38 of a multi-cathode glow tube 40 such as the type 6844A tube to provide a visible display of the decimal output of the circuit 10. In the circuit shown, and for 842-1 code to be described, the collectors of transistors 24 and 24' are connected to the cathode numerals 0 and 1, respectively; the collectors of transistors 23 and 23' are connected to the cathode numerals 2 and 3, respectively; the collector electrodes of transistors 22 and 22 are connected to cathode numerals 6 and 7, respectively; the collector electrodes of transistors 21 and 21' are connected to cathode numerals 4" and 5, respectively; and the collector electrodes of transistors 20 and 20' are connected to cathode numerals 8 and 9, respectively.

The emitter electrodes of control transistors 25 and 25' are coupled together and through a suitable resistor to a power source V2 such that the emitters of these transistors are at a potential between logical 1 and logical 0, as defined below.

The tube 40 also includes an anode electrode which is coupled through a resistor 62 to a positive DC. power source V1.

A diode matrix decoding network, embodying the invention, for converting binary-coded decimal information to pure decimal information is coupled to the pairs of transistors to perform the required conversion or decoding operation. The decoding circuit includes a first diode 70, oriented as shown and having its anode coupled through lead 74 to the base electrodes of transistors 20 and 20. The cathode of diode is provided with an input terminal 78. Diodes 84 and 88 comprise a two-part AND gate and have their anodes connected through lead 90 to the base electrodes of transistors 21 and 21'. Diodes 94 and 98 comprise a two-part AND gate and have their anodes connected through lead 102 to the base electrodes of transistors 22 and 22. The cathodes of diodes 88 and 94 are connected together by lead 108 to form a sub-pair of diodes, and lead 108 is provided with an input terminal 110. Diodes 112 and 118 comprise another twopart AND gate and have their anodes connected through lead 120 to the base electrodes of transistors 23 and 23'. The cathodes of diodes 98 and 112 are connected together by a lead 128 to form a sub-pair of diodes, and lead 128 is provided with an input terminal 130.

The circuit also includes three diodes 134, 135, and 136 which comprise a three-part AND gate and have their anodes coupled through lead 140 to the base electrodes of transistors 24 and 24'. The cathodes of diodes 118 and 134 are connected together by a lead 148 to form a subpair of diodes, and the lead 148 is provided with an input terminal 150. The cathode of diode 84 is coupled to the cathode of diode by lead 154 to form another subpair of diodes, and lead 154 is provided with an input terminal 160. The cathode of diode 136 is provided with an input terminal 170. A single diode 174 has its anode coupled by lead 178 to the base electrode of transistor 25, and its cathode is provided with an input terminal 180. Finally, a single diode 184 has its anode coupled by lead 188 to the base electrode of control transistor 25, and its cathode is provided with an input terminal 190.

It can be seen that the diode matrix includes eight input lines coupled to the cathodes of the diodes and seven output lines coupled between the anodes of the diodes and the transistors.

The positive DC. power source V1 is coupled through lead 200 and a separate resistor 204 to each of the matrix output lines 74, 90, 102, 140, 178, and 188.

The decoder circuit 10 can be used to convert at least five different binary-coded decimal codes to pure decimal signals. These codes include that 842l code, cyclic 20 Gray code, Watts code, the 24-21 code, and the 5-4-2-1 code. The truth table for each of these codes is shown below. Each truth table shows the various combinations of code signals and the decimal equivalent for each.

S I 4 i 2 1 Decimal number Code hits (I (I (I (I O (l t l] U 1 1 (I (I 1 (I .1 (I (I 1 1 3 (l 1 l) I) 4 I) 1 (l 1 5 (l 1 1 t) t) I) 1 1 1 7 1 l) U I) 8 1 o 1 9 Cyclic 30 (l ray Decimal G4 (i3 L22 Lil number (ode bits l 1 i n 1 0 0 1 I 1 1 n 1 I 1 1 1 .2 1 1 U 1 3 l I I) U 4 l) 1 t) 0 I) 1 t) l [l 0 1 1 1 T l) l 1 I) S l) U l O J Watts Decimal (-4 U3 G2 G1 umubcr Code bits I) 0 0 0 l) t) O 0 1 1 D I) 1 1 .2 0 I) 1 0 d t) 1 1 I) 4 1 1 1 I) 5 1 [I 1 0 l1 1 t) 1 1 7 1 0 0 1 S 1 l) l) l) i) Decimal number Code bits 4 t] O 0 0 (l (J (I (I l 1 1 0 0 (I A 1 (I (I l d l (I l (l 4 1 0 1 1 5 1 1 (l (I (1 1 1 I) 1 7 1 1 1 (I 8 1 1 1 1 J Decimal number In order to utilize the circuit 10 convert the 842l code to pure decimal, the signal bits of the 8-4-2-1 binary-coded decimal signal are connected to the input terminals as follows:

the? bit is coupled to the terminal 190 the 2 bit is coupled to the terminal 180 the F bit is coupled to the terminal 170 the 2 bit is coupled to the terminal 160 the 2 bit is coupled to the terminal 150 the 2 bit is coupled to the terminal 130 the 2 bit is coupled to the terminal the 2 bit is coupled to the terminal 78 It is understood that 2 is the complement of 2 and 2 is complement of 2 etc. In addition, logical 0 in the truth table represents a negative voltage, for example, 6 volts, and logical 1 represents a more positive voltage, for example, zero volts.

In the circuit 10, a current flow path is provided from the positive DC. power source V1 through each of the resistors 204 and through each of the matrix output lines 74, 90, 102, 120, 140, 178, and 188 and through one of the transistors of each pair, depending on the state of the control transistors 25 and 25'. The presence or absence of each current flow in any of these seven matrix output lines is determined by th potential applied to the line by the combination of input signals appearing at the input to the diode matrix, If a negative potential appears on a matrix output line, then no current flows through it or either of the transitors to which it is connected. If a more positive potential appears on the line, then current can flow through this lead and through one of the transistors of the pair of transistors to which it is connected.

Assuming that the group of binary-coded decimal signal bits is applied representing decimal 0, then the 8, 4, 2, and 1 bits are logical zero which is 6 volts and their complements are logical 1 which is zero volts. This combination of signal bits turns on control transistor 25. The other signal bits applied through the diode matrix product current flow only in line 140, and this current turns on transistor 24 which in turn energizes cathode numeral 0 in tube 40.

The other combinations of signal bits in the 8-4-2-1 truth table, when applied to the input of the diode matrix, cause current to flow in one matrix output line. This one matrix output line energizes the transistor coupled to the glow cathode numeral representing the correct decimal number corresponding to the applied combination of signal bits.

In order to use the circuit 10 to perform the same decoding operation for the other codes, it is only necessary to (1) connect the signal bits to the pro-per input terminals and (2) connect the collector electrodes of the transistor pairs to the correct cathode electrodes in the indicator tube 40.

The following tables show the codes and the arrangement of their connections to the input terminals and the are many codes which satisfy these requirements and can be decoded by the circuit 10.

corresponding connections of the collectors of the transistors.

What is claimed is: 1. A decoder circuit including Input 5 4 2 1 Transistor Cathode five pairs of transistors and a pair of auxiliary transis- Tel'mml Numeral 5 tors, each of which is coupled to and controls the operation of one transistor of each pair of transistors, 78 4 9 a diode matrix 110 2 20' 4 t 130 1 21 7 eight input lines to said diode matrix, 150 2 10 seven output lines from said diode matrix coupled to 150 22 8 said transistors, and g3 g 33' 3 said diode matrix including a two-diode AND gate in 190 g 1 three of said seven lines, a three-diode AND gate in 3: 3 one of said lines, and a single diode in each of the remaining lines including the two lines coupled to said auxiliary transistors, there thus being four AND gates, Input watts Transistor cathoda each [one] diode of each two-diode AND gate being Terminal Bit Numeral connected to one diode of one other AND gate to form diode sub-pairs, rs 9 20 5 two diodes of said three-diode AND gate being congg g? f nected to diodes in separate two-diode AND gates, 150 b one diode of said three-diode AND gate thus not being 160 E 22 a connected to any other AND gate, 170 E 22' 1 25 a signal input terminal coupled to each of said sub- 133 g: :3, 2 pairs of diodes and to the one diode in said three- 24 6 diode AND gate not connected to any other AND 3 gate and to each 0 the single diodes coupled to said auxiliary transistors [two AND gates which are not 3 connected to diodes in other AND gates], I t 2 4 2,1 T H C th d said input terminals :being adapted to receive different 133 13 g g g combinations of signal bits in one code and providing current flow on one output line from the diode 78 3 20 1 matrix to one of said pairs of transistors and mom 110 4 0 of said auxiliary transistors whereby one transistor 130 1. 21 7 of one of said pairs of transistors is turned on and :23 2; 3 provides an output signal having a meaning in an- 170 2 22 8 other COdC. 133 1 g, 2 2. A decoder circuit including 24 3 40 five pairs of transistors and a pair of auxiliary transis- 2 tors, each of which is coupled to and controls the operation of one transistor of each pair of transistors, a diode matrix, Input- Cyclie 20 Transistor Cathode eight input line.s to Said diofie m Terminal Gray bit Numeral seven output lines from said diode matrix with five lines of said seven lines coupled one to each of said 78 7 20 9 five pairs of transistors and one line coupled to each 110 E2 0 of said auxiliary transistors, and 8 8; 3%, 2 said diode matrix including a two-diode AND gate in 160 E1 22 6 three of said seven lines, a three-diode AND gate 170 G 22' 3 in one of said lines, and a single diode in each of 180 '6 2s 7 the remaining lines including the two lines coupled 190 2 to said auxiliary transistors 24 8 r 24' 1 there thus being four AND gates,

each [one] diode of each twodiode AND gate being connected to one diode of one other AND gate to From the foregoing description, it can be seen that the diode :p circuit of the invention can be used to convert many two dlodes said i d AND gate being conbinary-coded decimal codes to pure decimal code. It is nected to diodes Separale t -di de AND gates, noted that each such code which can be decoded has a one diode of said threediode AND gate thus not being biquinary characteristic which means that the truth table Q f to y other AND gate, for the code includes one column of bits containing five a Slgnal Input terminal collpledfo F slib-Palrs logical zeroes and five logical ones. This column of sigof dlodes and to the one dlodfi Sald "Wee-diode nal bits is called the separator or control column and is AND gate not P' f to 0th?" 8" f used to operate the auxiliary transistors. In addition, to each f the single diode-Y Coupled Said an examination of the other rows and columns of bits "animal's AND gaifis Whlch are not connectfid shows that the rows of bits can be grouped into five filodes f gates], pairs of identical rows of bits with one member of a pair 531d npi t t rminals being ad apted to receive different being associated with a logical zero in the separator combmatlms of Slgnalblisln code and pfovlfimg column and the other member of the pair being assocurl-6.1 flow on p P P 11m f the diode ciated with a logical zero and one associated with a one matr x to one of 581d Pairs of tfanslslol's andfo one in the Separator Column Those Skilled in the art il of said auxiliary transistors whereby one transistor of understand that this type of code produces a two-layer one of Said Pairs of transistors is turned on and Veitch diagram which includes four signals in one layer Pr vides an output signal having a meaning in anand one signal in the other. Thus, it appears that there other code.

3. A decoder circuit including five pairs of transistors and a pair of auxiliary transistors, each of which is coupled to and controls the operation of one transistor of each pair of transistors,

a diode matrix,

eight input lines to said diode matrix,

seven output lines from said diode matrix and coupled to said transistors,

three [two] two-diode AND gates coupled by their anodes to three of said output lines,

a three-diode AND gate coupled by the anode of each of its diodes to one of said output lines,

each [one] diode of. each of said two-diode [two] AND gates being coupled by its cathode to the cathode of another diode in one other of said [two] AND gates to form diode sub-pairs, one diode of said three-diode AND gate being not connected to another diode,

a signal input terminal coupled to the joined cathodes of each diode sub-pair and to said one diode of said three-diode AND gate,

[a three-diode AND gate coupled by the anode of each of its diodes to one of said output lines,]

[two of the diodes of said three-diode AND gate being coupled by their cathodes to the cathodes of one diode in each of said two-diode AND gates to form two additional diode sub-pairs with an input terminal coupled to the joined cathodes of said two additional diode sub-pairs,]

and single diodes coupled by their anodes to three of said output lines with an input terminal connected to the cathode of each of said single diodes,

two of said single diodes being coupled to said auxiliary transistors,

said input terminals being adapted to receive different combinations of signal bits in one code and providing current flow on one output line from the diode matrix to one of said pairs of transistors and to one of said auxiliary transistors whereby one transistor of one of said pairs of transistors is turned on and provides an output signal having a meaning in another code.

4. The circuit defined in claim 3 and including a decimal display device coupled to said pairs of transistors to provide a visual display of the output signal which results L from a signal decoding operation.

5. A circuit for use in decoding biquinaiy code signals comprising five pairs of decimal-representing transistors,

two auxiliary control transistors, each coupled to and controlling the operation of one transistor of each pair of transistors,

a diode matrix,

eight input lines to said diode matrix,

seven output lines from said diode matrix,

said diode matrix including single diodes in three of said output lines,

three two-diode AND gates in three of said output lines,

and one three-diode AND gate in one of said output lines,

said input lines being adapted to receive different combinations of signal bits in one code and providing current flow on one output line from the diode matrix to one of said pairs of transistors and to one of said auxiliary transistors whereby one transistor of one of said pairs of transistors is turned on and provides an output signal having a meaning in decimal code.

6. A decoder circuit including five pairs of semiconductor switching devices and a pair of auxiliary semiconductor switching devices, each of which. is coupled to and controls the operation of one device of each pair of devices,

a diode matrix,

eight input lines to said diode matrix,

seven output lines from said diode matrix coupled to said devices, and

said diode matrix including a two-diode AND gate in three of said seven lines, a three-diode AND gate in one of said lines, and a single diode in each of the remaining lines including the two lines coupled to said auxiliary devices,

there thus being four AND gates,

each diode of each two-diode AND gate being connected to one diode of one other AND gate to form diode sub-pairs,

two diodes of said three-diode AND gate being connected to diodes in separate two-diode AND gates,

one diode of said three-diode AND gate thus not being connected to any other AND gate,

a signal input terminal coupled to each of said subpairs of diodes and to the one diode in said threediode AND gate not connected to any other AND gate and to each of the single diodes coupled to said auxiliary devices,

said input terminals being adapted to receive difierent combinations of signal bits in one code and providing current flow on one output line from the diode matrix to one of said pairs of devices and to one of said auxiliary devices whereby one device of one of said pairs of devices is turned on and provides an output signal having a meaning in another code.

7. A decoder circuit including first, second, third, fourth, and fifth pairs of semiconductor switching devices, each having an input electrode and an output electrode,

two auxiliary control semiconductor switching devices having input and output electrodes and each coupled to and controlling the operation of one device in each pair of devices,

a first input terminal connected through a first diode and a first input line to the input electrodes of said first pair of devices,

a second input terminal coupled through a second diode and a second input line to the input electrodes of said second pair of devices, said second input terminal also being coupled through a third diode and a third input line to the input electrodes of said third pair of devices,

a third input terminal coupled through a fourth diode and said third input line to the input electrodes of said third pair of devices, said third input terminal also being coupled through a fifth diode and a fourth input line to the input electrodes of said fourth pair of devices,

a fourth input terminal coupled through a sixth diode and said fourth input line to said fourth pair of devices, said fourth input terminal also being coupled through a seventh diode and a fifth input line to said fifth pair of devices,

a fifth input terminal coupled through an eighth diode and said second input line to said second pair of devices, said fifth input terminal also being coupled through a ninth diode and said fifth input line to said fifth pair of devices,

a sixth input terminal coupled through a tenth diode and said fifth input line to said fifth pair of devices,

a seventh input terminal coupled through an eleventh diode to the input of one of said auxiliary devices, and

an eighth input terminal coupled through a twelfth diode and a seventh input line to the input of the other auxiliary control device,

said input terminals being adapted to receive difierent combinations of signal bits in one code and providing current flow on one output line from the diode matrix to one of said pairs of devices and to one of said auxiliary devices whereby one device of one of said pairs of devices is turned on and provides an output signal having a meaning in another code.

References Cited The following references, cited by the Examiner, are 5 10 UNITED STATES PATENTS 3,086,198 4/1963 Tate 340-347 MAYNARD R. WILBUR, Primary Examiner I. GLASSMAN, Assistant Examiner

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