USRE36613E - Multi-chip stacked devices - Google Patents
Multi-chip stacked devices Download PDFInfo
- Publication number
- USRE36613E USRE36613E US08/610,127 US61012796A USRE36613E US RE36613 E USRE36613 E US RE36613E US 61012796 A US61012796 A US 61012796A US RE36613 E USRE36613 E US RE36613E
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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Definitions
- This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.
- Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the from of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads.
- IC integrated circuit
- the bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire.
- a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip.
- a trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
- IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inches. A method of increasing density is to stack die or chips vertically.
- An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer.
- the lower, slightly larger die is face-bonded to the lower surface of the lead extensions with the lower lead-frame die-bonding region via a second, adhesively coated, film layer.
- the wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires.
- the lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
- a Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
- method 3 one chip attached above and one chip attached below a common paddle.
- a controlled, first, thin-adhesive layer affixing a first die above the paddle
- a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame frame lead fingers;
- a second thin-adhesive layer affixing a second die above the first die
- FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention.
- FIG. 2 is a side elevation taken through 2--2 of FIG. 1 showing a four die stacking.
- the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted the paddle 14 and other dies 16, 18, and 20 (FIG. 2) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22. Thermoplastic indicating the adhesive sets at an elevated temperature. The group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24.
- Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal.
- the critical bonding method used at the die end pad 26 is ultrasonic ball bond as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.
- the other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28.
- the wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface.
- the lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.
- Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42.
- the stack is finally encapsulated by a plastic or ceramic at 44.
- FIG. 2 A dimensional analysis is provided by referring to FIG. 2.
- the encapsulation thickness 48 is between 0.010 and 0.012 inches.
- the paddle 74 thickness 50 can be between 0.005 and 0.010 inches and is a matter of choice.
- the controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches.
- the individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inches nd the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inches.
- the top encapsulation 58 is between 0.010 and 0.012 inches so as to cover the top loop.
- the height at 60 would be between 0.058 and 0.073 inches and for a three-die stack it would be from 0.078 to 0.100 inches.
- the die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel.
- the final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
- SOJ small outline J-leaded
- DIP dual in-line package
- SIP single in-line package
- PLCC plastic leaded chip carrier
- ZIP zig-zag in-line package
Abstract
Description
Claims (7)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US08/610,127 USRE36613E (en) | 1993-04-06 | 1996-02-29 | Multi-chip stacked devices |
US10/346,860 USRE40061E1 (en) | 1993-04-06 | 2003-01-16 | Multi-chip stacked devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/043,503 US5291061A (en) | 1993-04-06 | 1993-04-06 | Multi-chip stacked devices |
US08/610,127 USRE36613E (en) | 1993-04-06 | 1996-02-29 | Multi-chip stacked devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/043,503 Reissue US5291061A (en) | 1993-04-06 | 1993-04-06 | Multi-chip stacked devices |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US42712399A Continuation | 1993-04-06 | 1999-10-21 |
Publications (1)
Publication Number | Publication Date |
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USRE36613E true USRE36613E (en) | 2000-03-14 |
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Application Number | Title | Priority Date | Filing Date |
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US08/043,503 Ceased US5291061A (en) | 1993-04-06 | 1993-04-06 | Multi-chip stacked devices |
US08/610,127 Expired - Lifetime USRE36613E (en) | 1993-04-06 | 1996-02-29 | Multi-chip stacked devices |
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US08/043,503 Ceased US5291061A (en) | 1993-04-06 | 1993-04-06 | Multi-chip stacked devices |
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US (2) | US5291061A (en) |
Cited By (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6229202B1 (en) * | 2000-01-10 | 2001-05-08 | Micron Technology, Inc. | Semiconductor package having downset leadframe for reducing package bow |
US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
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