USRE36916E - Apparatus for stacking semiconductor chips - Google Patents
Apparatus for stacking semiconductor chips Download PDFInfo
- Publication number
- USRE36916E USRE36916E US09/064,348 US6434898A USRE36916E US RE36916 E USRE36916 E US RE36916E US 6434898 A US6434898 A US 6434898A US RE36916 E USRE36916 E US RE36916E
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- US
- United States
- Prior art keywords
- chip
- surface mount
- module
- circuit board
- chips
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- Expired - Lifetime
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/023—Stackable modules
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to the vertical stacking of conventional integrated circuit packages to increase the density of components on a printed circuit board. More particularly, the present invention relates to the vertical stacking of conventional memory integrated circuits packages on a surface mount printed circuit board.
- An integrated circuit or "IC” is a microcircuit formed from active and passive electrical components interconnected on or within a single semiconductor substrate. To protect the IC and to facilitate connection of the IC to a printed circuit board, off-the-shelf ICs are commonly packaged within a ceramic, plastic or epoxy IC package having multiple external terminals or "pins.” The full integrated circuit package, including the IC, is commonly referred to (and will be referred to herein) as a "chip.”
- the present invention involves a multi-chip memory module having two or more vertically stacked memory chips that are interconnected using a pair of printed circuit boards or "side boards.”
- the multi-chip memory module can be constructed using standard, off-the-shelf memory chips, without modification to the pins of the memory chips.
- the multi-chip memory module is constructed such that pins of the lower-most memory chip in the stack are surface-mountable directly to pads of a memory board, permitting the multi-chip memory module to be mounted with a low profile relative to the memory board.
- the multi-chip memory module comprises a plurality of memory chips that are stacked on top of one another, with each memory chip having conductive surface mount pins.
- First and second side boards are mounted to the stacked memory chips such that the side boards are substantially parallel to one another.
- Each of the two side boards has vias for receiving the surface mount pins of the memory chips, with the vias arranged in rows such that each row corresponds to a respective memory chip. Vias of a bottom-most row of each side board fall along a lower side board edge, so that vias of the bottom-most row serve as surface mount terminals for surface mounting the multi-chip memory module to pads of a printed circuit board.
- Conductive traces are provided on or within each side board for interconnecting the surface mount pins of the memory chips.
- a memory module that includes at least one multi-chip module.
- the memory module includes a circuit board having at least first and second sets of surface mount pads.
- the memory module further includes a first side board that is surface-mounted to the first set of surface mount pads such that the first side board is substantially perpendicular to the circuit board, and a second side board that is surface-mounted to the second set of surface mount pads such that the second side board is substantially perpendicular to the circuit board and substantially parallel to the first side board.
- the memory module further includes a plurality of chips stacked on top of one another between the side boards, with each chip conductively connected to the first and second side boards.
- a method of increasing the density of memory chips on a memory board includes the step of providing first and second side boards, with each side board comprising a printed circuit board having vias thereon, and with vias along bottom edges of the side boards forming surface mount terminals.
- the method further includes the step of stacking a plurality of memory chips on top of one another to generate a stack of memory chips.
- the method further includes the steps of positioning the first and second side boards relative to the stack of memory chips such that terminals of the memory chips extend within the vias, and attaching the first and second side boards to the stack of memory chips by filling the vias with solder.
- a method of interconnecting circuit board components to increase component density includes the step of constructing a first printed circuit board that has a plurality of vias formed along a row. The method further includes the step of cutting the first printed circuit board along the row to expose the vias along an edge of the printed circuit board. The method further includes the steps of soldering the vias to respective pins of a semiconductor chip, and soldering the vias to pads of a second printed circuit board such that the first printed circuit board is substantially perpendicular to the second printed circuit board.
- FIG. 1 is a perspective view illustrating a multi-chip memory module in accordance with a preferred embodiment of the present invention, illustrated above a portion of a printed circuit board to which the multi-chip memory module may be surface mounted. Solder plugs and circuit board traces are omitted to show the construction of the multi-chip memory module;
- FIG. 2 is an exploded perspective view of the multi-chip memory module of FIG. 1;
- FIG. 3 is a top plan view of the multi-chip memory module of FIG. 1, with terminal numbers for the multi-chip memory module shown in brackets;
- FIG. 4 is a cross sectional view taken along the line 4--4 of FIG. 1;
- FIGS. 5a and 5b are top and bottom plan views of a portion of a circuit board panel, illustrating a process of manufacturing side boards in accordance with the present invention, and further illustrating conductive traces on first and second sides of the side boards of FIG 1;
- FIG. 6a is an enlarged view in partial cross section, showing a bottom portion of a side board of the multi-chip memory module of FIG. 1 with partially cut-away vias filled with solder to form surface mount terminals, and further showing the printed circuit board and pads of FIG. 1;
- FIG. 6b is an enlarged view in partial cross section of a side board and a printed circuit board with pads, illustrating an alternative configuration that results when conductive cylinders of vias are pushed inward during a routing process;
- FIG. 7 is a schematic diagram illustrating the electrical interconnections of memory chip pins and side board terminals for the multi-chip memory module of FIG. 1, with chip pin numbers shown in parenthesis and multi-chip memory module terminal numbers shown in brackets; and
- FIG. 8 is a plan view of a single in-line memory module having eight multi-chip memory modules surface mounted to one side thereof.
- one multi-chip memory module design is described herein.
- various embodiment-specific details are set forth, such as the number of memory chips in the module, the layouts of the printed circuit boards of the module, and the capacity, number of data bits and pin-outs of the memory chips. It should be understood, however, that these details are provided only to illustrate this single preferred embodiment, and are not intended to limit the scope of the present invention.
- a 28-terminal multi-chip memory module 30 (hereinafter “multi-chip module”) comprises four functionally-identical, vertically-stacked memory chips 32, 34, 36, 38.
- the memory chips 32-38 are conventional 24-pin surface mount TSOP ("thin small outline package") chips, available from Toshiba, Mitsubishi, and the like. Each memory chip 32-38 has a capacity of 16M ⁇ 1-bit.
- the vertically-stacked memory chips 32-38 are held together and electrically interconnected by a pair of printed circuit boards 42, 44, referred to herein as "side boards.”
- the side boards 42, 44 are positioned in parallel to each other, and perpendicular to the top surfaces of the chips 32-38.
- the multi-chip module 30 is configured to be surface-mounted to a memory board 70 (FIG. 1) that has surface mount pads 66 thereon.
- bottom refers generally to the portion of the multi-chip module 30 that is closest to the memory board 70 when the multi-chip module 30 is mounted to the memory board 70.
- top refers generally to the portion of the multi-chip module 30 that is closest to the memory board 70 when the multi-chip module 30 is mounted to the memory board 70.
- bottom refers generally to the portion of the multi-chip module 30 that is closest to the memory board 70 when the multi-chip module 30 is mounted to the memory board 70.
- top bottom
- lower are not intended to imply a specific spacial orientation of the multi-chip module 30.
- Each side board 42, 44 has a plurality of plated through-holes or "vias" 48 for receiving the pins 50 of the chips 32-38, with each via 48 comprising a conductive tubular cylinder portion 48a that extends through the side board.
- the vias 48 are positioned to form four horizontal rows 52, 54, 56, 58, with each row corresponding to a respective memory chip 32, 34, 36, 38.
- the rows 52-58 of vias are formed such that the distance D between centers of adjacent rows is approximately equal to the thickness T of each chip 32-38, so that adjacent memory chips are touching (or nearly touching) each other when the multi-chip module 30 is assembled.
- Adjacent memory chips could alternatively be spaced apart from one another, as may be desirable in certain applications to facilitate the cooling of the memory chips 32-38.
- the vias of the bottom-most row 58 are partially cut away, with the conductive cylinder 48a of each such via extending to the lower edge 80 of the side board so that the pins 50 of the bottom-most chip 38 can be soldered directly to the surface mount pads 66 (FIG. 1) of the memory board 70.
- the vias 48 along the lower edges 80 of the side boards 42, 44 thus serve as surface mount terminals.
- This aspect of the multi-chip module 30, in combination with the close spacings between adjacent memory chips, allows the multi-chip module 30 to be mounted with a very low profile relative to the memory board 70.
- the lower edge 80 is preferably formed using a routing machine, as further described below.
- the multi-chip module 30 has a total of 28 surface mount terminals (terminal numbers shown in brackets), with the terminals arranged in two rows of 14 terminals each.
- the surface mount pads 66 are arranged in two rows of 14 pads each (corresponding to the 14 terminals per side board 42, 44), with the distance between the two rows corresponding to the width of each chip 32--38.
- the multi-chip module 30 occupies approximately the same area on the memory board 70 as would a single one of the memory chips 32-38.
- the memory chips 32-38 are interconnected such that all four 16M ⁇ 1-bit chips 32-38 are selected simultaneously, with each chip supplying (or, during a write cycle, storing) one bit of data.
- the multi-chip module 30 thus acts as a 16M ⁇ 4-bit memory module.
- each via 72 provides access to either a data input pin or a data output pin of a respective memory chip 32-38, and is thus dedicated to a single chip. It will be recognized that other types of terminal structures could be used in place of the vias 72.
- the memory chips 32-38 are initially stacked on top of one another.
- the side boards 42, 44 are then positioned so that the pins 50 extend within the corresponding vias, as best shown by FIG. 4.
- no modification to the pins 50 of the standard TSOP memory chips 32-38 is required.
- all of the vias 48 of both side boards 42, 44 are filled with solder (solder plugs omitted in FIGS. 1-4).
- a solder with a relatively high melting point is used for this purpose so that the multi-chip module 30 can subsequently be mounted to the memory board 70 using a solder with a lower melting point without melting the solder within the vias 48.
- FIGS. 5a and 5b illustrate a circuit board panel 90 mid-way through the manufacturing process.
- FIG. 5a illustrates the outward-facing surface (relative to the multi-chip module 30) of the side board 42, and the inward-facing surface of the side board 44.
- FIG. 5b illustrates the inward-facing surface of the side board 42, and the outward-facing surface of the side board 44.
- Traces 92 are initially formed on both sides of the circuit board panel 90 using a conventional film etching process. Via holes are then drilled through the circuit board panel 90, with the holes positioned to correspond to the pin positions of the chips 32-38. A conventional plating process is then used to form the conductive cylinders 48a of the vias 48 (preferably formed from copper), and to interconnect the via cylinders 48a to the appropriate traces 92.
- the panel 90 is routed to form the lower edge 80 and the top edge 81 of each side board 42, 44.
- the panel 90 shown in FIGS. 5a and 5b is mid-way through the routing process, with top and bottom edges 80, 81 formed only for the four side boards 42, 44 closest to the bottom of each Figure.
- the routing bit is preferably passed so that approximately 5% of the diameter of each via cylinder 48a along the bottom row 58 is cut away. Due to imperfections in the routing process, the lower portions of some cylinders may be pushed inward (toward the centers of the respective vias) by the routing bit, as schematically shown at 96 in FIGS. 5a and 5b (and further illustrated in FIG. 6b). Cylinders that are formed in this manner have been found to work well as surface mount terminals, and need not be modified.
- the panel 90 is scored on both sides to form break-away grooves 94.
- the break-away grooves 94 can be formed either before or after the above-described routing process.
- side boards 42, 44 are manually broken away from the panel 90, and soldered to stacks of memory chips (as described above) to form multi-chip modules 30.
- each solder plug 98 is exposed along the bottom edge 80, forming a terminal that can be soldered to a corresponding surface mount pad 66.
- Each solder plug 98 preferably extends slightly below the lower edge 80, facilitating connection of the multi-chip module 30 to the pads 66.
- via cylinders 48a that are pushed inward during the routing process are similarly exposed along the lower edge 80, and are well-suited for connection to the pads 66.
- FIG. 7 illustrates the interconnections the memory chips 32-38 of the multi-chip module 30, and also illustrates the connections between the memory chips 32-38 and the 28 terminals of the multi-chip module 30.
- Signal names for each of the 28 multi-multi-chip module terminals are shown at the left of FIG. 7.
- Terminal numbers for the multi-chip module 30 are shown in brackets in FIG. 7, and correspond to the bracketed terminal numbers of FIG. 3.
- Pin numbers for the chips 32-38 are shown in parenthesis in FIG. 6.
- like address pins (A0-A11), control pins (RAS, CAS and WE), and power pins (VCC and VSS) of the four memory chips 32-38 are connected together, and are connected to respective terminals of the multi-chip module 30.
- the A0 pins (pin 8) of all four memory chips 32-38 are connected together, and are accessed via terminal 10 of the multi-chip module. With like address and control pins connected together, all four chips 32-38 are selected simultaneously, and are fed identical address values.
- the data-input pin (D) of each memory chip 32-38 is connected to a respective dedicated input terminal (D0-D3) of the multi-chip module 30, allowing a 4-bit value to be written to the multi-chip module 30 on each write cycle.
- the data-output pin (Q) of each memory chip 32-38 is connected to a respective dedicated output terminal (Q0-Q3), allowing a 4-bit value to be read from to the multi-chip module 30 on each read cycle.
- the chips 32-38 could alternatively be connected such that fewer than all of the chips are selected with each multi-chip module access.
- a 64M ⁇ 4-bit multi-chip can be constructed from four 16M ⁇ 4-bit memory chips that are interconnected so that only one memory chip is selected at a time.
- the write enable pins and like address, data-in, and data-out pins of all four memory chips would be connected, and the RAS and CAS pins of each chip would be connected to dedicated RAS and CAS input lines (i.e., one pair of RAS/CAS input lines per memory chip).
- FIG. 8 illustrates one side of a 16M ⁇ 36 bit single in-line memory module (SIMM) 100 in accordance with the present invention.
- the SIMM 100 comprises a SIMM board 170 having eight 16M ⁇ 4 bit multi-chip modules 30a-30h mounted on the side shown.
- Four 16M ⁇ 1-bit TSOP memory chips (not shown) are mounted on the opposite side of the SIMM board 170, in addition to one or more conventional buffer chips.
- Standard connector terminals 104 are provided along the bottom edge of the SIMM 100, permitting insertion of the SIMM into a connector slot.
- the eight 16M ⁇ 4-bit multi-chip modules 30a-30h and four 16M ⁇ 1-bit memory chips combine to produce a data width of 36 bits (32 data bits plus 4 error-correction code bits).
- the low profile of each multi-chip module 30a-30h advantageously enables multiple SIMMs to be mounted in close proximity to one another within a computer.
- stacking techniques described herein may be useful in alternative applications that do not involve the stacking of memory chips.
- the stacking techniques could be used to stack multiple buffer chips, or to stack multiple logic driver chips.
Abstract
Description
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/064,348 USRE36916E (en) | 1995-03-21 | 1998-04-22 | Apparatus for stacking semiconductor chips |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/408,552 US5514907A (en) | 1995-03-21 | 1995-03-21 | Apparatus for stacking semiconductor chips |
US09/064,348 USRE36916E (en) | 1995-03-21 | 1998-04-22 | Apparatus for stacking semiconductor chips |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/408,552 Reissue US5514907A (en) | 1995-03-21 | 1995-03-21 | Apparatus for stacking semiconductor chips |
Publications (1)
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USRE36916E true USRE36916E (en) | 2000-10-17 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US08/408,552 Ceased US5514907A (en) | 1995-03-21 | 1995-03-21 | Apparatus for stacking semiconductor chips |
US09/064,348 Expired - Lifetime USRE36916E (en) | 1995-03-21 | 1998-04-22 | Apparatus for stacking semiconductor chips |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US08/408,552 Ceased US5514907A (en) | 1995-03-21 | 1995-03-21 | Apparatus for stacking semiconductor chips |
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Cited By (42)
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US6225689B1 (en) * | 1998-08-21 | 2001-05-01 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
US6278616B1 (en) * | 1998-07-07 | 2001-08-21 | Texas Instruments Incorporated | Modifying memory device organization in high density packages |
US6288907B1 (en) * | 1996-05-20 | 2001-09-11 | Staktek Group, L.P. | High density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain relief |
US20020017709A1 (en) * | 2000-06-07 | 2002-02-14 | Yoshiyuki Yanagisawa | Assembly jig and manufacturing method of multilayer semiconductor device |
US6487078B2 (en) | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
US20030040166A1 (en) * | 2001-05-25 | 2003-02-27 | Mark Moshayedi | Apparatus and method for stacking integrated circuits |
US20030067082A1 (en) * | 2001-05-25 | 2003-04-10 | Mark Moshayedi | Apparatus and methods for stacking integrated circuit devices with interconnected stacking structure |
US6552424B2 (en) | 2001-08-30 | 2003-04-22 | Micron Technology, Inc. | Angled edge connections for multichip structures |
US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
US6608763B1 (en) | 2000-09-15 | 2003-08-19 | Staktek Group L.P. | Stacking system and method |
US20030165051A1 (en) * | 2000-03-13 | 2003-09-04 | Kledzik Kenneth J. | Modular integrated circuit chip carrier |
US6670701B2 (en) * | 2001-02-01 | 2003-12-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor module and electronic component |
US6686654B2 (en) * | 2001-08-31 | 2004-02-03 | Micron Technology, Inc. | Multiple chip stack structure and cooling system |
US6719568B2 (en) * | 2001-12-19 | 2004-04-13 | Sumitomo Electric Industries, Ltd. | Electric circuit unit |
US6734538B1 (en) | 2001-04-12 | 2004-05-11 | Bae Systems Information & Electronic Systems Integration, Inc. | Article comprising a multi-layer electronic package and method therefor |
US20040096812A1 (en) * | 2001-01-02 | 2004-05-20 | Myers Dawes Andras ?amp; Sherman LLP Andras Joseph C. | Breadboard used for educational purposes |
US6762487B2 (en) | 2001-04-19 | 2004-07-13 | Simpletech, Inc. | Stack arrangements of chips and interconnecting members |
US20040194301A1 (en) * | 2001-03-14 | 2004-10-07 | Kledzik Kenneth J. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
US6806120B2 (en) | 2001-03-27 | 2004-10-19 | Staktek Group, L.P. | Contact member stacking system and method |
US20040214466A1 (en) * | 2003-04-25 | 2004-10-28 | Wen-Yen Lin | Joint connector of printed circuit board and manufacturing method thereof |
US6914324B2 (en) | 2001-10-26 | 2005-07-05 | Staktek Group L.P. | Memory expansion and chip scale stacking system and method |
US6940729B2 (en) | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
US7005584B2 (en) | 2004-02-13 | 2006-02-28 | Honeywell International Inc. | Compact navigation device assembly |
US20060107524A1 (en) * | 2000-10-16 | 2006-05-25 | Jason Engle | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
US20060249829A1 (en) * | 2005-04-08 | 2006-11-09 | Mitsuaki Katagiri | Stacked type semiconductor device |
US20080067657A1 (en) * | 2006-09-19 | 2008-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit devices with multi-dimensional pad structures |
US7405471B2 (en) | 2000-10-16 | 2008-07-29 | Legacy Electronics, Inc. | Carrier-based electronic module |
US20080189480A1 (en) * | 2007-02-01 | 2008-08-07 | Jung Pill Kim | Memory configured on a common substrate |
US7435097B2 (en) | 2005-01-12 | 2008-10-14 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
US7465608B1 (en) | 2001-08-17 | 2008-12-16 | Micron Technology, Inc. | Three-dimensional multichip module |
US7608919B1 (en) | 2003-09-04 | 2009-10-27 | University Of Notre Dame Du Lac | Interconnect packaging systems |
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US20100246141A1 (en) * | 2009-03-31 | 2010-09-30 | Hong Kong Applied Science and Technology Research Institute Co. Ltd. (ASTRI) | Electronic package and method of fabrication thereof |
US8236610B2 (en) | 2009-05-26 | 2012-08-07 | International Business Machines Corporation | Forming semiconductor chip connections |
US8802497B2 (en) | 2009-05-26 | 2014-08-12 | International Business Machines Corporation | Forming semiconductor chip connections |
US9035465B2 (en) | 2009-05-26 | 2015-05-19 | International Business Machines Corporation | Forming semiconductor chip connections |
US9620473B1 (en) | 2013-01-18 | 2017-04-11 | University Of Notre Dame Du Lac | Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment |
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