USRE40061E1 - Multi-chip stacked devices - Google Patents

Multi-chip stacked devices Download PDF

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Publication number
USRE40061E1
USRE40061E1 US10/346,860 US34686003A USRE40061E US RE40061 E1 USRE40061 E1 US RE40061E1 US 34686003 A US34686003 A US 34686003A US RE40061 E USRE40061 E US RE40061E
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die
bonding pads
lead
lead fingers
low
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US10/346,860
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Michael B. Ball
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Round Rock Research LLC
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Micron Technology Inc
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Priority claimed from US08/043,503 external-priority patent/US5291061A/en
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Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
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Definitions

  • This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.
  • Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the form of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads.
  • IC integrated circuit
  • the bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire.
  • a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip.
  • a trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
  • IC package density is primarily limited by the area available for die mounting and the height of the package.
  • Typical computer-chip heights in the art are about 0.110 inches inch.
  • a method of increasing density is to stack die or chips vertically.
  • An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer.
  • the lower, slightly larger die is face-bonded to the lower surface of the lead extensions within the lower lead-frame die-bonding region via a second, adhesively coated, insulative, film layer.
  • the wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires.
  • the lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
  • U.S. Pat. No. 4,996,587 shows a semiconductor chip package which uses a chip carrier to support the chips within a cavity.
  • the chip carrier as shown in the figures has a slot that permits connection by wires to bonding pads which, in turn, connect to the card connector by conductors.
  • An encapsulation material is placed only on the top surface of the chip in order to provide heat dissipation from the bottom surface when carriers are stacked.
  • a Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
  • the invention generally stated is a multiple-die low-profile semiconductor device comprising:
  • FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention.
  • FIG. 2 is a side elevation taken through lines 2 — 2 of FIG. 1 showing a four die stacking.
  • the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted upon to the paddle 14 and other dies 16 , 18 , and 20 ( FIG. 2 ) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22 .
  • Thermoplastic indicating “Thermoplastic” indicates that the adhesive sets at an elevated temperature.
  • the group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24 .
  • Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28 A, 28 B, 28 C . . . 28 N by thin (0.001 inch) gold or aluminum wires 30 A, 30 B, 30 C . . . 30 N; gold being the preferred metal.
  • the critical bonding method used at the die end pad 26 is an ultrasonic ball bond bond, as named by the shape of the bond as at 32 . This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34 , as will be described later.
  • the other end of gold wires 30 are attached to the lead fingers by a wedge bond 36 , which is also an ultrasonic bond, indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28 .
  • the wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface.
  • the lead fingers may be formed upward as at 38 to permit the use of shorter wires 30 .
  • Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42 .
  • the stack is finally encapsulated by a plastic or ceramic at 44 .
  • a dimensional analysis is provided by referring to FIG. 2 .
  • the encapsulation thickness 48 is between 0.010 and 0.012 inches inch.
  • the paddle 74 14 thickness 50 can be between 0.005 and 0.010 inches inch and is a matter of choice.
  • the controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches inch.
  • the individual dies 20 , 18 , 16 , and 12 each have a thickness 54 of 0.012 inches inch and the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches inch. These thin layers have to be slightly greater than the low-loop wire dimension 34 , which is about 0.006 inches inch.
  • the top encapsulation thickness 58 is between 0.010 and 0.012 inches inch so as to cover the top loop.
  • the height at 60 would be between 0.058 and 0.073 inches inch and for a three-die stack it would be from 0.078 to 0.100 inches inch.
  • the die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel.
  • the final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
  • SOJ small outline J-leaded
  • DIP dual in-line package
  • SIP single in-line package
  • PLCC plastic leaded chip carrier
  • ZIP zig-zag in-line package

Abstract

A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.

Description

CROSS REFERENCE TO RELATED APPLICATION
This reissue application is a divisional of application Ser. No. 09/427,123, filed Oct. 21, 1999, pending, which is a continuation of reissue application Ser. No. 08/610,127, filed Feb. 29, 1996, now U.S. Pat. Re. 36,613, reissued on Mar. 14, 2000, from U.S. Pat. No. 5,291,061, dated Mar. 1, 1994.
FIELD OF THE INVENTION
This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the form of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads. The bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire. Following the application of a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip. A trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
In the interest of higher performance equipment and lower cost, increased miniaturization of components and greater packaging density have long been the goals of the computer industry. IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inches inch. A method of increasing density is to stack die or chips vertically.
U.S. Pat. No. 5,012,323, issued Apr. 30, 1991, having a common assignee with the present application, discloses a pair of rectangular integrated-circuit dice mounted on opposite sides of the lead frame. An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer. The lower, slightly larger die is face-bonded to the lower surface of the lead extensions within the lower lead-frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
U.S. Pat. No. 4,996,587 (referred to hereafter as '587) shows a semiconductor chip package which uses a chip carrier to support the chips within a cavity. The chip carrier as shown in the figures has a slot that permits connection by wires to bonding pads which, in turn, connect to the card connector by conductors. An encapsulation material is placed only on the top surface of the chip in order to provide heat dissipation from the bottom surface when carriers are stacked.
A Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
  • method 1 two chips mounted on two paddles;
  • method 2 one chip mounted over a paddle and one below not attached to the paddle; and
  • method 3 one chip attached above and one chip attached below a common paddle.
    The chips are apparently wired in parallel as stated in the “PURPOSE” of Sano.
The chips of patent '587 are also apparently wired in parallel by contacts on the “S” chips which contact the connection means.
It is the purpose of this invention to provide multiple stacked dies assembled in a special vertical configuration such that as many as four encapsulated dies will have a height no greater than existing 0.110-inch high dies and also have a separate lead and lead finger for each die pad connection.
SUMMARY OF THE INVENTION
The invention generally stated is a multiple-die low-profile semiconductor device comprising:
  • a lead-frame paddle supported by a lead frame;
  • a controlled, first, thin-adhesive layer affixing a first die above the paddle;
  • a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame lead fingers;
  • a second thin-adhesive layer affixing a second die above the first die;
  • a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
  • additional dies affixed above the second die, by additional subsequent layers of adhesive and having additional thin wires bonded to addition additional bonding pads and lead fingers; and
  • an encapsulated layer surrounding all dies, adhesive layers, and thin wires.
Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention may be better understood and further advantages and uses thereof may become more readily apparent when considered in view of the following detailed description of exemplary embodiments, taken with the accompanied drawings, in which:
FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention; and
FIG. 2 is a side elevation taken through lines 2—2 of FIG. 1 showing a four die stacking.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted upon to the paddle 14 and other dies 16, 18, and 20 (FIG. 2) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22. Thermoplastic indicating “Thermoplastic” indicates that the adhesive sets at an elevated temperature. The group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24.
Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal. For clarity, only part of the 18 bonding pads, wires, and fingers are shown. The critical bonding method used at the die end pad 26 is an ultrasonic ball bond bond, as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.
The other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic bond, indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28. The wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface. The lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.
Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42. The stack is finally encapsulated by a plastic or ceramic at 44.
A dimensional analysis is provided by referring to FIG. 2.
By careful control of layer thicknesses, it is possible to fabricate a four-stack die device having an overall height 46 of about 0.110 inches inch which is the same height as a current single die. Starting at the bottom, the encapsulation thickness 48 is between 0.010 and 0.012 inches inch. The paddle 74 14 thickness 50 can be between 0.005 and 0.010 inches inch and is a matter of choice. The controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches inch. The individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inches inch and the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches inch. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inches inch. Finally, the top encapsulation thickness 58 is between 0.010 and 0.012 inches inch so as to cover the top loop.
Thus, it can be seen by carefully controlling and minimizing the adhesive layer thicknesses 56, the top and bottom encapsulation thicknesses 48 and 58, and the paddle adhesive layer 52 that it is possible to have an overall height between 0.108 and 0.110 inches inch overall for the four-stack die.
If the looser tolerances were used for a two-stack die, the height at 60 would be between 0.058 and 0.073 inches inch and for a three-die stack it would be from 0.078 to 0.100 inches inch.
The fabrication of these two or four-stack die devices, necessarily, has to be from the bottom up, since it is not possible to form the die pad wire ball bond 32 on the lower dies 16, 18, and 30, if the four dies are already stacked. This is due to the overhead space required by the wire bond machine.
The die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel. The former configuration would, therefore, require (for a four die stack) something less than 4×18=72 4×18=72 leads, while parallel connections would require something on the order of 22 or more pins, depending on the type of devices and system requirements. The final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
While a preferred embodiment of the invention has been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.

Claims (12)

1. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first diebonding pads, said wire bond having a wire height above the bonding pad of about 0.006 inches, and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. two additional dies affixed above the second die by additional subsequent layers of adhesive of about 0.008 inches and having additional thin wires bonded to additional bonding pads and lead fingers; and
g. an encapsulated layer surrounding all dies, adhesive layers, and thin wires wherein a total encapsulated-package height is about 0.110 inches.
2. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 to 0.005 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads, said low-loop wire ball bond having a wire height above the bonding pads of about 0.006 inches and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. an encapsulated layer surrounding all die adhesive layers and thin wires wherein a total encapsulation-layer height is about 0.070 inches.
3. A method for fabricating a multiple-die, low-profile semiconductor device, comprising:
a.providing a lead frame having a lead frame paddle and a plurality of lead fingers;
b.affixing to said paddle a first die having a plurality of first die-bonding pads;
c.connecting bond wires between each of said plurality of first die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of first die-bonding pads and a wire bond on each of said corresponding lead fingers;
d.affixing to said first die, following said connecting bond wires, a second die having a plurality of second die-bonding pads;
e.connecting bond wires between each of said plurality of second die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of second die-bonding pads and a wire bond on each of said corresponding lead fingers; and
f.affixing two additional dies above said second die.
4. The method of claim 3, further comprising encapsulating all dies and bond wires with an encapsulation layer having a height of about 0.110inchesinch.
5. The method of claim 3, wherein die-bonding pads of said first plurality of die-bonding pads are connected to said corresponding lead fingers of said plurality of lead fingers in parallel with die-bonding pads of said second plurality of die-bonding pads.
6. The method of claim 3, wherein die-bonding pads of said first plurality of die-bonding pads and die-bonding pads of said second plurality of die-bonding pads are each connected to individual ones of said plurality of lead fingers.
7. The method of claim 3, wherein said providing comprises providing a lead frame having a downset lead frame paddle and a plurality of lead fingers upset relative to said downset lead frame paddle.
8. The method of claim 3, wherein said connecting bond wires between each of said first and second pluralities of die-bonding pads and corresponding ones of said lead fingers comprises forming said low-loop wire bonds on each of said die-bonding pads to be ball bonds.
9. The method of claim 3, wherein said connecting bond wires between each of said first and second pluralities of die-bonding pads and corresponding ones of said lead fingers comprises forming said wire bonds on each of said corresponding lead fingers to be wedge bonds.
10. The method of claim 3, wherein said affixing said first die to said lead frame paddle comprises disposing a layer of adhesive between said lead frame paddle and said first die.
11. The method of claim 10, wherein said disposing said layer of adhesive comprises forming said layer of adhesive to be about 0.001inchesinch thick.
12. The method of claim 3, wherein said affixing said second die to said first die comprises disposing a layer of adhesive between said first die and said second die.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080122113A1 (en) * 2006-08-17 2008-05-29 Corisis David J Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device and methods for forming the same
US20080142942A1 (en) * 2006-12-19 2008-06-19 Yong Du Method and apparatus for multi-chip packaging
US20090146278A1 (en) * 2006-09-12 2009-06-11 Chipmos Technologies Inc. Chip-stacked package structure with asymmetrical leadframe
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory
JPS60182731A (en) 1984-02-29 1985-09-18 Toshiba Corp Semiconductor device
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS62126661A (en) 1985-11-27 1987-06-08 Nec Corp Hybrid integrated circuit device
JPS63128736A (en) 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
JPS6428856A (en) 1987-07-23 1989-01-31 Mitsubishi Electric Corp Multilayered integrated circuit
US4984059A (en) 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same
US4996587A (en) 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
JPH03169062A (en) 1989-11-28 1991-07-22 Nec Kyushu Ltd Semiconductor device
US5049976A (en) 1989-01-10 1991-09-17 National Semiconductor Corporation Stress reduction package and process
JPH0456262A (en) 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device
USRE36613E (en) 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory
US4984059A (en) 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
JPS60182731A (en) 1984-02-29 1985-09-18 Toshiba Corp Semiconductor device
JPS62126661A (en) 1985-11-27 1987-06-08 Nec Corp Hybrid integrated circuit device
JPS63128736A (en) 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
JPS6428856A (en) 1987-07-23 1989-01-31 Mitsubishi Electric Corp Multilayered integrated circuit
US5049976A (en) 1989-01-10 1991-09-17 National Semiconductor Corporation Stress reduction package and process
US4996587A (en) 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
JPH03169062A (en) 1989-11-28 1991-07-22 Nec Kyushu Ltd Semiconductor device
JPH0456262A (en) 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device
USRE36613E (en) 1993-04-06 2000-03-14 Micron Technology, Inc. Multi-chip stacked devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080122113A1 (en) * 2006-08-17 2008-05-29 Corisis David J Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device and methods for forming the same
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US20090146278A1 (en) * 2006-09-12 2009-06-11 Chipmos Technologies Inc. Chip-stacked package structure with asymmetrical leadframe
US20080142942A1 (en) * 2006-12-19 2008-06-19 Yong Du Method and apparatus for multi-chip packaging
US7691668B2 (en) * 2006-12-19 2010-04-06 Spansion Llc Method and apparatus for multi-chip packaging
US20100164124A1 (en) * 2006-12-19 2010-07-01 Yong Du Method and apparatus for multi-chip packaging
US8324716B2 (en) * 2006-12-19 2012-12-04 Spansion Llc Method and apparatus for multi-chip packaging
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge

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