USRE40076E1 - Program circuit - Google Patents
Program circuit Download PDFInfo
- Publication number
- USRE40076E1 USRE40076E1 US09/915,906 US91590601A USRE40076E US RE40076 E1 USRE40076 E1 US RE40076E1 US 91590601 A US91590601 A US 91590601A US RE40076 E USRE40076 E US RE40076E
- Authority
- US
- United States
- Prior art keywords
- information
- data
- memory cells
- output
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Definitions
- the present invention relates to a program circuit and, more particularly, to a program circuit which can prevent a lowering of reliability occurring during the process of verifying the programmed data.
- a flash memory device has functions of electrical program and erasure.
- the flash memory device also performs a verification operation so as to confirm whether the memory cell has been programmed or erased or not after completion of the programming or the erasure operation. At this time, if there are memory cells in which a programming or erasure operation has not completed, re-programming or re-erasure operation is performed again.
- a program circuit comprises a comparator for comparing output data of a data input buffer with output data of a sense amplifier bit by bit and for outputting a re-program operation signal if the data are different each other, a data latch circuit for latching the comparing results of the output data of the data input buffer and the output data of the sense amplifier, and a control circuit for generating a high voltage for receiving the output data of the data input buffer and the data latched at the data latch circuit, respectively and for outputting a signal for applying a program bias voltage to a memory cell which has not been programmed in response to a power-up reset signal and program state signal.
- the data latch circuit has a plurality of flip-flops, each flip-flop has a data input terminal to which comparing results of the output data of the data input buffer and the output data of the sense amplifier, a clock signal input terminal to which a program state signal, and a reset signal input signal to which power-up reset signal/program state signal/read mode signals are inputted.
- the control circuit for generating a high voltage includes a plurality of NOR gates to which output data of the data latch circuit and a power-up reset signal are inputted, respectively, a plurality of inverters to which output data of the data input buffer is inputted; and a plurality of NAND gates to which the output signals of the NOR gates, the output signals of the inverters and the program state signal are inputted, respectively.
- FIGURE is a circuit diagram for explaining a program circuit according to the present invention.
- the accompanying drawing is a circuit diagram for explaining a program circuit according to the present invention.
- the program circuit according to the present invention is consisted of a comparator 1 , a data latch circuit 2 , and a control circuit for generating a high voltage 3 , and added to the flash memory device.
- the comparator 1 comprises of a plurality of exclusive NOR gates EG 1 through EG 8 to which output data LDIN 0 through LDIN 7 of a data input buffer and output data SA 0 through SA 7 of a sense amplifier are inputted, respectively. Also, the comparator 1 comprises a NOR gate NG to which output signals of the exclusive NOR gates EG 1 through EG 8 are inputted. The NOR gate NG outputs logical combination signals via an output terminal DATA COMP.
- the data latch circuit 2 is consisted of a plurality of flip-flops F 1 through F 8 .
- Each of flip-flops F 1 through F 8 comprises a data input terminal D to which an output signal of one of the exclusive NOR gates EG 1 through EG 8 , a clock signal input terminal CL to which a program state signal PGM 4 is inputted, and a reset signal input terminal R to which a power-up reset signal/program state signal/read mode signals PURST/PGM 3 /READ are inputted.
- the control circuit for generating a high voltage 3 comprises a plurality of NOR gates N 1 through N 8 to which output data Q 0 through Q 7 of the flip-flops F 1 through F 8 and the power-up reset signal PURST are inputted, respectively, a plurality of inverters I 1 through I 8 to which the output data LDIN 0 through LDIN 7 of data input buffer are inputted, respectively, and a plurality of NAND gates NG 1 through NG 8 to which output signals of the NOR gates N 1 through N 8 , output signals of the inverters I 1 through I 8 and the program state signal PGM 1 , respectively.
- the plurality of NAND gates NG 1 through NG 2 output signals VCVPB 0 through VCVPB 7 , respectively.
- the data “10011000” is inputted to the exclusive NOR gates EG 1 through EG 8 via one input terminal, respectively, and the data read from the memory cell, that is, the data SA 0 through SA 7 outputted from the sense amplifier are inputted to the exclusive NOR gates EG 1 through EG 8 via other input terminal, respectively.
- the data “101111011” outputted via the output terminals of the exclusive NOR gates EG 1 through EG 8 is latched to the flip-flops F 1 through F 8 respectively depending on the input of the program state signal PGM 4 , and the output signals Q 0 through Q 7 of the flip-flops F 1 through F 8 are inputted to the NOR gates N 1 through N 8 , respectively.
- the flip-flops F 1 through F 8 are maintained at the state in which the data of “0” is latched by the input of the power-up reset signal PURST.
- the data “10011000” outputted from the flip-flops F 1 through F 8 are inputted to the NOR gates N 1 through N 8 of the control circuit for generating high voltage 3 respectively, and the output data “1001100” of the data input buffer is inputted to the inverters I 1 and I 8 , respectively.
- signals at a low level are outputted from only the output terminals VCVPB 1 and VCVPB 5 of the NAND gates NG 2 and NG 6 by the power-up reset signal PURST inputted with a low level and the program state signal PGM 1 inputted with a high level. Therefore, a programming bias voltage is again applied to only the memory cells which are corresponded to the second and the sixth bits, respectively.
- the program circuit according to the present invention can apply a program voltage to only the memory cells which are not programmed during a re-programming operation. Therefore, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a program bias voltage.
Abstract
Description
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/915,906 USRE40076E1 (en) | 1996-06-29 | 2001-07-25 | Program circuit |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960025547A KR100193898B1 (en) | 1996-06-29 | 1996-06-29 | Flash memory device |
US08/882,835 US5930179A (en) | 1996-06-29 | 1997-06-26 | Program circuit |
US09/915,906 USRE40076E1 (en) | 1996-06-29 | 2001-07-25 | Program circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/882,835 Reissue US5930179A (en) | 1996-06-29 | 1997-06-26 | Program circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE40076E1 true USRE40076E1 (en) | 2008-02-19 |
Family
ID=19464583
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/882,835 Ceased US5930179A (en) | 1996-06-29 | 1997-06-26 | Program circuit |
US09/915,906 Expired - Lifetime USRE40076E1 (en) | 1996-06-29 | 2001-07-25 | Program circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/882,835 Ceased US5930179A (en) | 1996-06-29 | 1997-06-26 | Program circuit |
Country Status (4)
Country | Link |
---|---|
US (2) | US5930179A (en) |
KR (1) | KR100193898B1 (en) |
GB (1) | GB2314953B (en) |
TW (1) | TW367502B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100322018B1 (en) * | 1999-01-23 | 2002-02-04 | 윤종용 | Apparatus for compensating voice band noise |
US6747481B1 (en) * | 2002-11-22 | 2004-06-08 | Texas Instruments Incorporated | Adaptive algorithm for electrical fuse programming |
FR2894710A1 (en) * | 2005-12-14 | 2007-06-15 | St Microelectronics Sa | Binary word`s write command execution method for e.g. smart card, involves comparing bit with program status of binary word to be written and bit of write word, and generating error signal when bits are different |
US8248848B1 (en) | 2007-10-01 | 2012-08-21 | Marvell International Ltd. | System and methods for multi-level nonvolatile memory read, program and erase |
KR102651590B1 (en) | 2022-04-05 | 2024-03-25 | 한국타이어앤테크놀로지 주식회사 | Tires with Air Pocket Performance |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4811294A (en) * | 1985-06-21 | 1989-03-07 | Mitsubishi Denki Kabushiki Kaisha | Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM) |
US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
US5299162A (en) * | 1992-02-21 | 1994-03-29 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and an optimizing programming method thereof |
US5521868A (en) * | 1993-08-11 | 1996-05-28 | Sony Corporation | NOR-type non-volatile memory using tunnel current and having selective re-write |
US5570315A (en) * | 1993-09-21 | 1996-10-29 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
US5574684A (en) * | 1995-01-09 | 1996-11-12 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Flash memory having data refresh function and data refresh method of flash memory |
US5629890A (en) * | 1994-09-14 | 1997-05-13 | Information Storage Devices, Inc. | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method |
US5657270A (en) * | 1990-03-31 | 1997-08-12 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with threshold value controller for data programming |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3176008B2 (en) * | 1994-03-30 | 2001-06-11 | 株式会社東芝 | Semiconductor memory circuit |
KR100208433B1 (en) * | 1995-12-27 | 1999-07-15 | 김영환 | Flash memory device and program method using it |
-
1996
- 1996-06-29 KR KR1019960025547A patent/KR100193898B1/en not_active IP Right Cessation
-
1997
- 1997-06-19 GB GB9712951A patent/GB2314953B/en not_active Expired - Fee Related
- 1997-06-26 US US08/882,835 patent/US5930179A/en not_active Ceased
-
1998
- 1998-04-08 TW TW087105311A patent/TW367502B/en not_active IP Right Cessation
-
2001
- 2001-07-25 US US09/915,906 patent/USRE40076E1/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4811294A (en) * | 1985-06-21 | 1989-03-07 | Mitsubishi Denki Kabushiki Kaisha | Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM) |
US5163021A (en) * | 1989-04-13 | 1992-11-10 | Sundisk Corporation | Multi-state EEprom read and write circuits and techniques |
US5657270A (en) * | 1990-03-31 | 1997-08-12 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with threshold value controller for data programming |
US5299162A (en) * | 1992-02-21 | 1994-03-29 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and an optimizing programming method thereof |
US5521868A (en) * | 1993-08-11 | 1996-05-28 | Sony Corporation | NOR-type non-volatile memory using tunnel current and having selective re-write |
US5570315A (en) * | 1993-09-21 | 1996-10-29 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
US5629890A (en) * | 1994-09-14 | 1997-05-13 | Information Storage Devices, Inc. | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method |
US5574684A (en) * | 1995-01-09 | 1996-11-12 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Flash memory having data refresh function and data refresh method of flash memory |
Also Published As
Publication number | Publication date |
---|---|
US5930179A (en) | 1999-07-27 |
GB2314953A (en) | 1998-01-14 |
TW367502B (en) | 1999-08-21 |
KR980005026A (en) | 1998-03-30 |
KR100193898B1 (en) | 1999-06-15 |
GB2314953B (en) | 2000-07-05 |
GB9712951D0 (en) | 1997-08-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:030085/0600 Effective date: 20120323 Owner name: FIDELIX CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SK HYNIX INC.;REEL/FRAME:030086/0328 Effective date: 20130307 |
|
AS | Assignment |
Owner name: DOSILICON CO., LTD., CHINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FIDELIX CO., LTD.;REEL/FRAME:042244/0073 Effective date: 20170412 |