USRE41733E1 - Dual-addressed rectifier storage device - Google Patents
Dual-addressed rectifier storage device Download PDFInfo
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- USRE41733E1 USRE41733E1 US09/821,182 US82118201A USRE41733E US RE41733 E1 USRE41733 E1 US RE41733E1 US 82118201 A US82118201 A US 82118201A US RE41733 E USRE41733 E US RE41733E
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Definitions
- the present invention relates to electronic data retrieval devices, and more particularly to electronic digital logic devices having semiconductor mass storage capabilities by virtue of their data being stored in highly symmetrical arrays of diodes.
- ROM read-only memory
- ROM read-only memory
- Many of these ROM devices have been disclosed having a wide variety of implementations. In many of these devices the bit storage means is accomplished through the application of gates or transistors. But, a subset of these ROM devices has accomplished the bit, storage means through the use of a matrix of diodes, as was disclosed by Robb in U.S. Pat. No. 3,245,051. Many of these ROM devices is include diode matrix storage means utilizing a set of conductors that act as selectors and a second orthogonal set of conductors that act as data outputs.
- one set of generally parallel conductors acts as the Selection Input Lines and a second set of generally parallel conductors that is orthogonal to and overlapping with the first acts as the Digit Output Lines.
- a bit of information is represented at each point of intersection of the Selection Input lines with the Digit Output Lines by the presence or absence of a diode at that point, where the presence or absence of a diode distinguishes the logical state of the stored information bit at that point of intersection.
- a selection circuit selects one line of the Selection Input Lines such that the state of all of the Digit Output Lines is then controlled to the extent that each of those Digit Output Lines is connected to that selected Selection Input Line through a diode. All of the digit Digit Output Lines are read in parallel.
- a disadvantage is that as the matrix is increased in size, the complexity of the selection logic that drives the selection circuits (such that one line is selected out of the many Selection Input Lines) grows exponentially. But as this matrix increases in size, so too will the number of Digit Output Lines that will have to be simultaneously supplied with current and that current will vary depending upon the state of the bits at those various locations. Also, as the number of simultaneously driven Digit Output Lines increases, some means of selecting the subset of desired data bits would have to be added.
- the addressing means could be of the same DTL type to keep said addressing means small, the large number of buffering transistors to select the various conductive lines will remain large (at least one FET per conductive line and, on about half of the lines, two FET's). Furthermore, this inclusion of FET transistors may make the device subject to damage from static electrical discharges that might make it less practical for use in a consumer product where the consumer may handle these devices.
- Eardley discloses a dual-addressed device wherein the selected diode is at the intersection of a column line and a row line (where the column lines are connected to the diodes' cathodes and the row lines are connected to the diodes' anodes) such that the voltage potential of one column line is lowered and the voltage potential of one row line is raised thereby forward biasing the diode, if any, at the point of intersection of the two lines.
- One of the features of this device over the prior art is the circuitry for the selection logic; Eardley discloses means for line selection comprising high speed transistor driver circuits.
- the disclosed device also requires two types of Schottky barrier diode devices. As a result, it is anticipated that the disclosed device will suffer from several problems, particularly when one attempts to scale up the device to extremely high storage densities. These problems may include transistor current leakage becoming noticeable as the number of transistors increases and device yields becoming reduced as the complexity of multiple semiconductor fabrication steps and nore more complex device interconnect circuitry increases. These problems may prevent the kind of size scaling that could result in devices in the Gigabit range that would be necessary to create memory chips that could replace today's CD-ROMs.
- the Dual-addressed Rectifier Storage (DRS) Array comprised by the present invention solves many of the Problems problems associated with the above mentioned inventions while sustaining high data packing densities by simultaneously using both orthogonal sets of conductors to address the data bits without the need for transistor switches on each conductive line. It does this by having a diode-logic addressing mechanism directly controlling the voltage levels on the conductive lines. Also, by extending the application of the diode array to perform the functions of addressing, storage, and bit sensing, symmetry is increased and this higher symmetry results in higher packing densities.
- a means for programming the information into a semiconductor diode array by selectively etching away openings through the oxide layer that insulates the plurality of doped conductors from the orthogonal plurality of metalized conductors on the surface such that each opening enabled contact between the respective conductor of each plurality thereby forming a diode representing a toggled bit of stored information at that array location.
- the present invention discloses a means for constructing the semiconductor device up to the final metalization etch step before programming the data thereby enabling the programming of data to be performed much later in the manufacturing process.
- Mass storage devices comprising moveable media such as magnetic disks, optical compact disks, digital tape, or the like, have motors and other mechanical parts that are prone to breaking or wearing out, can suffer audio disruption when subjected to vibrations, are too heavy to be carried during certain activities such as jogging, and consume significant electrical power (due to the operation of the mechanical components).
- Devices utilizing ROM chips are limited in their capacities due to the limited storage densities of present day ROM chips.
- the present invention eliminates or reduces all of these drawbacks because it uses DRS Arrays and, as a result, has the high storage densities of a CD-ROM without having mechanical parts.
- this device comprises one or more Dual-addressed Rectifier Storage (DRS) Arrays which are read-only memory (ROM) devices that utilize an array of rectifiers for its storage means.
- DRS Dual-addressed Rectifier Storage
- ROM read-only memory
- the logical state of stored data is determined by the presence or absence of rectifiers at the points of intersection of two orthogonal and overlapping sets of generally parallel conductive lines.
- the present invention uses both sets of generally parallel conductive lines for addressing but senses the logical state of the addressed data by sensing the loading on the selected lines.
- the DRS Array comprises a cross-point selection means that enables the selection of a single point of intersection from within an array by applying a forward voltage across that point; this selection means will find applications in Read Only Memory (ROM) as shown in the present device, One-Time Programmable Read Only Memory (OTPROM), Random Access Memory (RAM), and LED matrix displays.
- ROM Read Only Memory
- OTPROM One-Time Programmable Read Only Memory
- RAM Random Access Memory
- LED matrix displays LED matrix displays.
- the DRS Array comprises an array of Rectifiers rectifiers (where the column lines are connected to the cathodes of said rectifiers and the row lines are connected to the anodes of said rectifiers) wherein the row lines and column lines are pulled through resistive means to either the positive supply or to ground, respectively, such that, absent any addressing circuitry, all of the rectifiers in the array would be forward biased.
- the addition of addressing circuitry will selectively connect those row lines and column lines to either ground or the positive supply such that the voltage potential between any row line and column line would be dropped to the point that an interconnected rectifier no longer would be forward biased. Any line whose voltage is pulled close to either ground or to the positive supply and away from that voltage that would result from the resistive means alone will be referred to as Being being “disabled.”
- This disabling means is a greatly simplified selection circuit on both orthogonal sets in the array.
- the addressing means, the storage means, and the bit sensing means are all formed in the same rectifier array structure in a highly simple and symmetric design that is ideal for high packing densities.
- the present invention comprises DRS Arrays that could be removable and interchangeable so that one could pop them in and out according to their current musical interest or desire.
- a DRS Array is expected to be able to hold the equivalent of an entire CD-ROM or more on a single one inch (or smaller) square of silicon, unlike conventional read only memory chips (ROM's) which would require about 50 ROM chips if each contained about 10 Megabytes of data.
- ROM's read only memory chips
- the present invention would be very small and compact.
- the present invention through the use of the DRS array, eliminates the mechanical components of such devices. In so doing, the present invention reduces the risk of mechanical failures, the problems of bulkiness, and the consumption of electrical power.
- the many possible variations on the DRS Array make it a very versatile storage medium ranging from a stand-alone array chip, to an array chip with an incorporated sequentially loaded address sequencer, to a microcomputer chip that utilizes the DRS Array for its program memory, to a personal stereo unit utilizing a removable DRS Array instead of a music CD-ROM, to a pocket sized video player utilizing a removable DRS Array module containing compressed video data.
- FIG. 1 illustrates a block diagram of a digital logic device comprising a Dual-addressed Rectifier Storage (DRS) Array, keypad, LCD display and dual analog outputs.
- DRS Dual-addressed Rectifier Storage
- FIG. 2 illustrates a schematic diagram showing one way to interface a Dual-addressed Rectifier Storage Array to a digital logic device.
- FIG. 3 illustrates a schematic diagram of a Dual-addressed Rectifier Storage Array.
- FIG. 4 illustrates a schematic diagram of a Dual-addressed Rectifier Storage Array which includes complementary address selection circuitry.
- FIG. 5 illustrates a variation on the data sensing means of a Dual-addressed Rectifier Storage Array for simultaneously accessing multiple stored bits in parallel and a variation on the addressing means for reducing the device's power consumption.
- FIG. 6 illustrates the doping step in the semiconductor manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 7 illustrates the oxide growth step in the semiconductor manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 8 illustrates the oxide etch step in the semiconductor Manufacture manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 9 illustrates the metalization step in the semiconductor Manufacture manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 10 illustrates the metalization etching step in the semiconductor manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 11 illustrates a variation on the semiconductor manufacture of the Anode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressed Rectifier Storage Array.
- FIG. 12 illustrates a plot of the voltage/current relationship of a diode.
- FIG. 13 illustrates a schematic diagram of a variation on the Dual-addressed Rectifier Storage Array wherein the resistive means is accomplished via “leaky” diodes.
- FIG. 14 illustrates a schematic diagram of a variation on the Dual-addressed Rectifier Storage Array which includes serial addressing circuitry.
- FIG. 1 shows a block diagram of a digital logic device comprising a microcomputer, a keypad, an LCD display, analog to digital to analog converters, analog buffers and amplifiers, a headphone jack, and a Dual-addressed Rectifier Storage (DRS) Array.
- Microcomputer, A is connected to a keypad, B, and an LCD display, C. This configuration is very common and several of the manufacturers of microcomputer chips have application notes showing the details and schematics of such a circuit configuration.
- Microcomputer, A is also interfaced to two 16 bit digital to analog converters, E, whose outputs are connected to circuitry, F, capable of driving a set of headphones (plugged into this device at the headphone jack, G).
- Circuitry such as this just described is known by one skilled in the art; this circuitry exists in essentially this form in many common devices, including portable CD-ROM audio players used for listening to music CD's.
- Software running in the microcomputer could also read from the keypad to affect the operation of that running software and cause it to jump to a specific address in the DRS Array at which point it would continue to read sequentially (such as to skip or repeat certain audio tracks, play the tracks contained in the DRS Array in random order, or the like).
- the data contained in the DRS Array need not be limited to musical data. Video data, computer software or applications, reference data such as text, diagrams or the like, or a variety of other information could be stored. Of course, in many of these possible data types, the exact configuration as shown in FIG. 1 may not be needed. For example, a DRS Array containing computer software would likely not need two digital to analog converters for output but would rather need interface logic such that it could be connected to a standard computer such that it emulated a standard CD-ROM drive.
- DRS arrays In this way, one could enjoy the benefits afforded by the use of DRS arrays without having to modify one's standard computer or its software (given an accurate emulation of a CD-ROM drive, that standard computer would operate just as if it was actually connected to a CD-ROM drive). What is needed is the ability to connect DRS Arrays to such digital logic devices as a personal computer, a microprocessor, a microcomputer chip or the like.
- FIG. 2 shows a possible way to interface a Dual-addressed Rectifier Storage Array to a digital logic device.
- A the address lines (or input/output ports configured to perform the function of addressing), A 0 through A 15 , connect directly to the lower address lines, A 0 through A 15 , of the DRS Array, as well as to the inputs of the 16 bit latch, H.
- the upper 16 bits of the address to the DRS Array are set by writing to a location in memory having the same lower 16 address bits as is desired for the upper address bits.
- the DRS Array is configured to be enabled by applying power through PNP transistor, I, and resistor, J, when the read line, ⁇ RD, goes low.
- the DRS Array as shown in FIG. 2 would contain about 537 Megabytes of information or about 56 minutes of 16-bit stereo audio sampled at 40,000 KHz, roughly the equivalent of a present day CD-ROM.
- FIG. 3 illustrates an example of a preferred embodiment of a Dual-addressed Rectifier Storage Array. While the array in this example is only 64 bits in size, it will become clear to one skilled in the art that this array is highly scaleable.
- the Storage Rows, P are connected to the Row Resistors, R. Also connecting to the Storage Rows, P, at various points are the anodes of the Storage Rectifiers, K, the anodes of the Row Addressing Rectifiers, L, and the anodes of the Storage Bit Sensing Rectifiers, U. Connecting to the Addressing Columns, N, are the cathodes of the Row Addressing Rectifiers, L. Connecting to the Storage Bit Sensing Column, M, are the cathodes of the Storage Bit Sensing Rectifiers, U.
- the Storage Columns, O are connected to the Column Resistors, S. Also connecting to the Storage Columns at various points are the cathodes of the Storage Rectifiers, K, and the cathodes of the Column Addressing Rectifiers, T. Connecting to the Addressing Rows, Q, at various points are the anodes of the Column Addressing Rectifiers, T.
- any rectifier present among the Storage Rectifiers, K would be forward biased and the forward voltage drop of any said Storage rectifier would be centered around the voltage level of one-half of the positive supply (the Row Resistors, R, and the Column Resistors, S, are of equal resistance values and therefore form a voltage divider having a center voltage level of one-half of the positive supply).
- the resistive means, Row Resistors, R, and the Column Resistors, S could be constructed through the use of resistors or their equivalent, the use of transistors (bipolar or FET) biased in their linear region (between being completely turned off and being saturated), the use of “leaky” diodes, or the like.
- the Addressing Columns, N work in complementary pairs labeled by address designation An and its complement ⁇ An (where n indicates the Nth address line). Addressing is performed by pulling an Addressing Column near to ground or near to the positive supply and its complementary Addressing Column near to the positive supply or near to ground respectively.
- the Addressing Rows, Q work in complementary pairs labeled by address designation An and its complement ⁇ An (where n indicates the Nth address line) addressing Addressing is performed by pulling an Addressing Row near to ground or near to the positive supply and its complementary Addressing Row near to the positive supply or near to ground respectively.
- Disabling the Storage Rows by pulling their voltages down and disabling the Storage Columns by pulling their voltages up will reverse bias any Storage Rectifiers at the intersection of said disabled Storage Rows with said disabled Storage Columns.
- the Storage Rectifier, if any, at the intersection of the remaining enabled Storage Row with the remaining enabled Storage Column will be forward biased and the forward voltage drop of said Storage Rectifier, if any, would be centered around the voltage level of one-half of the positive supply. This would place the voltage level on the enabled Storage Row at one-half of the positive supply plus one-half of the forward voltage drop across said Storage Rectifier. Also, this would place the voltage level on the enabled Storage Column at one-half of the positive supply less one-half of the forward voltage drop across said Storage Rectifier.
- the Storage Bit Sensing Column, M is to be biased to a voltage level just below the positive supply minus one rectifier forward voltage drop. Recalling that a disabled Storage Row will be at a voltage level equal to a near to ground voltage plus a rectifier's forward voltage, this means that the Storage Bit Sensing Rectifiers, U, between the Storage Bit Sensing Column, M, and each of the disabled Storage Rows will be reverse biased and conduct no current; this will account for the state of all of the Storage Bit Sensing Rectifiers, U, except the one connected between the Storage Bit Sensing Column, M, and the one enabled Storage Row.
- the voltage level of the positive supply is sufficiently high to forward bias the various rectifiers as described.
- This leakage current would be fairly constant and equal to the leakage of a rectifier reverse biased by an amount equal to the difference between the bias voltage on the output and the voltage on a disabled Storage Row multiplied by the number of disabled Storage Rows and, as such, could be corrected for if necessary. For example, an opposite current of equal magnitude could be injected into the Storage Bit Sensing Column.
- each Storage Row P
- the “X” signifies the upper address bit inputs (which control the Addressing Rows, Q, ) and the binary digits signify the lower address Bit inputs which control the Addressing Columns, N.
- Each bit position in the address designation of any Storage Row corresponds to a given address bit input and to a complementary pair of Addressing Columns.
- each Storage Column, O is an address designation shown as some binary digits followed by an “X”.
- the “X” signifies the lower address bit inputs (which control the addressing Rows, N) and the binary digits signify the upper address bit inputs which control the Addressing Rows, Q.
- Each bit position in the address designation of any Storage Column corresponds to a given address bit input and to a complementary pair of Addressing Rows.
- FIG. 4 shows identical circuitry to that shown in FIG. 3 except for the addition of complementary address input buffer-driver circuitry, V, W, X, and Y, as well as an output driver circuit, Z.
- transistors Q 2 and Q 4 will be turned on through resistors R 10 and R 12 when A 2 is at a high logic state.
- Transistor Q 4 When Transistor Q 4 is turned on, it will pull away the current available at the base of Q 3 , dropping the voltage on the base of Q 3 and thereby turning off Q 3 .
- the result is that the directly addressed Addressing column, A 2 , will be pulled to near ground (approximately 0.2 v) when A 2 is low and Q 3 is turned on (saturated), or the complementary addressed Addressing Column, ⁇ A 2 , will be pulled to near ground (approximately 0.2 v) when A 2 is high and Q 2 is turned on.
- transistors Q 11 and Q 12 will be turned off through resistors R 19 and R 20 when A 3 is at a high logic state (a high enough voltage that the base emitter junctions of Q 11 and Q 12 are not forward biased) or floating.
- transistor Q 11 When transistor Q 11 is turned off, transistor Q 13 will be turned on through resistor R 21 to ground.
- transistors Q 11 and Q 12 When A 3 is at a low logic state.
- transistor Q 11 When transistor Q 11 is turned on, it will cause the voltage on the base of Q 13 to come within 0.2 v of the positive supply and thereby turning off Q 13 .
- the output driver circuit, Z achieves the voltage biasing of the Storage Bit Sensing Column, M, while providing gain to the output current.
- the three rectifiers, D 33 , D 34 , and D 35 serve to set the voltage on the emitter of transistor Q 1 at three rectifier forward voltage drops below the positive supply. Assuming that the forward voltage drop across the base-emitter junction of transistor Q 1 is the same as the forward voltage drop of the rectifiers, this would require that the base of that transistor be at a voltage level no less than two rectifier forward voltage drops below the positive supply in order for its collector to draw current, which in turn would require that the one enabled Storage Row be at a voltage level no less than one rectifier forward voltage drop below the positive supply in order for the collector of transistor Q 1 to draw current. Naturally, it is not necessary that the forward voltage drop across the base-emitter junction of transistor Q 1 would be the same as the forward voltage drop of the rectifiers and one skilled in the art will know of other ways to bias the Storage Bit Sensing Column.
- the circuit used to describe the operation of a DRS Array and shown in FIG. 4 can be constructed using silicon diodes (such as the 1N914) for all of the rectifiers; 1 M ⁇ resistors for all of the Row Resistors, R, and Column Resistors, S, and for the resistor in the output driver circuit, R 9 ; 10K ⁇ resistors for all of the resistors of the address input buffer-driver circuitry, V and W; 2N3904 transistors for all of the NPN transistors and 2N3906 transistors for all of the PNP transistors.
- the output will sink virtually no current when addressing the point of intersection of a Storage Row with a Storage Column that has a rectifier present at that point. If no rectifier is present at the addressed point of intersection, approximately 0.7 ⁇ A will flow into the base of Q 1 and, assuming a current gain ( ⁇ ) of about 100 times for Q 1 , the output will therefore sink abouto about 0.07 mA.
- FIG. 5 shows two variations on the Dual-addressed Rectifier Storage Array.
- the first variation relates to the number of bits of stored information that will be retrieved at the same time. Notice that Row Addressing Rectifiers D 9 through D 16 , transistors QZ Q 2 through Q 4 and resistors R 10 through R 12 have been removed, that transistor Q 23 , rectifiers D 86 , D 87 , and D 88 and resistor R 39 have been added, and that the Storage Bit Sensing Rectifiers have been split into two groups where the cathodes of rectifiers D 5 through D 8 are now connected to the base of transistor Q 23 through a new Storage Bit Sensing Column.
- the resulting circuit is the equivalent of two DRS Arrays placed one above the other with each having four Storage Rows and eight Storage Columns where those eight Storage Columns (and their associated addressing means) are common to both arrays and where the Addressing Columns that are connected to the cathodes of the Row Addressing Rectifiers of the two arrays (and their associated addressing means) are also common to both.
- Transistor Q 1 , rectifiers D 33 , D 34 , and D 35 , and resistor R 9 now operate with Storage Bit Sensing Rectifiers, D 1 , D 2 , D 3 , and D 4 , to detect state of the addressed bit within one array and transistor Q 23 , rectifiers D 86 , D 87 , and D 88 , and resistor R 39 now operate with Storage Bit Sensing Rectifiers, D 5 , D 6 , D 7 , and D 8 , to detect state of the addressed bit within the other array.
- this variation can be applied multiple times such that even larger numbers of bits can be read simultaneously.
- FIG. 5 Also shown in FIG. 5 is a variation relating to the power requirements of the device and, in particular, to limiting the current in the device to only a portion of that device thereby reducing the overall power consumption.
- Column Addressing Rectifiers D 36 through D 43 transistors Q 17 through Q 19 and resistors R 25 through R 27 have been removed, that transistors Q 20 , Q 21 and Q 22 , and resistors R 36 , R 37 , and R 38 have been added and that the Storage Columns have been divided into two groups where one group is connected to the collector of transistor Q 20 through column Resistors R 28 through R 31 and the other group is connected to the collector of transistor Q 21 through Column Resistors R 32 through R 35 .
- Address line A 4 controls transistors Q 20 , Q 21 , and Q 22 such that Q 20 and Q 21 are a complementary pair that controls the enabling of the left four lines or the right four lines of the Storage columns. Since a Storage Column is otherwise disabled by applying a voltage to that line (through an Addressing Row and a Column addressing Rectifier) which results in a current equal to roughly the difference of the positive supply less 0.9 v divided by the Cathode Resistor value 1 M ⁇ (4.1 ⁇ A if using a 5 v supply), wherever a line can be disabled by cutting off the current through the Column Resistor, that much currert current will be saved. These savings will become significant in much larger arrays having a very large number of Storage Columns.
- the limit on the number of address lines that will control this type of power reducing means for enabling Storage Columns relates to the complexity of the circuit by increasing the number of transistors (a complex component) while reducing the number of rectifiers (a relatively less complex component).
- This same type of power saving enabling means could also be created on the Storage Rows by using PNP transistors to control the cutting off of current to those Storage Rows (through the Row Resistors).
- Another variation might be to use differently made components.
- silicon rectifiers having a forward voltage of about 0.7 v and transistors having base-emitter forward voltages also of about 0.7 v were assumed. But, other types of rectifiers and transistors could be used having lower or higher forward voltages.
- the Storage Rectifiers used could be the base-emitter junctions of NPN transistors (having all of their collectors tied together in the same way one would tie together the outputs of opened-collector gates in a logical AND configuration); this would make it possible to eliminate all of the Storage Bit Sensing Rectifiers, transistor Q 1 , resistor R 9 and rectifiers D 33 , D 34 and D 35 and instead sense the current sunk on the combined collectors.
- Storage Rectifier a base-emitter junction
- Other variations could include, memory cells comprising a fusible link resulting in a One Time Programmable Read Only Memory (OTPROM) device (see U.S. Pat. Nos. 4,312,046 and 4,385,368), or memory cells comprising charge-storage devices to create a Random Access Memory (RAM) device (see U.S. Pat. Nos. 3,626,389 and 3,838,405).
- OTPROM One Time Programmable Read Only Memory
- RAM Random Access Memory
- FIG. 12 shows a plot depicting the voltage/current relationship of a typical diode, where the horizontal axis is voltage, V, and the vertical axis is current, I. Moving right from the plot's origin, one can see that no significant current flows through the diode until the Forward Voltage, F, is reached. Moving left from the plot's origin, one can see that only a small amount of leakage current flows until the Reverse Breakdown Voltage, R, is reached. However, there is a region, A, between the origin and the point of the Reverse Breakdown Voltage where the device behaves similarly to a resistor.
- FIG. 13 shows a variation wherein the resistive means comprises diodes that are believed to operate in this resistor-like region.
- the diode biasing circuit, A (which would typically not be constructed as a part of an integrated circuit comprising the remainder of the circuit shown in this figure), comprises circuitry for biasing a row of diodes, H, in this resistor-like region for the row lines as well as circuitry for biasing a row of diodes, J, in this resistor-like region for the column lines. All of the diodes would be formed as a part of the same integrated circuit and would therefore have operating characteristics that are matched. On the row lines, the diodes, H, will be biased between the voltage of a disabled row and the voltage present at the output of the operational amplifier, B.
- the operational amplifier circuitry will ensure that the voltage across feedback diode D 102 will be the same as is across the diodes, H. As a result, the current through diodes, H, and diode D 102 will be the same as a result of the device matching. This is accomplished by pulling down point K in identical fashion to when pulling down any of the row address lines (A 0 through ⁇ A 2 ). This ensures that the voltage on the anode of diode D 103 will match the voltage on any one of the disabled row lines since an operational amplifier operates (as one skilled in the art knows) such that the same voltage will be present at the ‘+’ and ‘ ⁇ ’ terminals in normal feedback mode.
- FIG. 13 also shows a possible solution should the cumulative diode leakage currents in extremely large arrays of Storage Rectifiers become noticeable.
- An additional Addressing Row, N has been included. Notice this row has a rectifier connecting it to every one of the Storage Columns and that asserting this row by pulling it to the positive supply will disable the one remaining Storage Column that had been left enabled. As a result, it is believed that one could detect the presence of a Storage Rectifier at the point of intersection of the enabled Storage Row and Storage Column even with the existence of such leakage currents by sampling the level at the output both while asserting and not asserting this Addressing Row, N.
- Dual-addressed Rectifier Storage Arrays will typically be fabricated as an integrated circuit; a possible layout of the Rows, the Columns, and the rectifiers are shown in FIGS. 6 through 10 (the addressing transistors and resistors, the Row and Column Resistors, and the connection pads to the chip have been omitted for clarity—the fabrication of these devices are well known to those skilled in the art).
- FIG. 6 an N-type wafer is shown to be doped with P-type channels which form the Rows.
- FIG. 7 is shown that an oxide layer is grown and then ( FIG.
- FIG. 8 shows the chip with an aluminum metalization layer and finally ( FIG. 10 ) shows the result of etching that aluminum into vertical lines which form the Columns.
- a rectifier of the type sometimes referred to as a metal-on-silicon junction type or as a Schottky Diode type
- the N-type wafer substrate would be kept at the most negative voltage in the circuit thereby creating reverse biased p-n junction between the doped regions and the substrate, the result of which is to electrically isolate those generally parallel doped regions.
- the generally parallel metalized regions which form the Columns are electrically isolated from each other due to their being formed upon the non-conducting oxide layer (except where they contact the doped regions through the holes in the oxide layer).
- a metal-on-silicon junction rectifier is formed such that the current flow (where conventional current flow is the flow of holes, that is to say, current flowing from positive voltage potential to negative voltage potential) is from the doped regions to the metalized regions when the junction is forward biased.
- space is available for the manufacture of the addressing components and the Row and Column Resistive means at the lower left corner of the chip and around the edges.
- the addressing components might also be modified when constructing a DRS Array as an integrated circuit.
- the pair of resistors directly connected between each address input and the bases of the two addressing transistors could be replaced by a single resistor (as shown in FIG. 3 , a single resistor could do the job of resistors R 10 and R 12 , a single resistor could do the job of resistors R 13 and R 15 , and so on).
- Those transistors could be external to the integrated circuit form of the DRS Array.
- a variation on the semiconductor manufacturing of a DRS Array might be to dope N-type regions into a P-type wafer thereby reversing the polarity of the metal-on-silicon junction rectifiers (the Rows and the Columns would be reversed).
- Another variation would spread out the Addressing Columns across the width of the chip—alternating Addressing Columns with one or more Storage Columns—instead of grouping those Addressing Columns at the left side of the chip; this will spread out those Lines lines carrying most of the current in the circuit thereby more evenly distributing the power dissipation across the chip (the same technique could be done with the Rows).
- Another variation would be to construct the device with p-n junction rectifiers or a combination on metal-on-silicon junction rectifiers and p-n junction rectifiers.
- Another variation might enable programming the stored data during the metalization etching step.
- an opening has been etched through the oxide layer at every potential Storage Rectifier location.
- Programming of the stored data bits is accomplished when the metalization layer is etched.
- a metal connection is left during the metal etching step between the metal pad covering the opening in the oxide layer and the metal Column; where no storage Rectifier is desired, that metal connection is etched away. It is believed that this approach will enable all of the semiconductor manufacturing steps, except the final metal etching step to be performed and that wafers so made could be stored safely under the protective metalized layer. In this way, wafers could be mass produced without regard to the data to be stored in the chip.
- devices comprising DRS Arrays that are addressed via serially loaded counters By limiting the manufacture of devices comprising DRS Arrays that are addressed via serially loaded counters to analog output only, the same degradation of copies will occur thereby reducing some of the risks to the makers of programming by causing the copies to be less desirable than the originals. While devices comprising DRS Arrays that are addressed via serially loaded counters could be limited to analog output only, they could still include means for reading DRS Arrays in other formats (i.e., DRS Arrays directly addressed via many address lines), however, devices comprising DRS Arrays that are directly addressed via many address lines and which give digital access to the information stored therein would not include means for reading DRS Arrays that are addressed via serially loaded counters.
- the selection of a line by disabling all undesired lines could be utilized in many related electronic devices.
- the rectifiers at the storage locations could be fabricated as Light Emitting Diodes (LED's) with such a rectifier present at every storage location.
- LED's Light Emitting Diodes
- the device could be used as a display panel where a given display pixel could be turned on by selecting that bit location; the display panel would be scanned, selecting and illuminating bit locations in sequence while skipping bit locations that are to remain dark.
- pulse width modulation which is well known to one skilled in the art, one could even control the duration of a pulse of light emitted at any given pixel location and thereby control the perception of the intensity of the light emitted.
- the high expected storage densities come from the symmetry of the design—the Storage Bit Sensing Rectifiers, The the Addressing Rectifiers, and the Storage Rectifiers are all constructed in the same way. The result of this is that they can all be made at the same time with the same semiconductor manufacturing steps.
- metal-on-silicon junction rectifiers the primary components in the circuit are essentially constructed vertically on the semiconductor's surface instead of horizontally as might conventionally be done resulting in a very efficient use of the semiconductor “real estate”. The scaling up of the device is expected to be easily accomplished.
Abstract
Description
Claims (66)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/821,182 USRE41733E1 (en) | 1996-03-05 | 2001-03-29 | Dual-addressed rectifier storage device |
US11/780,220 USRE42310E1 (en) | 1996-03-05 | 2007-07-19 | Dual-addressed rectifier storage device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/610,992 US5673218A (en) | 1996-03-05 | 1996-03-05 | Dual-addressed rectifier storage device |
US08/863,156 US5889694A (en) | 1996-03-05 | 1997-05-27 | Dual-addressed rectifier storage device |
US09/821,182 USRE41733E1 (en) | 1996-03-05 | 2001-03-29 | Dual-addressed rectifier storage device |
Related Parent Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/610,992 Continuation-In-Part US5673218A (en) | 1996-03-05 | 1996-03-05 | Dual-addressed rectifier storage device |
US08/863,156 Reissue US5889694A (en) | 1996-03-05 | 1997-05-27 | Dual-addressed rectifier storage device |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/863,156 Continuation US5889694A (en) | 1996-03-05 | 1997-05-27 | Dual-addressed rectifier storage device |
US11/780,220 Continuation USRE42310E1 (en) | 1996-03-05 | 2007-07-19 | Dual-addressed rectifier storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE41733E1 true USRE41733E1 (en) | 2010-09-21 |
Family
ID=24447205
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/610,992 Expired - Lifetime US5673218A (en) | 1996-03-05 | 1996-03-05 | Dual-addressed rectifier storage device |
US09/821,182 Expired - Lifetime USRE41733E1 (en) | 1996-03-05 | 2001-03-29 | Dual-addressed rectifier storage device |
US11/780,220 Expired - Lifetime USRE42310E1 (en) | 1996-03-05 | 2007-07-19 | Dual-addressed rectifier storage device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US08/610,992 Expired - Lifetime US5673218A (en) | 1996-03-05 | 1996-03-05 | Dual-addressed rectifier storage device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US11/780,220 Expired - Lifetime USRE42310E1 (en) | 1996-03-05 | 2007-07-19 | Dual-addressed rectifier storage device |
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US (3) | US5673218A (en) |
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US7593256B2 (en) * | 2006-03-28 | 2009-09-22 | Contour Semiconductor, Inc. | Memory array with readout isolation |
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US20080013398A1 (en) | 2008-01-17 |
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