WO1980001220A1 - Three-dimensionally structured microelectronic device - Google Patents

Three-dimensionally structured microelectronic device Download PDF

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Publication number
WO1980001220A1
WO1980001220A1 PCT/US1979/001012 US7901012W WO8001220A1 WO 1980001220 A1 WO1980001220 A1 WO 1980001220A1 US 7901012 W US7901012 W US 7901012W WO 8001220 A1 WO8001220 A1 WO 8001220A1
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WIPO (PCT)
Prior art keywords
wafers
microelectronic device
wafer
dimensional
electric signal
Prior art date
Application number
PCT/US1979/001012
Other languages
French (fr)
Inventor
J Grinberg
A Jacobson
K Chow
Original Assignee
Hughes Aircraft Co
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Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Priority to DE7979901673T priority Critical patent/DE2967358D1/en
Publication of WO1980001220A1 publication Critical patent/WO1980001220A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a three-dimensional micro-electronic device structure and, particularly, to such -_a device in -which information is transferred through 5 stacked wafers interconnected with adjacent wafers with topological one-to-one correspondence.
  • Elements of present-day electronic digital compute transfer information through leads on a surface of a chi or a wafer to its edge and then through external leads to another wafer.
  • Such interconnections limit ' the numbe of channels of information, and result in very large physical size and power consumption with associated heat removal problems, high price, and relatively long inter ⁇ connections.
  • this type of architecture precludes the use of low power logic, which is too slow to be used in serially structured machines for high data rate applications. Power requirements are relatively high, also because the high freguency, long lines have t be low impedance (50 ohm) matched transmission cables.
  • the resultant system size is large because of its requir ments for printed boards, connector cables, packages and the like.
  • the price is high because of the high labor content of fabrication of and interconnections within printed circuit boards and packaging of the chips.
  • the present invention avoids or overcomes the abov problems by transferring information through stacked wafers, each of which is interconnected to its adjacent wafer with topological one-to-one correspondence.
  • Another object of the present inventi is to provide a means by which massive parallel computing channels (10 ⁇ or more) can be effected.
  • Another object of the present invention is to pro ⁇ vide for equivalent processing throughput which is 100 times higher than the fastest pipeline processors pre ⁇ sently known.
  • a further object of the present invention is to provide for significantly lower dissipated power than present computing devices.
  • Another object of the present invention is to permit the use of low power logic.
  • Still another object of the invention is to permit the use of high impedance, e.g., 10 kilo-ohms, short lines of less than one inch, for example, as compared to 50 ohms on conventional" high speed computers.
  • Another object of the invention is to provide for smaller sizes, e.g., 100 times smaller, than present computers. Another object of the present invention is to reduce the cost of microelectronic devices by reducing their labor content.
  • FIG. 1 is a view of a preferred embodiment of the present invention, depicting a basic block diagram of a three-dimensional microelectronic computer;
  • FIG. 2 illustrates one means by which a signal is fed through a wafer by using thermomigration technology
  • FIGS. 3-5 depict one means by which interconnections between wafers may be made with topological one-to-one correspondence
  • FIGS. 6 and 7 illustrate a modification of the interconnection means shown in FIGS. 3-5.
  • FIGS. 8a-8c illustrate means by which the inter- • connectrionsy-embodied-'as- microspringsy -may-be bricated.
  • OMPI /.. IPO constructing microelectronic computers to meet one of t most pr.essing needs in rapid data processing, i.e., the processing of two-dimensionally organized information.
  • the present invention as applied to digital com- puting," is .intended to reorganize the electronic digital processor from serial.to parallel architecture. In the new computer, many parallel channels, 10 or more, operate simultaneously on the data. This organization i more natural, and therefore more efficient,, for processi two-dimensional array data.
  • microelectronic wafers or chips whic are densely packed with circuits must be interconnected. Because each wafer requires a large number of connecting leads, the wafers are stacked against each other and the leads are interconnected from adjacent wafers with topo— logical one-to-one correspondence.
  • FIG. 1 A basic block diagram of a typical system is shown in FIG. 1 as a computer 10.
  • An input wafer 12 is, for example, a charge coupled serial-parallel CCD array which accepts serial electrical analog signals from input 14.
  • An analog-to-digital converter 16 converts the signal which is then supplied to a stack of logic wafers 18.
  • Conductor lines 20 extend through all the wafers and comprise data, address and control bus lines.
  • data lines 20a can number 10 to 10°, for example, and only relatively few (10 or so) serve address and control functions as shown by 20b, for example.
  • a stored program control unit 22 performs the control function and stores the software program.
  • the software program consists of address and control command
  • the program counter included in the control unit, reads out the appropriate address and control information into the address and control bus lines.
  • the address line 20b 1 addresses typically two wafers simultaneously, one from which the information is read out and the one to which
  • the control command determines the mode of operation of the written-in wafer. After the information has been processed on the wafer, it is similarly transferred to another wafer for process- ing or storage and so on. Each wafer is considered to be an independent station that can be addressed by means of the address lines.
  • the NxN information array is trans ⁇ ferred and processed in parallel.
  • An output wafer 24 serves as a serial-, digital input/output element. Pro- Completed information is read out through this element.
  • This unit is also useful for local processing control.
  • a mask of information can be introduced this unit, and then the mask can be transferred to any wafer by the bus lines. In this manner one can, for example, carry out locally different processing on different parts of the array information.
  • the output of the serial input/output unit can be transferred to- a process evaluation unit (not shown in FIG. 1).
  • This unit evaluates the process output and modi- fies the program stored in the control unit accordingly, or introduces a modified mask into the processor.
  • there is a digital feedback system which in near real-time modifies the programming according to image and evaluation data.
  • the use of massive parallel organization and storage of the entire image on the wafer eliminates memory cycling and increases the computational speed of this system.
  • the illustrated system has been compared to the faster digital computers utilizing semiconductor memory. It is assumed words will be processed in parallel, and bits in a word will be processed serially.
  • the system advantage for two-dimensional information analysis is high data-rate processing capability (ten to one hundred times faster), low power (by a factor of ten to one hundred times), high computation capability, and small weight and volume (by a factor of ten to one thousand times).
  • These features are mutually exclusive with present com ⁇ puter technology. Processing speeds in excess' of 10 instructions per second are required in typical applications for high altitudes surveillance, navigation, target identification or cueing, and tracking by model matching. Present com ⁇ puters cannot meet this requirement and appear unlikely to be able to come close to this speed in the foresee ⁇ able future.
  • the extensive parallelism of the present invention can provide the required throughput (10 ⁇ instructions per second or more). '
  • thermo- migration technology as depicted in FIG. 2, to transfer the electrical signal from one side of the wafer to the other.
  • thermomigration is the phenomenon of a liquid zone in the form of a droplet, a sheet, or a rod migrating in a solid along a thermal gradient.
  • the thermomigration of liquid droplets in solids can be understood as follows. A liquid droplet is embedded in a solid subjected to a thermal gradient. This thermal gradient causes the temperature on the
  • This dissolution process- was used to form one device of present invention utilizing liquid-aluminum droplets migrating up a thermal gradient in a crystal of n-type silicon.
  • the liquid droplets migrated as explained above:
  • thermomigration temperature the temperature at which bus lines through a thin silicon wafer is etched.
  • FIGS. 2a-2e The basic processing sequence of thermomigration f the implementation of bus lines through a thin silicon wafer is illustrated in FIGS. 2a-2e.
  • an array of holes 28 through a layer 32 of silicon dioxide (10 to 25 ⁇ in deep) was etched into a n-type silicon wafe 30 (FIG. 2). These holes were used to prevent the subse quent liquid zones from moving laterally on the silicon surface, and thus serve to preserve the registration and pattern of the deposited array.
  • the wafer was placed in the chamber of a metal evaporator where a laye of aluminum 34 was deposited (FIG. 2b).
  • the thickness o this aluminum layer is preferably approximately equal to the depth of the etched holes (FIG. 2).
  • excess aluminum was removed by grinding (FIG. 2c).
  • FIGS. 2a and 2b A slight modification of this process is presently preferred.
  • the steps depicted in FIGS. 2a and 2b have been eliminated. Instead, aluminum dots are placed on a base silicon wafer using standard lithographic techniques. No holes are etched.
  • the wafer was placed in an electron beam thermo ⁇ migration apparatus, which was designed to produce a very uniform vertical temperature gradient.
  • the radiation block was made of molybdenum, which is heated by an incident electron-beam. Radiation from the hot molybdenum block produces uniform heating of one face of the silicon wafer to a temperature of 1000 to 1200°C.
  • the wafer was suspended in a vacuum of 5 x 10 ⁇ 5 Torr and seated in a silicon sample holder.
  • the aluminum-evaporated side of the wafer faced the water-cooled copper block.
  • a tem ⁇ perature gradient of 10 to 100°C/cm was maintained between the two surfaces of the silicon bulk. Cylindrical radiation shields around the sample prevented unwanted radial gradients from developing in the wafer.
  • a silicon epireactor with helium or nitrogen cooling gas is now utilized.
  • the buried aluminum melted and alloyed with the silicon and then migrated up the thermal gradient, leaving behind.an array 38 of. heavily doped regions of p-type silicon forming the desired feedthrough part of the bus line.
  • P-type dots were then diffused as spots 40 at the end of -f edthrough lines 38. These dots 40 are sufficiently large to make contact with feed- throughs 38, which exhibit some random, rather than straight-line, migration through the wafer.
  • the preferred interconnect uses spring contacts, and is an outgrowth of the technology for the fabrication of miniature audio frequency tuning forks and beam lead crossovers.
  • These crossover-type spring contacts are fabricated so that th height of the tunnel underneath is sufficient to accommo date for the distortion across a wafer and permit comple interconnection of all the contacts in parallel.
  • the contacts may be batch-fabricated by either electroplatin or vacuum evaporation, and the process is compatible with silicon technology.
  • FIG. 3 The basic structure of a spring contact 50 is shown in FIG. 3..
  • the contact on one chip When fabricated on silicon chips, the contact on one chip is oriented at right angles to the contact on the other chip. Thus, when juxtaposed wafers 52 and 54 are mated, the springs make contact at right angles, as shown in FIG. 4, forming a cross 56.
  • This juxtaposition increases the probability of contact and ensures a more secure interconnection. Also, this arrangement accommodates maximum chip displacement while occupying minimum space on the silicon chip. This desig satisfies the need for reliable miniature contacts, even when the chips are distorted.
  • Another advantage of this type of contact is that the stack may be disassembled an the individual chips demounted. If desired, spacers 58 (FIG. 5) of photoresist, for example, may be secured to
  • the spring-contact concept originated in the technology for producing miniature tuning forks (tunis- . tors) and resonant gate transistors used in monolithic audio oscillators.
  • a similar technology known as the beam-lead crossover, was also developed at about the same time.
  • the basic fabrication process is the same in each case. The principal steps are shown in FIGS. 8a-8c.
  • a spacer 70 10 ⁇ M or more, thick is evapo ⁇ rated or electroplated onto a substrate 72 (FIG. 8a).
  • the spring contact 74 is evaporated or electro ⁇ plated on top of the spacer (FIG. 8).
  • the spacer is etched away, and a flexible microspring bridge 74a results (FIG. 8).
  • each microspring is also coated with a thin layer of indium. During the assembly of the wafer stack, the wafers are heated to near the melting point of indium and the two. microsprings will be bonded.

Abstract

A large scale parallel architecture in which many parallel channels operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stack integrated circuit wafers (16, 18) having top and bottom surfaces, electric signal paths (20) extending through each of the wafers between the surfaces, and micro-interconnects (50) on the surfaces of adjacent wafers interconnecting the respective electric signal paths with a topographical one-to-one correspondence.

Description

THREE-DIMENSIONALLY STRUCTURED MICROELECTRONIC DEVICE
TECHNICAL FIELD
The present invention relates to a three-dimensional micro-electronic device structure and, particularly, to such -_a device in -which information is transferred through 5 stacked wafers interconnected with adjacent wafers with topological one-to-one correspondence.
BACKGROUND ART Rapid advances in the science and technology of 10 microelectronics have led to a rapid growth in the power of digital computers, for example, in their ability to calculate and process data.. Even so, in recent years the increasing need for processing two-dimensionally organized data has out-stripped the power of the elec- 15 tronic digital computer in several important areas of application. These applications mainly involve near real¬ time machine processing of video, and wideband signals from radar or digitized infrared imagery, and solving multidimensional, non-linear parallel differential 20 equations governing such physical systems as meteorology
--' .--.and. aerodynamics;^ -For^examp-le "the enormous quantity of information on a single continuous-tone high-resolution photograph challenges the capabilities of even the larger- -present-day .electronic digital computers. As a result, 25 near real-time analysis of the multi-image input from video or infrared imaging systems exceeds the capabilities
OMPI * °\ of conventional serially organized electronic digital compute'rs.
Elements of present-day electronic digital compute transfer information through leads on a surface of a chi or a wafer to its edge and then through external leads to another wafer. Such interconnections limit'the numbe of channels of information, and result in very large physical size and power consumption with associated heat removal problems, high price, and relatively long inter¬ connections. For example, this type of architecture precludes the use of low power logic, which is too slow to be used in serially structured machines for high data rate applications. Power requirements are relatively high, also because the high freguency, long lines have t be low impedance (50 ohm) matched transmission cables.
The resultant system size is large because of its requir ments for printed boards, connector cables, packages and the like. The price is high because of the high labor content of fabrication of and interconnections within printed circuit boards and packaging of the chips.
SUMMARY OF THE INVENTION The present invention avoids or overcomes the abov problems by transferring information through stacked wafers, each of which is interconnected to its adjacent wafer with topological one-to-one correspondence.
It is, therefore, an object of the present inventi to provide a means by which massive parallel computing channels (10^ or more) can be effected. Another object of the present invention is to pro¬ vide for equivalent processing throughput which is 100 times higher than the fastest pipeline processors pre¬ sently known.
A further object of the present invention is to provide for significantly lower dissipated power than present computing devices.
f O Another object of the present invention is to permit the use of low power logic.
Still another object of the invention is to permit the use of high impedance, e.g., 10 kilo-ohms, short lines of less than one inch, for example, as compared to 50 ohms on conventional" high speed computers.
Another object of the invention is to provide for smaller sizes, e.g., 100 times smaller, than present computers. Another object of the present invention is to reduce the cost of microelectronic devices by reducing their labor content.
Other aims and objects as Well as a more complete understanding of the present invention will appear from the following explanation of the exemplary embodiments and the accompanying drawings thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view of a preferred embodiment of the present invention, depicting a basic block diagram of a three-dimensional microelectronic computer;
FIG. 2 illustrates one means by which a signal is fed through a wafer by using thermomigration technology;
FIGS. 3-5 depict one means by which interconnections between wafers may be made with topological one-to-one correspondence;
FIGS. 6 and 7 illustrate a modification of the interconnection means shown in FIGS. 3-5; and
FIGS. 8a-8c illustrate means by which the inter- •connectrionsy-embodied-'as- microspringsy -may-be bricated.
DESCRIPTION OF THE PREFERRED EMBODIMENT ._._.-__.- while--_he--pres-en-t- i-n7eτrtrion-has-general"appli¬ cability to any three-dimensionally structured micro¬ electronic device, it was developed primarily for use in
OMPI /.. IPO constructing microelectronic computers, to meet one of t most pr.essing needs in rapid data processing, i.e., the processing of two-dimensionally organized information. The present invention, as applied to digital com- puting," is .intended to reorganize the electronic digital processor from serial.to parallel architecture. In the new computer, many parallel channels, 10 or more, operate simultaneously on the data. This organization i more natural, and therefore more efficient,, for processi two-dimensional array data. To organize a digital com¬ puter in parallel, microelectronic wafers or chips, whic are densely packed with circuits must be interconnected. Because each wafer requires a large number of connecting leads, the wafers are stacked against each other and the leads are interconnected from adjacent wafers with topo— logical one-to-one correspondence.
A basic block diagram of a typical system is shown in FIG. 1 as a computer 10. An input wafer 12 is, for example, a charge coupled serial-parallel CCD array which accepts serial electrical analog signals from input 14. An analog-to-digital converter 16 converts the signal which is then supplied to a stack of logic wafers 18. Conductor lines 20 extend through all the wafers and comprise data, address and control bus lines. In this typical system, data lines 20a can number 10 to 10°, for example, and only relatively few (10 or so) serve address and control functions as shown by 20b, for example.
A stored program control unit 22 performs the control function and stores the software program. The software program consists of address and control command The program counter, included in the control unit, reads out the appropriate address and control information into the address and control bus lines. The address line 20b1 addresses typically two wafers simultaneously, one from which the information is read out and the one to which
f O the information is written in. The control command determines the mode of operation of the written-in wafer. After the information has been processed on the wafer, it is similarly transferred to another wafer for process- ing or storage and so on. Each wafer is considered to be an independent station that can be addressed by means of the address lines. The NxN information array is trans¬ ferred and processed in parallel. An output wafer 24 serves as a serial-, digital input/output element. Pro- cessed information is read out through this element.
This unit is also useful for local processing control. A mask of information can be introduced this unit, and then the mask can be transferred to any wafer by the bus lines. In this manner one can, for example, carry out locally different processing on different parts of the array information.
The output of the serial input/output unit can be transferred to- a process evaluation unit (not shown in FIG. 1). This unit evaluates the process output and modi- fies the program stored in the control unit accordingly, or introduces a modified mask into the processor. In this case, there is a digital feedback system which in near real-time modifies the programming according to image and evaluation data. The use of massive parallel organization and storage of the entire image on the wafer eliminates memory cycling and increases the computational speed of this system.
The illustrated system has been compared to the faster digital computers utilizing semiconductor memory. It is assumed words will be processed in parallel, and bits in a word will be processed serially. For 10 MHz clock rates for the three-dimensional computer, the system advantage for two-dimensional information analysis is high data-rate processing capability (ten to one hundred times faster), low power (by a factor of ten to one hundred times), high computation capability, and small weight and volume (by a factor of ten to one thousand times).. These features are mutually exclusive with present com¬ puter technology. Processing speeds in excess' of 10 instructions per second are required in typical applications for high altitudes surveillance, navigation, target identification or cueing, and tracking by model matching. Present com¬ puters cannot meet this requirement and appear unlikely to be able to come close to this speed in the foresee¬ able future. The extensive parallelism of the present invention can provide the required throughput (10 ϋ instructions per second or more).'
There are two basic requirements for implementing the three-dimensional computer system. It requires a feedthrough of electrical signals from one side of the wafer to the other while preserving the spatial modula¬ tion of the signal. It must be fast and work equally well in both directions, and must provide a means of interconnecting the wafers in a stack.
While it is possible to etch holes through wafers to overcoat the holes with an insulating layer and electroplate conductive materials on the wall of the bore of holes, the preferable approach employs thermo- migration technology, as depicted in FIG. 2, to transfer the electrical signal from one side of the wafer to the other.
Prior work in other laboratories has shown the effects of thermomigration. Thermomigration is the phenomenon of a liquid zone in the form of a droplet, a sheet, or a rod migrating in a solid along a thermal gradient. The thermomigration of liquid droplets in solids can be understood as follows. A liquid droplet is embedded in a solid subjected to a thermal gradient. This thermal gradient causes the temperature on the
OMPI forward' droplet interface to be higher than the' tempera¬ ture on the rear droplet interface. Since- the. solubility • of a solid in a liquid increases with temperature, the concentration of dissolved solid atoms is higher in the liquid at the hotter forward interface of the droplet than in the liquid at the cooler rear interface of the droplet. This inequality in concentration produces a concentration gradient of dissolved solid atoms across the liquid droplet. This concentration gradient, in-
10 turn, generates a flux" of dissolved solid atoms down the concentration gradient from the front to the rear interface of the liquid droplet. To feed this diffusion flux, additional solid atoms dissolve into the liquid at the forward hot face of the droplet while dissolved
15 solid atoms deposit on the cold rear face of the droplet. • As a consequence, the liquid droplet moves forward up the thermal gradient in the solid by dissolving the solid at its front, passing the atoms or molecules of the solid through itself to its rear, and redepositing these atoms
20 behind itself.
This dissolution process-was used to form one device of present invention utilizing liquid-aluminum droplets migrating up a thermal gradient in a crystal of n-type silicon. The liquid droplets migrated as explained above:
£"5J solid silicon dissolved into the liquid aluminum at the forward, hotter interface of the droplet, the dissolved silicon atoms were transported through the intervening liquid, and the same silicon atoms were redeposited on the rear, cooler interface of the liquid aluminum droplet.
30 At..the.rear..face.,,of- the..-drople.t.,-...tra.ce....amounts.of aluminum up to the solid solubility limit of aluminum in solid silicon at the migration temperature were incorporated in..the..redeposited silicon......The_-disso..lve.d._aluminum. a.toms doped the redeposited silicon in the trail behind the
35 droplet with a p-type conductivity, thereby forming a highly conductive channel which is insulated from, the bulk by- a p-n junction.
Such wafer feedthroughs' are based on developments by Thomas R. Anthony^and Harvey E. Cline of the General Electric Company. Known patents of these two parties include U.S. Patents, 3,895,967; 3,898,106; 3,899,361; 3,899,362; 3,901,736; 3,902,925; and 3,904,442, all date in the months of July-September, 1975. Publications include the following: Journal of Applied Physics, Vol. 43, No. 11, November 1972, pages 4391-4395; IEEE Transactions on Electron Devices, Vol. ED-23, No. 8, August 1976, pages 818-823; Journal of Applied Physics, Vol. 47, No. 6, June 1976, pages 2316-2336 and 2550- 2557; Journal of Applied Physics, Vol. 48, No. 6, June 1977, pages 2196-2201; Applied Physics Letters,
Vol. 31, No. 2, 15 July 1977, pages 125-126; and Journal of Applied Physics, Vol. 48, No. 9, September 1977, page 3943-3949.
The specific experimental setup used for ther o- migration processing and the important physical paramete of the process such as thermomigration temperature, drop size, effect of crystallographic orientation, random wal displacement, and required thermal gradient are as follo The basic processing sequence of thermomigration f the implementation of bus lines through a thin silicon wafer is illustrated in FIGS. 2a-2e. First, by using co ventional photolithography and etching techniques, an array of holes 28 through a layer 32 of silicon dioxide (10 to 25 μin deep) was etched into a n-type silicon wafe 30 (FIG. 2). These holes were used to prevent the subse quent liquid zones from moving laterally on the silicon surface, and thus serve to preserve the registration and pattern of the deposited array. Next, the wafer was placed in the chamber of a metal evaporator where a laye of aluminum 34 was deposited (FIG. 2b). The thickness o this aluminum layer is preferably approximately equal to the depth of the etched holes (FIG. 2). Next, excess aluminum was removed by grinding (FIG. 2c). The array of 34a of aluminum dots, half buried in the surface of the silicon, wask then ready for thermomigration processing (FIG. 2d).
A slight modification of this process is presently preferred. The steps depicted in FIGS. 2a and 2b have been eliminated. Instead, aluminum dots are placed on a base silicon wafer using standard lithographic techniques. No holes are etched.
The wafer was placed in an electron beam thermo¬ migration apparatus, which was designed to produce a very uniform vertical temperature gradient. The radiation block was made of molybdenum, which is heated by an incident electron-beam. Radiation from the hot molybdenum block produces uniform heating of one face of the silicon wafer to a temperature of 1000 to 1200°C. The wafer was suspended in a vacuum of 5 x 10~5 Torr and seated in a silicon sample holder. The aluminum-evaporated side of the wafer faced the water-cooled copper block. A tem¬ perature gradient of 10 to 100°C/cm was maintained between the two surfaces of the silicon bulk. Cylindrical radiation shields around the sample prevented unwanted radial gradients from developing in the wafer. It is also presently preferred that, instead of using the vacuum thermomigration system, a silicon epireactor with helium or nitrogen cooling gas is now utilized. As shown in FIG. 2d, the buried aluminum melted and alloyed with the silicon and then migrated up the thermal gradient, leaving behind.an array 38 of. heavily doped regions of p-type silicon forming the desired feedthrough part of the bus line. P-type dots were then diffused as spots 40 at the end of -f edthrough lines 38. These dots 40 are sufficiently large to make contact with feed- throughs 38, which exhibit some random, rather than straight-line, migration through the wafer.
OMPI /», WIPO The fabrication of .chip interconnections is the. second major technological development required for the
3-dimensional computer. The very large number of contac (10 4 to 108) imposes the need for high reliability and small contact dimensions. Also, any proposed intercon¬ nection technique must be compatible with wafers that ar somewhat dist rted. The concept, of a bus that .passes through all wafers in the stack requires that the contac have low capacitance, have low resistivity, and be' independent of polarity and orientation.
The preferred interconnect, as depicted in FIGS. 3-8, uses spring contacts, and is an outgrowth of the technology for the fabrication of miniature audio frequency tuning forks and beam lead crossovers. These crossover-type spring contacts are fabricated so that th height of the tunnel underneath is sufficient to accommo date for the distortion across a wafer and permit comple interconnection of all the contacts in parallel. The contacts may be batch-fabricated by either electroplatin or vacuum evaporation, and the process is compatible with silicon technology.
The basic structure of a spring contact 50 is shown in FIG. 3.. When fabricated on silicon chips, the contact on one chip is oriented at right angles to the contact on the other chip. Thus, when juxtaposed wafers 52 and 54 are mated, the springs make contact at right angles, as shown in FIG. 4, forming a cross 56. This juxtaposition increases the probability of contact and ensures a more secure interconnection. Also, this arrangement accommodates maximum chip displacement while occupying minimum space on the silicon chip. This desig satisfies the need for reliable miniature contacts, even when the chips are distorted. Another advantage of this type of contact is that the stack may be disassembled an the individual chips demounted. If desired, spacers 58 (FIG. 5) of photoresist, for example, may be secured to
O Λ, I and between adjacent wafers 52 and 54 to limit spring deformation and prevent crossing contacts from being squashed. Greater numbers of contacts may be used, as illustrated in FIGS. 6 and.7, showing contact structures 60 and 62.'
The spring-contact concept originated in the technology for producing miniature tuning forks (tunis- . tors) and resonant gate transistors used in monolithic audio oscillators. A similar technology, known as the beam-lead crossover, was also developed at about the same time. The basic fabrication process is the same in each case. The principal steps are shown in FIGS. 8a-8c. First, a spacer 70 10 μM or more, thick is evapo¬ rated or electroplated onto a substrate 72 (FIG. 8a). Then the spring contact 74 is evaporated or electro¬ plated on top of the spacer (FIG. 8). Finally, the spacer is etched away, and a flexible microspring bridge 74a results (FIG. 8). To secure the contact between two microsprings, each microspring is also coated with a thin layer of indium. During the assembly of the wafer stack, the wafers are heated to near the melting point of indium and the two. microsprings will be bonded.
Although the invention has been described with reference to particular embodiments thereof, it should be realized that various changes and different embodi¬ ments or modifications may be made therein without departing from the spirit and scope of the invention.
"&ϋREA
OMPI
/*.___ IPO *

Claims

What is1 Claimed is:
, ■ • . 1. A three-dimensional microelectronic device
'2 comprising a.plurality of stacked integrated circuit waf
3 having top and bottom surfaces, electric signal paths
4 extending through .each of said wafers between the surfac
5 and means on the surfaces of adjacent wafers interconnec
6 ting their respective electric signal paths with a
7 topological one-to-one correspondence into an electronic"
8 function.
1 2. A three-dimensional microelectronic device
2 according to Claim 1 in which said electric signal paths
3 comprise data bus lines interconnecting individual elec-
4 tronic functions of said wafers into the electronic
5 function.
1 3. A three-dimensional microelectronic device
2 according to Claim 2 in which said electric signal paths
3 comprise trails defined by thermomigration of metal
4 droplets through each of said wafers.
1 4. The three-dimensional microelectronic device
•2 according to Claim 3 in which said wafers comprise silico 3 and said metal trails comprise aluminum. 5. The three-dimensional- microelectronic device according to Claim 2 in which the individual electronic functions comprise two dimensionally arrayed computing cells and said data bus lines comprise 10 to 10° chan- nels operating simultaneously on .the data for processing thereof, and said contacts are paired ih one equivalent 102 to 106 number.
6. The three-dimensional microelectronic device according to Claim 5 in which all computing cells and one of s.aid wafers are identified for processing data bit planes.
7. The three-dimensional microelectronic device according to Claim 6 in which said bus lines comprise three types including address, control and data bus lines in which the address and control bus lines are activated by a control unit external to said stacked wafers, the address determining all computing cells on one of said wafers, in which the control lines determine the mode of operation of said addressed wafer, an array of data being transferred forth and back, from wafer-to-wafer within said stack to accomplish each time an elementary computing step.
i*k β
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EP0020665A1 (en) 1981-01-07
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GB2049280A (en) 1980-12-17
DE2967358D1 (en) 1985-02-28
EP0020665A4 (en) 1982-04-22
EP0020665B1 (en) 1985-01-16
JPH0468667B2 (en) 1992-11-04

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