WO1988010012A1

WO1988010012A1 - Semiconductor device

Info

Publication number: WO1988010012A1
Application number: PCT/GB1988/000442
Authority: WO
Inventors: Anthony Alan Lane
Original assignee: Plessey Overseas Limited
Priority date: 1987-06-09
Filing date: 1988-06-06
Publication date: 1988-12-15
Also published as: GB2206235A; GB8813305D0; GB2206235B; JPH02500236A; EP0316397A1; GB8713403D0

Abstract

A semiconductor switching element including a FET and transmission line (11, 13) whereby the transmission line is mounted around the active channel (15) of the FET with a gate electrode stripe (17) therebetween. The transmission line (11, 13) is thus capable of being short-circuited to earth by application of a suitable electrical potential to the gate electrode. This allows construction of a microwave phase shift circuit which makes maximum use of the available area of semiconductor material.

Description

SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device and more specifically but not exclusively to such a device which can act as a microwave phase shift circuit.

When making use of an aerial that can be electronically scanned, it is essential in order to effect a precise beam forming operation to be able to achieve accurate phase shifts of the signal passing through the aerial.

The apparatus and techniques used at present for phase shift circuits for microwave signals are for the most part adaptations of designs used in lower frequency communication apparatus such as for radio. These designs because of the relatively low frequencies involved do not take a full account of the contributions of stray capacitance and inductance effects. However, with higher frequency microwave radiated signals these stray capacitance and inductance effects become highly important to the whole function of the apparatus. Some practical designs in use at the present time are in fact dependent upon the presence of parasitic or stray signal effects to achieve an effective working operation of the device.

Gallium arsenide (GaAs) along with other Hl-V type semiconductor materials such as indium phosphide can be useful in microwave switching applications because of their capability of high switching speeds. However these materials are costly and consequently the available area must be carefully employed with these devices in order to make full use of the material. A phase shift circuit derived from a lower frequency design thus may tend not to maximise use of the semiconductor material. Additionally, some of those prior devices have been provided with a transmission line topography involving adequate spacing of the lines to prevent inductive coupling etc. and have included bends in the length of the transmission lines. These factors can make determination of "effective" electrical properties difficult and they may in addition introduce phase shift errors due to the presence of unequal transmission line lengths. It is an object of the present invention to provide a device in which some of those problems are reduced.

According to one embodiment of the invention, there is provided a semiconductor switching element capable of causing a phase shift in a signal which is applied to said element, the element comprising a Metal Semiconductor Field Effect Transistor (FET) having a first ohmic track electrode and a second ohmic track electrode serially connected by an ohmic electrode bridge to form a transmission line for transmission of the signal, the transmission line being arranged adjacent to an active channel region and a gate electrode of the transistor, the gate electrode being arranged for coupling to a suitable electrical potential source whereby the active channel region is controllable such that a predetermined phase shift is applied to the signal upon transmission through the transmission line. An embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings in which:- Figure 1 illustrates a typical prior phase shift circuit diagram with semiconductor devices and inductive transmission lines;

Figure 2 is a plan of a practical embodiment of part of the circuit illustrated in Figure 1 ; Figure 3 shows symbolic representations of phase shift circuits adaptable for 22.5°, 45° and 90° phase shifts;

Figure 4 shows symbolic representations of phase shift circuits adaptable for a 180° phase shifts;

Figure 5 is a plan view of a phase shift circuit element according to the present invention;

Figure 6 is a plan view of a practical embodiment of the element illustrated in Figure 5;

Figure 7 is a plan view of the embodiment illustrated in Figure 5 used in a loaded line type arrangement; and, Figure 8 illustrates in plan view several elements as illustrated in Figure 5 arranged in a delay line phase shift arrangement.

Typical prior phase shift circuits as shown in Figure 1 comprise several switching devices such as Metal Semiconductor Field Effect Transistors (MESFET) (a) and (b) arranged to switch in phase sequence on an incoming wave signal between effective high and low pass filter arrangements. The MESFETs (a) and (b) are arranged to work in antagonistic sets wherein when MESFETs (a) are in operation the MESFETs (b) are "pinched-off" or inoperative and vice-versa. By using this phased switching sequence the incoming wave signal has its phase shifted. The circuit can be considered as four distinct areas or elements (1 ,4,6, and 8). Areas 4 and 6 comprise a MESFET (a) with a parallel capacitance C connected across the source and drain electrodes at the MESFET (a), these elements receive the incoming signals through an input port 2 and output the shifted signals at an output port 10 respectively and are located before and after a switching area 1. The area 8 comprises a MESFET (b) and a parallel arrangement of a MESFET (a) and an inductance L2 both anchored to electrical earth. The switching area 4 comprises a MESFET (b) (denoted 3) and two equal lengths of transmission line 5 with a connection to area 8 therebetween.

These prior phase shift circuits as illustrated in Figure 1 are usually constructed with GaAs Metal Semiconductor Field Effect Transistor (MESFET) devices arranged to switch between low and high pass filter arrangements. At the centre of each shift circuit there is the area 1 comprising a MESFET 3 and two equal lengths of transmission line 5. The difficulties encountered in designing such circuits arise when the parasitic values of the components are taken into consideration. The presence of parasitic or stray capacitance and inductance effects can make modelling of the circuit difficult. Additionally, these prior designs tend to have a highly distributed layout and thus do not make full use of the available area of costly GaAs material. In addition, the required inductor value may be too small to be capable of being constructed in the form of a monolithic microwave integrated circuit.

If the MESFETs (a) are placed in a "pinched off condition and MESFETs (b) in an "ON" condition that is, with zero gate bias, the circuit shown in Figure 1 approximates to a high pass filter arrangement. Conversely with MESFETs (a) in an "ON" condition with zero gate bias and MESFETs (b) in the "pinched off" condition then the circuit of Figure 1 approximates to a low pass filter arrangement. It is by switching between these two states that a shift operation is achieved.

With the circuit of Figure 1 in the high pass state, the insertion loss must be low consequently the reactance of the capacitances should be low (high capacitance) while the reactance of the inductor L₂ should be high (high inductance). In the low pass state, the reactance of the inductors Li should be low (low inductance) while the reactance of the MESFETs (a) should be high (low capacitance). The only method of achieving this low inductance of Li is by having a short length of transmission line. The area 1 at the centre of the phase shift circuit (Figure 1) being a MESFET shunted by two equal lengths (electrically) of transmission line.

In Figure 2 the transmission lines ,7 and 9 illustrate that in a practical application of the circuit of Figure 1 the transmission lines

(7,9) must be spaced and include bends to facilitate construction along with reducing inductive electrical coupling between the lines. This topography of transmission lines (7,9) makes electrical analysis of the circuit difficult while an accurate determination of effective electrical lengths of transmission lines is necessary to achieve adequate phase shift performance.

The phase shift circuits can be realised as high pass low pass "T" networks for 22.5°, 45° and 90° phase bits as . seen in Figure 3 while 180° phase shifts are realised as inverted "L" "T" networks (Figure 4).

With prior phase shift arrangements it has been difficult to achieve small phase shifts (less than 45° ) using "T" networks due to the effects of the parasitic capacitance and inductance associated with the components which comprise the circuit. The semiconductor device of the present invention utilises the parasitic capacitance and inductance effects by combining two passive circuit elements, that is the transmission lines with a MESFET device. This allows a circuit to be constructed which has a phase bit as low as 22.5°.

A summary of the root mean square (rms) phase errors and average insertion losses can be seen in the table below.

TABLE Average insertion losses and rms phase errors for phase shift circuits

Phase setting Average Insertion Loss Rms phase error

/degrees - /dB

/degrees

22.5 1.4 1.5 45 1.4 0.6

90 2.3 1.4

1 80 3.0 6.5

The combination of a MESFET and the transmission lines into a continous FET (CFET) as shown in Figure 5 illustrates the present invention. The design reduces the effects of the parasitics hereby improving radio frequency performance while allowing high circuit packing densities to be achieved. This can economise on the valuable GaAs area permitting a lower unit production cost with higher manufacturing yields.

The combination of a MESFET and the transmission line into a continuous FET (CFET) as shown in Figure 5 illustrates the present invention. The CFET is constructed though depositing two parallel layers or tracks (11, 13) of metalisation on to an "active" GaAs area or mesa 15. With a gate stripe 17 placed between the two tracks (11,13) it is possible to control the resistance of the GaAs area 15 channel by application of a potential to the gate stripe 17. If two adjacent ends of the tracks (11,13) are connected by a bridge 19 then a functional transmission line is formed. This transmission line (11,19,13) may be short circuited, that is with zero current passing through the transmission line, by the active GaAs mesa 15 when zero potential is applied to the gate stripe 17. However, when a negative potential of sufficient magnitude to deplete the active region of carriers in the GaAs mesa 15 is applied to the gate stripe 17 the transmission line (11,19,13) becomes operative.

Figure 6 illustrates the CFET of the present invention inserted into a practical circuit arrangement as mentioned previously in the description relating to Figure 5.

As will be appreciated, the CFET can be accommodated on a much reduced surface area of GaAs consequently substantial cost savings can be made.

It will be seen that the disclosed CFET has a symmetrical layout without the need to include specific transmission line bends or a suitable line spacing to avoid electrical coupling. Consequently, apart from making a more efficient use of surface area as indicated above this layout allows a more accurate determination of "effective" electrical path lengths and thus a greater consistency in the phase shifting operation.

It will be understood by the man skilled in the art that by altering the length of the CFET in conjunction with the capacitance and inductive values phase shift circuits of differing degree can be constructed.

The CFET of the present invention may also be used in a loaded line application as shown in plan view in Figure 7. The metallised tracks (31,33) have capacitance C areas attached to their length though integrated circuit layer inter-connective vias or paths such that the effective lengths of the tracks are enhanced consequently surface area can be saved.

Figure 8 illustrates a further application of the present CFET in a switched delay line phase shift circuit where several delay lines (51, 53, 55) of varying transmission length can be switched to alter the operating characteristics of the circuit. Alternatively the CFET could be used in a voltage controlled filter where the potential applied to the transmission lines may allow alteration of the filter pass characteristic.

Although the use of III-V material has been specifically described in this embodiment it will be appreciated that alternative suitable materials may be used such as indium phosphide or silicon- on-sapphire. Whilst the embodiment herein described relates to "normally- off ^* MESFET devices it will be appreciated that "normally-on" MESFET devices may alternatively be used.

Claims

1. A semiconductor switching element capable of causing a phase shift in a signal which is applied to said element, the element comprising a Metal Semiconductor Field Effort Transistor (FET) having a first ohmic track electrode and a second ohmic track electrode serially connected by an ohmic electrode bridge to form a continuous transmission line for transmission of the signal, the transmission line being arranged adjacent to an active channel region and a gate electrode of the transistor, the gate electrode being arranged for coupling to a suitable electrical potential source whereby the active channel region is controllable such that a predetermined phase shift is applied to the signal upon transmission through the transmission line.

2. A semiconductor switching element is claimed in claim 1 wherein the transmission line is a continuous length of metalisation.

3. A semiconductor switching element as claimed in claim 1 or 2 wherein the first ohmic track electrode and the second ohmic track electrode are respectively a drain electrode and a source electrode for the transistor.

4. A semiconductor switching element as claimed in claim 1 , 2 or 3 wherein the device is formed upon a substrate of gallium arsenide. 5. A semiconductor switching element as claimed in any proceeding claim wherein the predetermined phase shift is either 22.

5° or 45° or 90° or 180°.

6. A semiconductor claim wherein at least one capacitive via is attached to the transmission line whereby its effective length for the predetermined phase shift is enhanced.

10. A semiconductor switching element substantially as hereinbefore described with reference to figures 5 to 8 of the accompanying drawings.

7. A semiconductor switching element as claimed in any proceeding claim wherein the electrical potential source applies a fixed electrical potential to the gate electrode.

8. A semiconductor switching element as claimed in any of claims 1 to 6 wherein the electrical potential source applies a variable electrical potential to the gate electrode whereby the electrical potential applied my be varied to provide a variable filter pass characteristic for the switching element.

9. An assembly of semi-conductor switch elements as claimed in any proceeding claim wherein each element Is serially connected and operated by a control potential applied to it's gate electrode.