WO1989010667A1 - High capacity communication system utilizing or-type channels - Google Patents
High capacity communication system utilizing or-type channels Download PDFInfo
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- WO1989010667A1 WO1989010667A1 PCT/US1989/001668 US8901668W WO8910667A1 WO 1989010667 A1 WO1989010667 A1 WO 1989010667A1 US 8901668 W US8901668 W US 8901668W WO 8910667 A1 WO8910667 A1 WO 8910667A1
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- 238000004891 communication Methods 0.000 title abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 55
- 238000012545 processing Methods 0.000 claims abstract description 36
- 238000012544 monitoring process Methods 0.000 claims abstract description 8
- 239000002131 composite material Substances 0.000 claims abstract description 7
- 230000001360 synchronised effect Effects 0.000 claims abstract description 7
- 230000004044 response Effects 0.000 claims abstract description 5
- 230000000644 propagated effect Effects 0.000 claims abstract description 4
- 230000009471 action Effects 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 5
- 230000001902 propagating effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 25
- 230000005540 biological transmission Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- CNQCVBJFEGMYDW-UHFFFAOYSA-N lawrencium atom Chemical compound [Lr] CNQCVBJFEGMYDW-UHFFFAOYSA-N 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/427—Loop networks with decentralised control
Definitions
- This invention relates generally to a multiple access communication network wherein a plurality of transmission channels interconnect numerous distributed stations and, more specifically, to a methodology and associated systems for effecting high capacity and low delay interstation communication over OR-type channels.
- a conventional configuration for a communication network is one wherein a plurality of stations are interconnected by a common transmission medium or channel, and messages are exchanged among the stations on a time- shared basis over the channel.
- a so-called conflict situation arises whenever multiple stations require use of the channel at the same instant.
- methods and concomitant arrangements exist for dealing with conflicts and these vary in complexity from simple, fixed priority techniques to sophisticated code division multiple access procedures.
- the type of communication network is referred to as a Carrier Sensed Multiple Access (CSMA) network.
- CSMA Carrier Sensed Multiple Access
- CSMA/CD CSMA with Collision Detection
- the CSMA/CD method is discussed in detail in the text entitled “Carrier Sensed Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications", published by The Institute of Electrical and Electronic Engineers, Inc. ' in 1985) .
- CSMA/CD Carrier Sensed Multiple Access with Collision Detection
- each transmitting station intentionally sends additional bits to ensure propagation of the collision throughout the system.
- the stations then deactivate for a random time period, called the backoff time, before attempting to transmit again. This process continues until only a " single message propagates collision-free over the channel.
- this technique is somewhat inefficient due to station deactivation during the backoff periods and the random nature of the retry process. From another 0 viewpoint, if a normalized efficiency per transmission period is defined as the ratio of the time utilized for information-bearing message transfer to the total time period, then the efficiency is less than unity for conventional contention resolving systems.
- each device compares the bus content bit-by-bit and then either terminates or continues its transmission according to the results of the comparison.
- the time required to resolve a contention is fixed by the number of bits assigned to the interrupt numbers.
- this time is deterministic, there is still a period in which no actual information-bearing messages may be transmitted and the normalized efficiency is less than one.
- None of the conventional techniques disclose or suggest a methodology for always achieving the optimum normalized throughput efficiency as defined above. Moreover, none of the conventional methods suggest the utilization of more than one channel or bus to resolve or even eliminate contention situations.
- the general method for a given bit interval commences by identifying candidate messages and assigning each of the candidates to selected ones of the lines.
- a candidate message is defined by the prefix or initial bit positions of the message, that is, only the revealed portion of the message up to the given bit interval under consideration.
- An encoding algorithm for this dynamic allocation process is used to effect the identification and assignment steps.
- a logic signal emanates from each of the active stations according to the logic level of the bit in the given interval.
- the logic signal from each station is associated with only one of the selected lines.
- each station monitors the composite signal levels on all the lines. This composite signal serves as input to the algorithm so that new collections for the next succeeding bit interval may be prepared.
- the candidates existing after the last bit interval has been processed determine the transmitted messages.
- a seminal feature of the communication system in accordance with the invention is that its throughput achieves 100 per cent of the combined channel capacity in the sense of the following two properties. If L denotes the number of channels or parallel lines, then:
- FIG. 1 is a representation of a multiple access communication system wherein a plurality of OR-type channels interconnect numerous, geographically-disbursed stations;
- FIG. 2 depicts an exemplary set of frames prepared as candidate messages for propagation over the plurality of channels shown in FIG. 1;
- FIG. 3 indicates how both the opening and closing phases overlay on the present and next frame messages in order to minimize system throughput delay;
- FIGS. 4-11 summarize, for an illustrative example, the assignment of the prefixes to the various communication lines during consecutive bit intervals in the opening phase of the transmission process in accordance with the present invention
- FIG. 12 summarizes the assignment of candidate messages to the various lines during the first bit interval in the closing phase of the illustrative example
- FIGS. 13 summarizes the assignment of candidate messages to the various lines during the last bit interval in the closing phase of the the illustrative example
- FIGS. 14 summarizes the prefixes tested and dropped during illustrative bit intervals in the transmission process
- FIG. 16 is a snapshot of the memory layout of FIG. 15 for bit interval 11 of the illustrative example;
- FIG. 17 is a flow diagram showing the processing steps executed by the encoder in accordance with the present invention.
- FIGS. 18 and 19 are flow diagrams showing the processing steps executed by the decoder in accordance with the present invention. Detailed Description
- FIG. 1 An illustrative embodiment in accordance with the present invention may be represented in general form by the block diagram of FIG. 1.
- an OR-type channel will be simply called a line.
- the article entitled "Performance Comparison of Explicit and Implicit Token-Passing Networks,” by O. C. Ibe as published in Performance, Vol. 10, No. 2, April, 1987 is incorporated herein by reference.
- FIG. 1 it is supposed that nine synchronized stations S.-Sg are coupled to eight lines 111-118; S.
- each station communicates via ten-bit message frames; an exemplary set of frames for the stations is shown in FIG. 2.
- the frame size is designated by F and the number of lines is given by L.
- the messages shown in FIG. 2 are first arranged in ascending order according to their binary values and then the stations are assigned accordingly. This simplifies the description but is not required in general.
- the decimal value corresponding to the binary representation of each of the frames is also given in FIG. 2.
- a short hand notation is to refer to a frame message by its decimal equivalent value.
- the transmission process comprises two phases, designated the opening phase and closing phase, respectively.
- the opening phase encompasses all F bits in a frame.
- the closing phase requires log 2 L-l additional NOT TAKEN INTO CONSIDERATION
- bit position log,L up through bit position F
- certain encoding activities such as WRITE and then immediate READ activities as discussed shortly, occur within each bit propagation interval.
- each station monitors the composite state of each line and determines whether a logic 0 or a logic 1 appears on each line.
- a 'Y' in the READ column means a logic 1 signal is on the line, whereas a 'N' indicates a logic 0 state.
- Lines 0, 3 and 5 have logic 1 states for this example.
- Line 0 carries the prefix of messages '34' and '56';
- Line 3 captured the prefix of messages '386', '402' and '438'; and
- Line 5 propagates the prefix for messages '650', '652', '709' and '733'.
- collection C Q _ is composed of the prefix 000;
- collection C- 3 has prefix Oil;
- collection C» 3 has prefix 101.
- prefix 000 of the first collection engenders the two prefixes 0000 and 0001. If any station has a message with the prefix 0000, the station writes a logic 1 on Line 0. ' Similarly, any station having a message with prefix 0001 writes a logic 1 on Line 1.
- the other two collections of prefixes are processed in a similar manner simultaneously with the first collection. It should be noted that the collections may be assigned to different lines than the lines upon which the collections were originally detected. The algorithm to effect this reassignment is known by all stations and will be discussed shortly.
- Lines 6 and 7 had no messages assigned to them because the number of collections at the start of the fourth bit interval was less than one-half the number of lines, and the collections were only split in half.
- FIG. 6 summarizes the unfolding process during the propagation of the fifth bit.
- prefix 0000 from the last detected bit position gives rise to prefixes 00000 and 00001.
- the other prefixes fostered by the prior collections are also depicted on FIG. 6.
- the association of the prefixes with their assigned lines is also identified. Because there are four collections at the beginning of the bit propagation interval, and each is split into two parts, all eight lines are utilized at this stage of the process. Any station with a message having the corresponding prefix places a logic 1 on the appropriate line and then monitors for the status of all the lines. At the end of the monitoring process, five collections have been identified.
- the message chosen to be traced is message '650' (1010001010) transmitted by station S g . From FIG. 7 it may readily be deduced that message '650' is in collection C_ 5 at the start of the sixth bit interval. Since the number of collections is more than half the number of lines, each collection is assigned to only one line. Thus collection C Q5 is assigned to Line 0, collection C 15 is assigned to Line 1, and so on. Finally, the pool is assigned to the remaining lines, namely. Lines 5, 6 and 7.
- the prefix 10100 in collection C 35 engenders the two prefixes 101000 and 101001. In order to distinguish between these two prefixes, only those messages having the latter prefix write a logic 1 on the assigned line, namely. Line 3. In this case, no message has a prefix 101001, so during the READ interval, this line yields a 'N' . Since it is already known that there is a message with prefix 10100 and Line 3 yielded a 'N', this implies that there is a collection consisting of the prefix 101000 at the end of the sixth bit interval. (A case where a logic 1 is written on a line is exemplified by collection C Q5 on Line 0.
- Message '56' has prefix 000011, so a logic 1 is written on Line 0 during the WRITE phase of bit interval 6. It is also possible that some prefixes neither belong to any collection nor are eliminated. Such prefixes are lumped into the special collection or pool, which is denoted a P g at the end of the sixth bit interval.
- the prefix 000010 from collection C Qt - is connected to Line 0 via a dotted line, even though messages with this prefix do not write a logic 1 on Line 0. This only serves to indicate that, had Line 0 yielded an 'N', it would have determined a collection that included 000010 instead of 000011 on Line 0. However, Line 0 yielded a 'Y', so message '34', with prefix 00010, NOT TAKEN INTO CONSIDERATION
- the pool collection is ignored as soon as L collections are identified.
- the system is defined by a status vector ⁇ a Q ,a. , ... ,a ⁇ _ 1 ;b j _>, i being the number of collections 0 ⁇ i ⁇ .
- P 0 ,p 1 , ... r P n _ 1 in increasing order, be those that show logic 1. Further, let p, be the line just written on by the station.
- Bit position log ⁇ L 3 (start of decision process) (FIG. 4)
- Prefix 10.
- m 2 (binary value of the prefix 10) .
- New bit b l.
- the closing phase requires an additional log 2 L-l bit positions to resolve completely the L messages.
- the general strategy of the closing phase is first presented and then the strategy is applied to the exemplary message frames discussed in the opening phase.
- a sequence ⁇ c ⁇ is defined wherein each element of the sequence is given by a rn./' ⁇ n-
- WRITE' (The prime notation is used to differentiate a WRITE in the closing phase from a WRITE in the opening phase.) If j ⁇ i and e «>0, then the integer division of member number of collection j by c. is performed to obtain the quotient q and the remainder r. If r ⁇ c.-l or i ⁇ L, then a logic 1 is written on line e Q +...+e. _+r. Otherwise, no signal propagation occurs.
- the bound on the size of collection j shrinks from a. to 1 in the following sequence: log 2 L-2 log 2 L-3 a., min a. ,d. , min a. ,d. , ...,
- Lines 3,4,5,6,7 are monitored to determine which have a logic 1. From FIG. 12, Lines 4 and 6 have a logic 1.
- This example is typical in that more than one message is conveyed by some of the lines (for instance, Lines 0, 1 and 4 each convey two of the eight messages) whereas other lines do not convey any of the messages (Lines 5 , 6 and 7 do not provide any successfully transmitted messages) ; the other two messages are transmitted by Lines 2 and 3.
- the dynamic allocation process in which all lines are utilized collectively during each bit interval leads to this result.
- a transmitting station keeps track of just three numbers for its intended message, namely: the number of collections; the collection identifier; and the membership identifier.
- each station actually has the capability to determine the collection and membership identifiers for any intended message. It is this algorithmic capability that enables every station to decode all the successfully transmitted messages.
- the manner in which each station manages data for decoding is as follows.
- the decoding function maps each eligible pair of the two identifiers to the bit pattern of the message, that is, to its corresponding prefix as the message unfolds. Eventually, there are up to L collections each containing only one message; each message is the one successfully transmitted.
- a data structure for the decoding function generally is composed of two tables having an identical format.
- the two tables serve alternately to store contending prefixes.
- each prefix stored in the active table is used to construct 0, 1 or 2 prefixes for the next bit interval.
- the new prefixes are then stored into the standby table and then the two tables interchange their roles as active and standby tables.
- a table comprises a 0 +...+a_ , entries, with every entry containing one activity bit and F data bits. Each entry stores one particular member of one particular collection/pool. Collection 0 occupies the first a Q entries in the table, collection 1 occupies the next a. entries, and so forth. In general, collection j starts at entry a Q +...+a.
- the initial pool contains L/2 predetermined members and requires no memory. Thereafter when there is a pool, it is treated as collection i (i ⁇ L) .
- This addressing scheme is fixed throughout the transmission session. An 'ON' activity bit of an entry indicates that the entry contains a contending prefix, while an 'OFF' bit indicates that the entry is currently serving only the purpose of padding. To exemplify this, the entry at the address a_+...+a.
- the degenerate case existing when there is a pool has not been shown but, illustratively, the pool could occupy the bottom portion of memory layout until all non-pool collections have been identified.
- FIG. 16 shows a snapshot of the memory contents of the active table for bit interval 11 of the illustrative example; FIG. 16 corresponds to the candidate, messages shown on the left-hand side of FIG. 12.
- FIG. 17 depicts the processing during any bit interval between log 2 L and F + log 2 L-l bit time positions; this arbitrary interval is designated by t in FIG. 17.
- the processing begins with decision process 201, which determines the bit position under consideration. If the interval is the first bit in the opening phase for which the lines are to be tested, the steps described by process block 203 are executed. These steps are basically the initialization steps to prepare the parameters i, j and m for the encoding algorithm. If the result of testing by block 201 indicates that bits other than the log 2 L bit are ready for processing, then decision step 205 is entered.
- Block 207 is also entered after initialization in block 203.
- the processing by block 207 causes the next bit in the message to be selected and this next bit serves as input information to the encoding algorithm.
- Processing block 209 depicts in general form the WRITE (WRITE') [in FIGS.
- both WRITE and WRITE' are designated by 'WRITE', and the appropriate one to use in a given situation is conveyed by the context; similar comments apply to READ and READ' as well as UPDATE and UPDATE', which follow] READ (READ') and UPDATE (UPDATE') algorithmic steps set forth in detail in the discussion of the function theoretic basis.
- decision block 213 is performed. This is the point of the process wherein unsuccessful candidate messages are dropped. If the candidate message is not dropped, then decision block 215 tests if both the opening and closing phases have been completed. If both phases are completed, then the transmission is successful. If the process is still in either the opening or closing phases, then the next bit interval is considered. This is depicted by processing block 217 wherein the next bit interval replaces the present interval and processing block 201 is again entered.
- FIG. 18 is first considered. Again, the process is described for any bit interval between log_L and F-+ log 2 L-l bit intervals; the particular bit interval is denoted by t.
- the two possible values for the next succeeding bit are serially processed by the subroutine shown in flow diagram in FIG. 19, which will be discussed shortly.
- the processing represented by block 315 is invoked. Briefly, this processing clears the activity bit of each active table entry (as discussed with reference to FIG. 15) and then interchanges the roles of the active and standby tables.
- decision block 317 is entered to determine the exact bit interval under consideration. If all bit intervals have been processed, block 319 is invoked to extract the transmitted messages from the then active table. If there are remaining bit intervals to be processed, the bit interval is incremented via block 319 and block 301 is again entered.
- Block 305 indicates that a READ (READ') operation is performed on the lines.
- READ READ
- Each station executes the same encoding algorithm, so each decoder embedded in the station may be coupled to its corresponding encoder and may monitor the results of the encoding process. Thus, each decoder has access to the value of i as it is determined.
- the station may UPDATE (UPDATE') the number of collections parameter i.
- decision block 307 is entered to determine if the opening phase or the closing phase is being processed.
- processing block 311 is entered.
- the main processing performed by the steps represented by block 311 is to prepare the appropriate information for subsequent calls to the subroutine depicted in FIG. 19.
- the processing is essentially the same as that performed by processing block 309.
- the branches available for traversal upon exiting the block are the same options existing upon exiting block 309.
- the final processing block in FIG. 18, namely, block 313, is invoked for the bit intervals corresponding to the closing phase.
- the value of i is known prior to entry into block 313, and a DO loop ranging over the active table entries is again executed.
- the values for j and m are obtained from the knowledge of i and the memory address information.
- Block 313 feeds block 315 and the processing then continues as described above.
- the entry point is processing block 351.
- the WRITE (WRITE') action required in either the opening or closing phases, as appropriate is identified.
- decision block 353 is invoked to determine if a logic 1 is to be propagated on any line. If 'YES', then follow-up decision processing in invoked for that line.
- a determination is made whether a logic 1 is READ (READ') from that line. If not, there is a Return from the subroutine. If so, then processing block 357 is entered; this block is also entered upon a 'NO' response to the processing by the steps of block 353.
- the encoding algorithm is used to identify the UPDATE (UPDATE') action required. Once identified, decision block 359 is entered to determine whether or not the UPDATE (UPDATE') action is to drop the candidated message. If so, there is a Return from the subroutine. If not, then the prefix is entered into the standby table as depicted by the processing of block 361. Upon completion of this processing, there is a normal Return form the processing subroutine.
- the status vector in the last bit interval may possibly become ⁇ 1,1,1,6> following the regular rules. It is undesirable to have the ⁇ 1,1,1;6> vector at the end of the opening phase because the closing phase may not be capable of determining the proper messages. Therefore, special rules are designed to change the above situation into
- n 0-19, 20-24, 25-27, 28-29, 30, 31
- n 0-37, 38-55, 56-58, 59-60, 61, 62, 63
Abstract
Description
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US184,331 | 1988-04-21 | ||
US07/184,331 US4852091A (en) | 1988-04-21 | 1988-04-21 | High capacity communication system utilizing OR-type channels |
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WO1989010667A1 true WO1989010667A1 (en) | 1989-11-02 |
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PCT/US1989/001668 WO1989010667A1 (en) | 1988-04-21 | 1989-04-19 | High capacity communication system utilizing or-type channels |
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US (1) | US4852091A (en) |
EP (1) | EP0412991A1 (en) |
JP (1) | JPH03505954A (en) |
WO (1) | WO1989010667A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0695677B2 (en) * | 1988-11-16 | 1994-11-24 | 株式会社日立製作所 | Network transmission system with multiple channels |
US5311512A (en) * | 1992-12-14 | 1994-05-10 | At&T Bell Laboratories | Multiple-master digital communication technique utilizing a dedicated contention bus |
US7106728B1 (en) | 2000-05-01 | 2006-09-12 | Industrial Technology Research Institute | Switching by multistage interconnection of concentrators |
US6591285B1 (en) | 2000-06-16 | 2003-07-08 | Shuo-Yen Robert Li | Running-sum adder networks determined by recursive construction of multi-stage networks |
US7609695B2 (en) * | 2001-06-15 | 2009-10-27 | Industrial Technology Research Institute | Optimizing switching element for minimal latency |
US7103059B2 (en) * | 2001-06-15 | 2006-09-05 | Industrial Technology Research Institute | Scalable 2-stage interconnections |
US6934876B1 (en) | 2002-06-14 | 2005-08-23 | James L. Holeman, Sr. | Registration system and method in a communication network |
US7400615B2 (en) * | 2003-10-15 | 2008-07-15 | Holeman Sr James L | System and method for deterministic registration for communication networks |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4871547A (en) * | 1971-12-27 | 1973-09-27 | Hitachi Ltd | |
GB1365838A (en) * | 1972-04-21 | 1974-09-04 | Ibm | Data handling system |
US4281380A (en) * | 1978-12-27 | 1981-07-28 | Harris Corporation | Bus collision avoidance system for distributed network data processing communications system |
US4359731A (en) * | 1980-08-22 | 1982-11-16 | Phillips Petroleum Company | Communication link contention resolution system |
IT1129371B (en) * | 1980-11-06 | 1986-06-04 | Cselt Centro Studi Lab Telecom | MESSAGE SWITCH WITH STRUCTURE DISTRIBUTED ON A CHANNEL WITH RANDOM ACCESS FOR INTERVIEW WITH MESSAGES BETWEEN PROCESSING UNITS |
US4376278A (en) * | 1980-12-22 | 1983-03-08 | Honeywell Information Systems Inc. | Apparatus and method for collision avoidance |
US4383314A (en) * | 1981-01-12 | 1983-05-10 | Burroughs Corporation | Circular access linkage loop configuration for system communication |
US4481626A (en) * | 1982-05-05 | 1984-11-06 | Xerox Corporation | Transceiver multiplexor |
US4476467A (en) * | 1982-06-08 | 1984-10-09 | Cromemco Inc. | Random entry intercomputer network with collision prevention |
US4536877A (en) * | 1983-01-21 | 1985-08-20 | E-Systems, Inc. | Tack-on acknowledgment in computer networks |
US4584679A (en) * | 1983-01-21 | 1986-04-22 | E-Systems, Inc. | Tack-on acknowledgement in computer networks |
US4586175A (en) * | 1984-04-30 | 1986-04-29 | Northern Telecom Limited | Method for operating a packet bus for transmission of asynchronous and pseudo-synchronous signals |
US4768189A (en) * | 1987-06-17 | 1988-08-30 | Bell Communications Research, Inc. | High capacity communication utilizing static, OR-type channels |
-
1988
- 1988-04-21 US US07/184,331 patent/US4852091A/en not_active Expired - Lifetime
-
1989
- 1989-04-19 EP EP89905503A patent/EP0412991A1/en not_active Ceased
- 1989-04-19 WO PCT/US1989/001668 patent/WO1989010667A1/en not_active Application Discontinuation
- 1989-04-19 JP JP1505252A patent/JPH03505954A/en active Pending
Non-Patent Citations (2)
Title |
---|
IEEE/IEICE Global Telecommunications Conference 1987, 15-18 November 1987, Tokyo, Japan, Conference Record, Volume 3 of 3, IEEE, (New York, US), H. OKADA et al.: "Priority Schemes of Multi-Channel CSMA/CD for Advanced Multi-Media Networks", pages 1607-1611 * |
Proceedings IEEE INFOCOM '86, Fifth Annual Conference "Computers and Communications Integration Design, Analysis, Management", 8-10 April 1986, Miami, Florida, IEEE, (New York, US), J.-Y. JUANG et al.: "Channel Allocation in Multiple Contention Bus Networks", pages 189-195 * |
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Publication number | Publication date |
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EP0412991A1 (en) | 1991-02-20 |
JPH03505954A (en) | 1991-12-19 |
US4852091A (en) | 1989-07-25 |
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