WO1993005536A1 - Eeprom cell with improved tunneling properties - Google Patents
Eeprom cell with improved tunneling properties Download PDFInfo
- Publication number
- WO1993005536A1 WO1993005536A1 PCT/US1992/007728 US9207728W WO9305536A1 WO 1993005536 A1 WO1993005536 A1 WO 1993005536A1 US 9207728 W US9207728 W US 9207728W WO 9305536 A1 WO9305536 A1 WO 9305536A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- oxide layer
- implant region
- implant
- layer
- tunnel
- Prior art date
Links
- 230000005641 tunneling Effects 0.000 title claims abstract description 43
- 239000007943 implant Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000007667 floating Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 230000015654 memory Effects 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000000126 substance Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- 230000001010 compromised effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000008672 reprogramming Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Definitions
- the present invention relates generally to non-volatile memories, and in particular to electrically erasable programmable read only memories (i.e., EEPROMs or E 2 PROMs) .
- EEPROMs electrically erasable programmable read only memories
- E 2 PROMs electrically erasable programmable read only memories
- ROMs Read only memories
- ROMs are non-volatile memory devices whose contents are typically programmed during fabrication. Once programmed, a standard ROM cannot be erased and reprogrammed. ROMs find utility in storing information such as operating code, reference data and so forth. Non-volatile ROMs have the advantage that stored information is not erased when power is removed from the device.
- EPROMs electrically programmable ROMs
- EPROMs are memory devices in which data can be written electronically using a technique known as hot electron injection.
- a floating gate With hot electron injection, a floating gate is charged by energizing carrier electrons to high energy levels. The high energy electrons are then able to pass through an insulator and into the floating gate.
- EPROMs typically use ultraviolet
- EPRO s do not require a UV light source for erasure and do not necessarily require the memory device to be removed from the circuit board for reprogramming.
- E 2 PR0M cells are fabricated using metal oxide semiconductor field effect transistors (MOSFETs) as described in U.S. Patent No. 4,477,883.
- MOSFETs metal oxide semiconductor field effect transistors
- an E 2 PROM memory cell is formed with a double layer of polysilicon and three electrodes electrically isolated from each other. E 2 PROMs use this configuration to exploit the known phenomenon of electron tunneling during programming and erasure.
- a first electrode 2 is formed from a first polysilicon layer as a floating gate completely encapsulated in an oxide insulating layer.
- the thickness in an area of the oxide under the gate is reduced to form a tunnel window region formed as a thin tunnel oxide layer.
- This tunnel window region is either defined in the thin gate oxide layer 10 (e.g., 300-400 k) or a special thicker, decoupling oxide layer (e.g., 3000 A) of a field shown as field oxide layer 5 in Figure 1 (e.g., 8500 k) .
- the tunnel oxide effectively isolates the floating gate to prevent charge migration to or from the floating gate.
- relatively high voltages e.g. 20V
- electrons tunnel through the thin oxide insulating layer in the aforementioned tunnel window region.
- a high voltage state can be used to program or erase the floating gate.
- a second electrode 4 is formed from an n- implant in a substrate 1 as a tunneling gate. Electrons tunnel between the electrodes 2 and 4 via the thin tunnel oxide layer 6 (e.g., 100 ) formed within a tunnel window region of the decoupling oxide layer 7 interposed between the electrodes 2 and 4.
- a third electrode 8 is formed from a second polysilicon layer as a coupling gate.
- the tunneling gate 4 is capacitively coupled to the floating gate 2 as is the coupling gate 8.
- the combination of the coupling gate 8, the floating gate 2 and the tunneling gate 4 can thus be represented schematically by two capacitors connected in series.
- the tunneling gate 4 and the coupling gate 8 control the charge and discharge (programming and erasure) of majority carriers (i.e., electrons) in the floating gate 2.
- a select transistor 12 is formed on substrate 1.
- the select transistor is formed with a portion of the tunneling gate 4, an n- implant representing a gate select contact 14, a portion of the thin gate oxide layer 10 and portion 16 of the first polysilicon layer.
- a low voltage e.g., ground
- the select transistors e.g., via gate select contact 14
- the coupling gate 8 is placed at a high potential (e.g., 20 volts). Accordingly, electrons pass from the gate select contact 14 across the substrate 1 to the tunneling gate 4. From the tunneling gate 4, these electrons pass through the thin tunnel oxide layer 6 and into the floating gate 2 where a negative charge is stored.
- the tunneling current lows through the thin tunnel oxide layer 6 in a region where the tunneling gate 4 and the floating gate 2 overlap. Electrons are thereby injected into the floating gate 2 to write the logic low, or "0". In this state, there is no current flow through this cell during a read operation.
- the coupling gate 8 associated with the floating gate 2 is grounded while the gate select contact 14 and the tunneling gate 4 are raised to a high potential (e.g., 20 volts).
- a high potential e.g. 20 volts.
- the floating gate 2 returns to a logic level high, or "1" by emitting tunneling electrons to the voltage source via the thin oxide layer 6.
- the floating gate is thereby left positively charged, and the cell conducts a current during a read operation.
- polysilicon-to-polysilicon tunneling can be used to remove floating gate electrons from the floating gate during an erasure mode.
- Figures 2a-2d show a method for fabricating a memory cell of an E 2 PROM such as that shown in Figure 1.
- Figure 2a shows formation of the Figure 1 E 2 PROM cell from a point following coating of a photoresist layer 17 on the field oxide layer 5 and substrate 1.
- a window in the photoresist layer 17, generally represented as window 18, encompasses a portion of the field oxide layer 5 and the thin gate oxide layer 10 so that an arsenic (As) implant can be used to form the tunneling gate 4 of Figure 1.
- a thicker decoupling oxide 7 is then grown over the arsenic implanted area.
- Figure 2b shows the arsenic implanted as the tunneling gate 4.
- the field oxide layer 5 is approximately 8500 Angstroms (A)
- the decoupling oxide layer 7 is shown to be approximately 3000 A.
- a tunneling window 20 is formed in the decoupling oxide layer 7 following coating of a photoresist layer 22 and an etching process.
- the etching process is used to remove a portion of the decoupling oxide layer 7 located within the tunnel window 20. This portion of the decoupling oxide layer is removed down to the substrate 1.
- the Figure 2c etching process has significant disadvantages.
- etching there are two types of etching: dry etching using plasma to etch a surface, and wet etching where a liquid chemical is used to dissolve material on a wafer surface.
- dry etching to perform the etching process of Figure 2c can significantly damage the silicon surface during removal of the decoupling oxide down to the substrate 1. This degrades the quality of the tunnel oxide layer grown in the tunnel area.
- a wet etch process is difficult to control through the thick decoupling oxide layer 7.
- the etching chemical may not wet the entire area within the tunnel window 20 such that an incomplete etching process may occur and significantly degrade the quality of the tunnel window oxide layer. Additionally, the wet chemical may not wet all the tunnel windows on an IC chip (which can number many thousand) leaving some windows unetched or partially etched and resulting in bad memory cells and low net yield.
- the chemical used for the wet etch may over-etch the area within the tunnel window 20, similarly degrading performance of the tunnel window oxide layer by increasing its size and the potential for current leakage during operation.
- This increase in tunnel window size also affects the electrical capacitance of the tunnel oxide which adversely affects the electrical performance.
- the wetting efficiency of a liquid is dependent on the size of the hole being wetted; it becomes more difficult as the hole size is reduced. This makes wet etching of the tunnel window less dependable as transistor sizes decrease and IC density increases.
- the present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular an E 2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate of the E 2 PROM cell.
- An E 2 PROM cell designed in accordance with the invention includes a tunneling gate fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages is independently optimized to improve the properties of the tunnel area. These properties enhance operating efficiency of the memory device, and extend the operating life of the memory device. Further, the windows used to define the implant regions are easily fabricated and provide for easy control of etching. More particularly, the two separate implant regions permit two separate doses of different materials to be implanted in the tunnel gate.
- the dose can be increased to reduce resistance.
- a second region of the tunnel gate under the thin tunnel oxide layer can be formed with a decreased dose to reduce leakage of the tunnel oxide during normal operation of the memory cell.
- the same mask used to fabricate an active area of peripheral transistors can be used to define a first implant region.
- a relatively large window can be used to establish a second implant region. This relatively large window can be defined with a wide tolerance without concern that over-etching will damage the substrate.
- a method for fabricating a cell for use in a semiconductor memory device includes the steps of forming a first oxide layer of varying thickness on a semiconductor substrate, the oxide layer having a first portion formed of a first thickness and a second portion formed of a second thickness greater than said first thickness.
- a silicon nitride layer on the first oxide prevents further growth of the first oxide.
- a first implant region of the substrate is defined beneath the first portion of the oxide layer by coating a photoresist material as a mask on the silicon nitride layer and exposing the tunnel gate area around (but not under) the tunnel window area.
- the silicon nitride is etched on this tunnel gate area, and a first dose of a conductive material is implanted within the first implant region.
- the photoresist mask is then removed.
- a third oxide layer is grown on the first oxide layer with the nitride layer in place over the tunnel area of the first oxide layer.
- This oxide is surrounded by a significantly thicker decoupling oxide which therefore defines the edge of the tunnel window.
- a second implant region of the substrate is defined beneath the tunnel area of the oxide layer by removing the silicon nitride layer and coating a second photoresist mask on the third oxide layer.
- a second dose of a conductive material is implanted within the second implant region.
- the first layer of oxide is removed from the tunnel area as is the second photoresist mask.
- a tunnel window oxide layer is grown on the substrate. At least a first polysilicon layer is then deposited over the tunnel window oxide layer to form a conductive region of the semiconductor memory cell.
- Figure 1 shows an E 2 PROM memory cell and gate select transistor
- Figures 2a-2d show a conventional fabrication method for forming a conventional E 2 PROM memory cell as shown in the right-hand side of Figure 1;
- Figures 3a-3d show an exemplary embodiment of a fabrication method for forming an E 2 PROM memory cell as shown in the right-hand side of Figure 1 in accordance with the present invention
- Figures 2 and 3 are cross-sectional views through the tunnel window of Figure 1 along section line A'-A'.
- Figures 3a-3d show an exemplary fabrication technique for forming an E 2 PROM memory device cell in accordance with the present invention.
- a memory cell is formed on a substrate 30.
- a variable thickness field oxide layer 32 is grown on the substrate 30.
- the variable thickness field oxide layer includes a first portion 34 having a first thickness and a second portion 36 having a second thickness.
- the first portion 34 has a thickness of approximately 8500 A
- the second portion has a thickness considerably less than 8500 A (e.g. , several hundred A) .
- a first implant region is defined on the substrate beneath the relatively thin second portion of the field oxide layer.
- the step of defining a first implant region includes a step of depositing a protective silicon nitride layer 38 on the variable thickness field oxide layer 32 where a tunnel window oxide layer is subsequently to be formed.
- the silicon nitride layer 38 is thus formed over a portion of the variable thickness field oxide layer 32 which will be used to form a tunnel area of the memory device cell shown.
- a photoresist material 40 is coated on the silicon nitride layer, and the silicon nitride layer is etched to define edges 42.
- the photoresist material 40 and -li ⁇ the etched silicon nitride layer 38 thus define boundaries of a first window having first and second openings 37 and 39 located on opposite sides of the silicon nitride layer 38 over the variable thickness field oxide layer 32.
- a first dose of a conductive material is implanted within a first implant region of the substrate 30 located beneath the first and second openings 37 and 39.
- the conductive material used for this first implant is arsenic.
- the arsenic is implanted into a first region represented by the dotted lines 44 and 46 in Figure 3b.
- a second field oxide layer is grown on the first oxide layer as shown in Figure 3b.
- This second oxide layer is grown along the entire length of the variable thickness field oxide layer 32 with the exception of the area beneath the silicon nitride layer 38 (note that some oxide will grow near edges of the silicon nitride layer thus deforming the silicon nitride layer) .
- the second oxide layer is grown over the variable thickness field oxide layer until the variable thickness field oxide layer adjacent the silicon nitride layer is approximately 3000 A thick.
- a second implant region of the substrate 30 is then defined.
- the silicon nitride layer which has been deformed in Figure 3b due to growth of the second oxide layer is chemically etched from the surface of the variable thickness field oxide layer 32. This chemical etching of the silicon nitride layer is preferably performed using hot phosphoric acid.
- a second photoresist mask 48 is then coated on the variable thickness field oxide layer 32 to establish a window 50 which defines a second implant region. Because the variable thickness field oxide layer 32 has been grown to a thickness (e.g., 3000 A) considerably greater than the thickness of the first oxide layer remaining beneath the etched silicon nitride layer, the width of the window 50 defined by the second photoresist mask 48 need not be precise. Rather, the width of the tunnel window region is defined by the silicon nitride dimension (i.e., layer 38) .
- a second dose of a conductive material is implanted within the second implant region of the substrate located within the tunnel area 52 of Figure 3c.
- the conductive material used for the second dose is phosphorous.
- a second implant region 54 as shown in Figure 3d is thus established between the first implant regions 44 and 46. After thermal diffusion during subsequent processing, the second implant region 54 overlaps slightly with the first implant regions 44 and 46 to define a continuous tunneling gate as shown in Figure 3d.
- the first layer of oxide which had been previously protected by the silicon nitride layer 38 is etched from the substrate 30.
- the etching of the first oxide layer previously located beneath the silicon nitride layer 38 is etched using a chemical process. Etching of the first oxide layer is performed until the substrate in the tunnel area 52 is exposed as shown in Figure 3c.
- the etching of the first oxide layer from the region of the substrate previously protected by the silicon nitride layer need not be precise. Rather, over-etching of the tunnel area will merely reduce the thickness of the variable thickness field oxide layer 32 located within the window 50 and will not increase the size of the tunnel window. Since only a thin oxide is etched (i.e., a few hundred A instead of 3000 A) , even a plasma etch can be used and will cause less damage to the substrate, thereby reducing the propensity for leakage in the tunnel oxide. It is for this reason that the second photoresist mask 48 need not be defined with great accuracy, thus simplifying the fabrication process.
- a tunnel window oxide layer 56 having an accurate thickness can be grown over the tunnel area 52.
- the tunnel window oxide layer 56 is grown to approximately 100 A.
- a first polysilicon layer 58 is deposited over the variable thickness field oxide layer 32 and the tunnel window oxide layer 56 as shown in Figure 3d.
- the remaining stages of an E 2 PROM memory device cell as shown in Figure 1 are then performed in conventional fashion to form, for example, the floating gate 2 and the coupling gate 8.
- a tunneling gate represented generally by the first and second implant regions 44, 46 and 54 in Figure 3d can be formed from two different materials using two different doses. Accordingly, the first implant region 44, 46 can be formed with a relatively high dose to decrease the resistance in an area closest to a select transistor. However, the dose of the material used to form the second implant region 54 can be relatively low so that current leakage from the floating gate through the tunnel window oxide 56 is mitigated. Thus, an E 2 PROM memory device cell can be ormed with improved properties which provide high quality programming and erasure control over a relatively large number of programming cycles.
- the photoresist mask described above with respect to the " conventional fabrication technique in Figure 2c requires a relatively accurately placed window having very accurate dimensions.
- the photoresist mask used to define the window 50 can be formed with dimensions having a great deal of tolerance. The actual tolerance associated with these dimensions is limited only by the length of the variable field oxide layer on either side of the tunnel area 52.
- the photoresist layer used to establish a mask for forming the implant region of the tunneling gate need not be accurately aligned with the field oxide layer, a relatively large window can be used to improve etching control during formation of the tunnel area.
- the relatively wide window 50 facilitates wetting of the oxide layer previously protected by the silicon nitride layer 38 without concern that over-etching will remove the oxide from areas over the substrate adjacent the tunnel area.
- a resulting memory cell designed in accordance with the present invention has improved tunneling characteristics which could not previously be realized. These characteristics included improved programming and erasing operations, and extended life of the memory cell.
- a semiconductor memory device cell designed in accordance with the invention is formed which is similar to that described above with respect to Figure 1.
- the tunnel window is easily defined by wet etching an oxide of a few hundred A thickness instead of an uncontrollable wet etch or a substrate damaging plasma etch of a thicker, decoupling oxide.
- a tunneling oxide grown therefore has a well defined size and less leakage and hence provides a longer life for the memory cell.
- the tunneling gate 4 is no longer formed with a single n- material, but rather is formed with two different doses of the same or different implant materials as described above with respect to Figure 3d.
- a tunneling gate formed with first and second implant regions provides improved operating characteristics and extends the life of the memory device cell.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular an E2PROM having an improved tunnel area (52) wherein electrons travel to and from a floating gate (2). The tunnel area is characterised by properties which lend to a relatively large number of programming and erasure cycles over the life of the E2PROM. The tunnel area includes a tunneling gate (4) which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimised to improve the properties of the tunnel area. Further, the windows (37, 39, 50) used to define the implant regions (44, 46, 54) are easily fabricated and are designed to facilitate formation of the implant regions.
Description
EEPROM CELL WITH IMPROVED TUNNELING PROPERTIES
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates generally to non-volatile memories, and in particular to electrically erasable programmable read only memories (i.e., EEPROMs or E2PROMs) .
State of the Art
Read only memories (ROMs) are non-volatile memory devices whose contents are typically programmed during fabrication. Once programmed, a standard ROM cannot be erased and reprogrammed. ROMs find utility in storing information such as operating code, reference data and so forth. Non-volatile ROMs have the advantage that stored information is not erased when power is removed from the device.
More recently, electrically programmable ROMs (EPROMs) have been developed. EPROMs are memory devices in which data can be written electronically using a technique known as hot electron injection.
With hot electron injection, a floating gate is charged by energizing carrier electrons to high energy levels. The high energy electrons are then able to pass through an insulator and into the floating gate.
However, EPROMs typically use ultraviolet
(UV) light to erase stored data. Accordingly, erasing an EPROM's contents requires removal of the EPROM from a circuit board. Such a procedure is inconvenient and time consuming.
Electrically erasable PROMs (EEPROM or E2PROM) are another variety of known memory devices. A document entitled "Comparison and Trends in Today's Dominant E2 Technologies" by S.K. Lai, V.K. Dham and D. Guterman generally describes two approaches for charging a floating gate of an E2PROM via a thin tunnel oxide.
EPRO s do not require a UV light source for erasure and do not necessarily require the memory device to be removed from the circuit board for reprogramming. Typically, E2PR0M cells are fabricated using metal oxide semiconductor field effect transistors (MOSFETs) as described in U.S. Patent No. 4,477,883. As shown in Figure 1 of the present application, an E2PROM memory cell is formed with a double layer of polysilicon and three electrodes electrically isolated from each other. E2PROMs use this configuration to exploit the known phenomenon of electron tunneling during programming and erasure.
Referring to Figure 1, a first electrode 2 is formed from a first polysilicon layer as a floating gate completely encapsulated in an oxide insulating layer. Typically, the thickness in an area of the oxide under the gate is reduced to form a tunnel window region formed as a thin tunnel oxide layer. This tunnel window region is either defined in the thin gate oxide layer 10 (e.g., 300-400 k) or a special thicker, decoupling oxide layer (e.g., 3000 A) of a field shown as field oxide layer 5 in Figure 1 (e.g., 8500 k) .
During normal operating voltages (e.g., 5V) , the tunnel oxide effectively isolates the floating gate to prevent charge migration to or from the floating gate. However, when subjected to relatively high
voltages (e.g., 20V), electrons tunnel through the thin oxide insulating layer in the aforementioned tunnel window region. Thus, a high voltage state can be used to program or erase the floating gate. When the floating polysilicon is charged positive, the memory cell will be turned on and conduct a current during a read operation. When the floating polysilicon is charged negative, the memory cell is turned off and will not conduct current during a read operation.
As shown in Figure 1, a second electrode 4 is formed from an n- implant in a substrate 1 as a tunneling gate. Electrons tunnel between the electrodes 2 and 4 via the thin tunnel oxide layer 6 (e.g., 100 ) formed within a tunnel window region of the decoupling oxide layer 7 interposed between the electrodes 2 and 4. A third electrode 8 is formed from a second polysilicon layer as a coupling gate.
The tunneling gate 4 is capacitively coupled to the floating gate 2 as is the coupling gate 8. The combination of the coupling gate 8, the floating gate 2 and the tunneling gate 4 can thus be represented schematically by two capacitors connected in series. The tunneling gate 4 and the coupling gate 8 control the charge and discharge (programming and erasure) of majority carriers (i.e., electrons) in the floating gate 2.
As shown in Figure 1, a select transistor 12 is formed on substrate 1. The select transistor is formed with a portion of the tunneling gate 4, an n- implant representing a gate select contact 14, a portion of the thin gate oxide layer 10 and portion 16 of the first polysilicon layer.
When data is written into the Figure 1 memory cell, a low voltage (e.g., ground) is supplied via the select transistors (e.g., via gate select contact 14) to the tunneling gate 4. In addition, the coupling gate 8 is placed at a high potential (e.g., 20 volts). Accordingly, electrons pass from the gate select contact 14 across the substrate 1 to the tunneling gate 4. From the tunneling gate 4, these electrons pass through the thin tunnel oxide layer 6 and into the floating gate 2 where a negative charge is stored. The tunneling current lows through the thin tunnel oxide layer 6 in a region where the tunneling gate 4 and the floating gate 2 overlap. Electrons are thereby injected into the floating gate 2 to write the logic low, or "0". In this state, there is no current flow through this cell during a read operation.
To write a logic level 1, the coupling gate 8 associated with the floating gate 2 is grounded while the gate select contact 14 and the tunneling gate 4 are raised to a high potential (e.g., 20 volts). As a result, the floating gate 2 returns to a logic level high, or "1" by emitting tunneling electrons to the voltage source via the thin oxide layer 6. The floating gate is thereby left positively charged, and the cell conducts a current during a read operation. In alternate embodiments, polysilicon-to-polysilicon tunneling can be used to remove floating gate electrons from the floating gate during an erasure mode.
Figures 2a-2d show a method for fabricating a memory cell of an E2PROM such as that shown in Figure 1. Figure 2a shows formation of the Figure 1 E2PROM cell from a point following coating of a photoresist layer 17 on the field oxide layer 5 and substrate 1. A window in the photoresist layer 17, generally
represented as window 18, encompasses a portion of the field oxide layer 5 and the thin gate oxide layer 10 so that an arsenic (As) implant can be used to form the tunneling gate 4 of Figure 1. A thicker decoupling oxide 7 is then grown over the arsenic implanted area.
Figure 2b shows the arsenic implanted as the tunneling gate 4. As shown in Figure 2b, the field oxide layer 5 is approximately 8500 Angstroms (A) , and the decoupling oxide layer 7 is shown to be approximately 3000 A.
In Figure 2c, a tunneling window 20 is formed in the decoupling oxide layer 7 following coating of a photoresist layer 22 and an etching process. The etching process is used to remove a portion of the decoupling oxide layer 7 located within the tunnel window 20. This portion of the decoupling oxide layer is removed down to the substrate 1.
In Figure 2d, the photoresist layer 22 has been stripped, and a tunnel window oxide layer 6, approximately 100 A thick, is grown. Afterwards, the first polysilicon layer 2 is deposited, and formation of the remaining portion of the Figure 1 E2PROM continued in known fashion.
The foregoing fabrication process of the Figure 1 E2PROM has several, significant drawbacks. For example, the Figure 2c etching process has significant disadvantages. Generally speaking, there are two types of etching: dry etching using plasma to etch a surface, and wet etching where a liquid chemical is used to dissolve material on a wafer surface.
The use of a dry etch to perform the etching process of Figure 2c can significantly damage the silicon surface during removal of the decoupling oxide down to the substrate 1. This degrades the quality of the tunnel oxide layer grown in the tunnel area. On the other hand, a wet etch process is difficult to control through the thick decoupling oxide layer 7. For example, the etching chemical may not wet the entire area within the tunnel window 20 such that an incomplete etching process may occur and significantly degrade the quality of the tunnel window oxide layer. Additionally, the wet chemical may not wet all the tunnel windows on an IC chip (which can number many thousand) leaving some windows unetched or partially etched and resulting in bad memory cells and low net yield.
Alternately, the chemical used for the wet etch may over-etch the area within the tunnel window 20, similarly degrading performance of the tunnel window oxide layer by increasing its size and the potential for current leakage during operation. This increase in tunnel window size also affects the electrical capacitance of the tunnel oxide which adversely affects the electrical performance. Finally, the wetting efficiency of a liquid is dependent on the size of the hole being wetted; it becomes more difficult as the hole size is reduced. This makes wet etching of the tunnel window less dependable as transistor sizes decrease and IC density increases.
Because the Figure 2a-2d process uses a single n- implant for the tunneling gate 4, design flexibility of the tunneling gate is also limited. Certain performance characteristics must be compromised to optimize other properties of the tunneling gate.
For example, it is known that if the substrate 1 is very heavily doped or implanted, the quality of the oxide grown (i.e., tunnel oxide 6) is compromised, resulting in higher leakage through the tunnel oxide layer 6. Because a single implant is used to create the tunneling gate 4, the dose of the entire region must be sufficiently low to prevent leakage current across the tunnel oxide layer 6 during normal operation. However, this low dosage results in a high resistance tunneling gate which hinders electron movement in and out of the tunneling gate via the gate select contact 14, thus decreasing operating efficiency during programming and erasure.
Accordingly, it would be desirable to provide a semiconductor memory device and method for fabricating a semiconductor memory device which overcomes the aforementioned deficiencies.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular an E2PROM, having an improved tunnel area wherein electrons travel to and from a floating gate of the E2PROM cell. An E2PROM cell designed in accordance with the invention includes a tunneling gate fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages is independently optimized to improve the properties of the tunnel area. These properties enhance operating efficiency of the memory device, and extend the operating life of the memory device. Further, the windows used to define the implant regions are easily fabricated and provide for easy control of etching.
More particularly, the two separate implant regions permit two separate doses of different materials to be implanted in the tunnel gate. For example, in a first outer implant region of the tunnel gate, the dose can be increased to reduce resistance. On the other hand, a second region of the tunnel gate under the thin tunnel oxide layer can be formed with a decreased dose to reduce leakage of the tunnel oxide during normal operation of the memory cell.
In establishing windows to define the implant regions, the same mask used to fabricate an active area of peripheral transistors (e.g., select transistors) can be used to define a first implant region. Further, a relatively large window can be used to establish a second implant region. This relatively large window can be defined with a wide tolerance without concern that over-etching will damage the substrate.
In accordance with a preferred embodiment, a method for fabricating a cell for use in a semiconductor memory device such as an E2PROM includes the steps of forming a first oxide layer of varying thickness on a semiconductor substrate, the oxide layer having a first portion formed of a first thickness and a second portion formed of a second thickness greater than said first thickness. When the second thicker oxide is being grown, a silicon nitride layer on the first oxide prevents further growth of the first oxide. A first implant region of the substrate is defined beneath the first portion of the oxide layer by coating a photoresist material as a mask on the silicon nitride layer and exposing the tunnel gate area around (but not under) the tunnel window area. The silicon nitride is etched on this tunnel gate area, and a first dose of a conductive material is implanted within the first
implant region. The photoresist mask is then removed. A third oxide layer is grown on the first oxide layer with the nitride layer in place over the tunnel area of the first oxide layer. Thus, only a thin oxide in the area of the tunnel oxide needs to be etched away. This oxide is surrounded by a significantly thicker decoupling oxide which therefore defines the edge of the tunnel window.
A second implant region of the substrate is defined beneath the tunnel area of the oxide layer by removing the silicon nitride layer and coating a second photoresist mask on the third oxide layer. A second dose of a conductive material is implanted within the second implant region. The first layer of oxide is removed from the tunnel area as is the second photoresist mask. A tunnel window oxide layer is grown on the substrate. At least a first polysilicon layer is then deposited over the tunnel window oxide layer to form a conductive region of the semiconductor memory cell.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings wherein like elements have been designated by like numerals and wherein:
Figure 1 shows an E2PROM memory cell and gate select transistor;
Figures 2a-2d show a conventional fabrication method for forming a conventional E2PROM memory cell as shown in the right-hand side of Figure 1; and
Figures 3a-3d show an exemplary embodiment of a fabrication method for forming an E2PROM memory cell
as shown in the right-hand side of Figure 1 in accordance with the present invention; Figures 2 and 3 are cross-sectional views through the tunnel window of Figure 1 along section line A'-A'.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figures 3a-3d show an exemplary fabrication technique for forming an E2PROM memory device cell in accordance with the present invention. As shown in Figure 3a, a memory cell is formed on a substrate 30. Using known fabrication techniques similar to those used for conventional memory cells as described above, a variable thickness field oxide layer 32 is grown on the substrate 30. The variable thickness field oxide layer includes a first portion 34 having a first thickness and a second portion 36 having a second thickness. For example, the first portion 34 has a thickness of approximately 8500 A, and the second portion has a thickness considerably less than 8500 A (e.g. , several hundred A) .
In a preferred embodiment, a first implant region is defined on the substrate beneath the relatively thin second portion of the field oxide layer. The step of defining a first implant region includes a step of depositing a protective silicon nitride layer 38 on the variable thickness field oxide layer 32 where a tunnel window oxide layer is subsequently to be formed. The silicon nitride layer 38 is thus formed over a portion of the variable thickness field oxide layer 32 which will be used to form a tunnel area of the memory device cell shown. A photoresist material 40 is coated on the silicon nitride layer, and the silicon nitride layer is etched to define edges 42. The photoresist material 40 and
-li¬ the etched silicon nitride layer 38 thus define boundaries of a first window having first and second openings 37 and 39 located on opposite sides of the silicon nitride layer 38 over the variable thickness field oxide layer 32.
Upon defining the aforementioned windows over the variable thickness field oxide layer 32, a first dose of a conductive material is implanted within a first implant region of the substrate 30 located beneath the first and second openings 37 and 39. In an exemplary embodiment, the conductive material used for this first implant is arsenic. The arsenic is implanted into a first region represented by the dotted lines 44 and 46 in Figure 3b.
Subsequently, a second field oxide layer is grown on the first oxide layer as shown in Figure 3b. This second oxide layer is grown along the entire length of the variable thickness field oxide layer 32 with the exception of the area beneath the silicon nitride layer 38 (note that some oxide will grow near edges of the silicon nitride layer thus deforming the silicon nitride layer) . The second oxide layer is grown over the variable thickness field oxide layer until the variable thickness field oxide layer adjacent the silicon nitride layer is approximately 3000 A thick.
A second implant region of the substrate 30 is then defined. As shown in Figure 3c, the silicon nitride layer which has been deformed in Figure 3b due to growth of the second oxide layer is chemically etched from the surface of the variable thickness field oxide layer 32. This chemical etching of the silicon nitride layer is preferably performed using hot
phosphoric acid. A second photoresist mask 48 is then coated on the variable thickness field oxide layer 32 to establish a window 50 which defines a second implant region. Because the variable thickness field oxide layer 32 has been grown to a thickness (e.g., 3000 A) considerably greater than the thickness of the first oxide layer remaining beneath the etched silicon nitride layer, the width of the window 50 defined by the second photoresist mask 48 need not be precise. Rather, the width of the tunnel window region is defined by the silicon nitride dimension (i.e., layer 38) .
Once the window 50 has been defined, a second dose of a conductive material is implanted within the second implant region of the substrate located within the tunnel area 52 of Figure 3c. In an exemplary embodiment, the conductive material used for the second dose is phosphorous. Following the phosphorous implant, a second implant region 54 as shown in Figure 3d is thus established between the first implant regions 44 and 46. After thermal diffusion during subsequent processing, the second implant region 54 overlaps slightly with the first implant regions 44 and 46 to define a continuous tunneling gate as shown in Figure 3d.
Returning to Figure 3c, upon completion of the phosphorous implant, the first layer of oxide which had been previously protected by the silicon nitride layer 38 is etched from the substrate 30. In a preferred embodiment, the etching of the first oxide layer previously located beneath the silicon nitride layer 38 is etched using a chemical process. Etching of the first oxide layer is performed until the
substrate in the tunnel area 52 is exposed as shown in Figure 3c.
Because the first and second oxide layers form a variable thickness field oxide layer immediately adjacent the tunnel area 52 which is relatively thick (e.g., 3000 A), the etching of the first oxide layer from the region of the substrate previously protected by the silicon nitride layer need not be precise. Rather, over-etching of the tunnel area will merely reduce the thickness of the variable thickness field oxide layer 32 located within the window 50 and will not increase the size of the tunnel window. Since only a thin oxide is etched (i.e., a few hundred A instead of 3000 A) , even a plasma etch can be used and will cause less damage to the substrate, thereby reducing the propensity for leakage in the tunnel oxide. It is for this reason that the second photoresist mask 48 need not be defined with great accuracy, thus simplifying the fabrication process.
Once the substrate has been exposed in the tunnel area 52, a tunnel window oxide layer 56 having an accurate thickness can be grown over the tunnel area 52. In a preferred embodiment, the tunnel window oxide layer 56 is grown to approximately 100 A. Afterwards, a first polysilicon layer 58 is deposited over the variable thickness field oxide layer 32 and the tunnel window oxide layer 56 as shown in Figure 3d. The remaining stages of an E2PROM memory device cell as shown in Figure 1 are then performed in conventional fashion to form, for example, the floating gate 2 and the coupling gate 8.
By the aforementioned preferred fabrication process, a tunneling gate represented generally by the
first and second implant regions 44, 46 and 54 in Figure 3d can be formed from two different materials using two different doses. Accordingly, the first implant region 44, 46 can be formed with a relatively high dose to decrease the resistance in an area closest to a select transistor. However, the dose of the material used to form the second implant region 54 can be relatively low so that current leakage from the floating gate through the tunnel window oxide 56 is mitigated. Thus, an E2PROM memory device cell can be ormed with improved properties which provide high quality programming and erasure control over a relatively large number of programming cycles.
In a preferred embodiment as described above, although two separate implants independent of one another are used, only two masking steps are used as was the case with the Figures 2a-d process. This is because the masking step used to form an active region of a select transistor (such as select transistor 12 in Figure 1) is used to define the first window during formation of the first implant region as described above with respect to Figure 3a.
Further, although two implant regions are used to define the tunneling gate, a preferred fabrication technique as described above is actually simplified. More particularly, the photoresist mask described above with respect to the "conventional fabrication technique in Figure 2c requires a relatively accurately placed window having very accurate dimensions. On the contrary, in accordance with the present invention, the photoresist mask used to define the window 50 can be formed with dimensions having a great deal of tolerance. The actual tolerance associated with these dimensions is limited only by the
length of the variable field oxide layer on either side of the tunnel area 52.
Because the photoresist layer used to establish a mask for forming the implant region of the tunneling gate need not be accurately aligned with the field oxide layer, a relatively large window can be used to improve etching control during formation of the tunnel area. For example, the relatively wide window 50 facilitates wetting of the oxide layer previously protected by the silicon nitride layer 38 without concern that over-etching will remove the oxide from areas over the substrate adjacent the tunnel area.
Accordingly, the precision previously required for fabricating a conventional E2PROM memory cell is not required in accordance with a preferred fabrication technique of the present invention. However, a resulting memory cell designed in accordance with the present invention has improved tunneling characteristics which could not previously be realized. These characteristics included improved programming and erasing operations, and extended life of the memory cell.
Using fabrication techniques as described above, a semiconductor memory device cell designed in accordance with the invention is formed which is similar to that described above with respect to Figure 1. However, there are two key differences. First, the tunnel window is easily defined by wet etching an oxide of a few hundred A thickness instead of an uncontrollable wet etch or a substrate damaging plasma etch of a thicker, decoupling oxide. A tunneling oxide grown therefore has a well defined size and less leakage and hence provides a longer life for the memory
cell. Second, the tunneling gate 4 is no longer formed with a single n- material, but rather is formed with two different doses of the same or different implant materials as described above with respect to Figure 3d. A tunneling gate formed with first and second implant regions provides improved operating characteristics and extends the life of the memory device cell.
It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced therein.
Claims
1. Method for fabricating a cell for use in a semiconductor memory device comprising the steps of: forming a first oxide layer of varying thickness on a semiconductor substrate, said oxide layer having a first portion formed of a first thickness and a second portion formed of a second thickness greater than said first thickness; defining a first implant region of said substrate beneath said first portion of said oxide layer, said step of defining further including depositing a nitride layer in a tunnel area of said first portion, coating a photoresist material as a mask on said nitride layer, and etching said nitride layer to define edges of said nitride layer; implanting a first dose of a conductive material within said first implant region; removing said photoresist mask; growing a second oxide layer on said first oxide layer with said nitride layer in place over said tunnel area of said first oxide layer; defining a second implant region of said substrate beneath said tunnel area of said first oxide layer, said step of defining a second implant region further including steps of removing said nitride layer, and coating a second photoresist mask on said second oxide layer; implanting a second dose of a conductive material within said second implant region; removing said first layer of oxide from said tunnel area and removing said second photoresist mask; growing a tunnel window oxide layer on said substrate; and depositing at least a first polysilicon layer over said tunnel window oxide layer to form a conductive region of said semiconductor memory cell.
2. Method according to claim 1, wherein different materials are used for said first and second implants.
3. Method according to claim 2, wherein arsenic is used for said first implant and phosphorous is used for said second implant.
4. Method according to claim 1, wherein an amount of said first dose is different from an amount of said second dose, said first dose being higher than said second dose.
5. Method according to claim 1, wherein said step of removing said nitride layer further includes the step of: chemically etching said nitride layer with hot phosphoric acid.
6. Method according to claim 1, wherein said step of removing said first layer of oxide from said tunnel area further includes the step of: chemically etching said first and second oxide layers until the substrate is exposed within said tunnel area.
7. Method according to claim 1, wherein said step of growing said tunnel window oxide layer is performed until said tunnel window oxide layer is approximately 100 Angstroms thick.
8. Method according to claim 7, wherein an oxide layer adjacent said tunnel window oxide layer is approximately 3000 Angstroms thick.
9. Method according to claim 1, wherein said first and second implant regions overlap to form a tunneling gate of the memory cell.
10. A semiconductor memory cell formed by a method comprising the steps of: forming a first oxide layer on a semiconductor substrate; defining a first implant region of a tunneling gate in said substrate beneath said first oxide layer; implanting a first dose of a conductive material within said first implant region; defining a second implant region of said tunneling gate adjacent said first implant region in said substrate beneath a tunnel area of said first oxide layer; implanting a second dose of a conductive material within said second implant region; removing said first layer of oxide from said tunnel area; and growing a tunnel window oxide layer on said substrate.
11. Semiconductor memory cell according to claim 10, wherein said cell is an E2PR0M cell having a floating gate and a tunneling gate.
12. A semiconductor memory cell for use in an E2PR0M comprising: a substrate; a floating gate for storing a charge; a coupling gate and a tunneling gate for charging and discharging said floating gate, said tunneling gate being formed within said substrate and including a conductive first implant region and a second conductive implant region, said first implant region having characteristics different from said second implant region.
13. Semiconductor memory cell according to claim
12, wherein said first implant region is formed with a first implant material and said second implant region is formed with a second implant material.
14. Semiconductor memory cell according to claim
13, wherein said first implant material is arsenic and said second implant material is phosphorous.
15. Semiconductor memory cell according to claim 12, wherein said first implant region is formed with a first dose of conductive material and said second implant region is formed with a second dose of conductive material.
16. Method for fabricating a cell for use in a semiconductor memory device comprising the steps of: forming a first oxide layer on a semiconductor substrate; defining a first implant region of a tunneling gate in said substrate beneath said first oxide layer; implanting a first dose of a conductive material within said first implant region; defining a second implant region of said tunneling gate adjacent said first implant region in said substrate beneath a tunnel area of said first oxide layer; implanting a second dose of a conductive material within said second implant region; removing said first layer of oxide from said tunnel area; and growing a tunnel window oxide layer on said substrate.
17. Method according to claim 16, wherein said first implant material is arsenic and said second implant material is phosphorous.
18. Method according to claim 16, wherein said step of defining a first implant region is also used to define an active region of peripheral transistors on the substrate.
19. Method according to claim 16, wherein said step of defining a first implant region further includes a step of: depositing a silicon nitride layer in said tunnel area of said first oxide layer, said second implant region corresponding to an area of said substrate beneath said silicon nitride layer.
20. Method according to claim 19, wherein edges of said silicon nitride layer define an interface between said first implant region and said second implant region in said substrate.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5505520A JPH06510637A (en) | 1991-09-12 | 1992-09-11 | EEPROM cell with improved tunnel characteristics |
KR1019940700801A KR940702645A (en) | 1991-09-12 | 1992-09-11 | EEPROM CELL WITH IMPROVED TUNNELING PROPERTIES With Improved Tunneling Properties |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US758,554 | 1991-09-12 | ||
US07/758,554 US5198381A (en) | 1991-09-12 | 1991-09-12 | Method of making an E2 PROM cell with improved tunneling properties having two implant stages |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1993005536A1 true WO1993005536A1 (en) | 1993-03-18 |
Family
ID=25052154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1992/007728 WO1993005536A1 (en) | 1991-09-12 | 1992-09-11 | Eeprom cell with improved tunneling properties |
Country Status (4)
Country | Link |
---|---|
US (2) | US5198381A (en) |
JP (1) | JPH06510637A (en) |
KR (1) | KR940702645A (en) |
WO (1) | WO1993005536A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0730239A2 (en) * | 1995-02-28 | 1996-09-04 | International Business Machines Corporation | Method and apparatus for telephone modification of documents |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1252214B (en) * | 1991-12-13 | 1995-06-05 | Sgs Thomson Microelectronics | PROCEDURE FOR THE DEFINITION OF PORTIONS OF THIN OXIDE PARTICULARLY FOR MEMORY CELLS ONLY READING PROGRAMMABLE AND ELECTRICALLY ERASABLE. |
JPH08130258A (en) * | 1994-10-31 | 1996-05-21 | Sony Corp | Semiconductor nonvolatile memory element |
US5719427A (en) * | 1997-01-14 | 1998-02-17 | Pericom Semiconductor Corp. | Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures |
US6232633B1 (en) | 1998-06-08 | 2001-05-15 | International Business Machines Corporation | NVRAM cell using sharp tip for tunnel erase |
US6754485B1 (en) * | 1998-12-23 | 2004-06-22 | American Calcar Inc. | Technique for effectively providing maintenance and information to vehicles |
US6369422B1 (en) | 2001-05-01 | 2002-04-09 | Atmel Corporation | Eeprom cell with asymmetric thin window |
US8314024B2 (en) * | 2008-12-19 | 2012-11-20 | Unity Semiconductor Corporation | Device fabrication |
JP2010283110A (en) * | 2009-06-04 | 2010-12-16 | Rohm Co Ltd | Semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2085226A (en) * | 1980-10-14 | 1982-04-21 | Intel Corp | Floating gate eprom cells |
EP0060408A1 (en) * | 1981-02-27 | 1982-09-22 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read only memory |
US4780424A (en) * | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
DE4105636A1 (en) * | 1990-02-22 | 1991-08-29 | Mitsubishi Electric Corp | ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREFOR |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4519849A (en) * | 1980-10-14 | 1985-05-28 | Intel Corporation | Method of making EPROM cell with reduced programming voltage |
DE3318213A1 (en) * | 1983-05-19 | 1984-11-22 | Deutsche Itt Industries Gmbh, 7800 Freiburg | METHOD FOR PRODUCING AN INTEGRATED INSULATION LAYER FIELD EFFECT TRANSISTOR WITH CONTACTS FOR THE GATE ELECTRODE SELF-ALIGNED |
EP0164605B1 (en) * | 1984-05-17 | 1990-02-28 | Kabushiki Kaisha Toshiba | Method of manufacturing nonvolatile semiconductor eeprom device |
US4851361A (en) * | 1988-02-04 | 1989-07-25 | Atmel Corporation | Fabrication process for EEPROMS with high voltage transistors |
US5100819A (en) * | 1988-07-15 | 1992-03-31 | Texas Instruments Incorporated | Method of making electrically programmable and erasable memory cells with field plate conductor defined drain regions |
-
1991
- 1991-09-12 US US07/758,554 patent/US5198381A/en not_active Expired - Fee Related
-
1992
- 1992-09-11 WO PCT/US1992/007728 patent/WO1993005536A1/en active Application Filing
- 1992-09-11 JP JP5505520A patent/JPH06510637A/en active Pending
- 1992-09-11 KR KR1019940700801A patent/KR940702645A/en not_active Application Discontinuation
-
1994
- 1994-04-01 US US08/221,463 patent/US5371393A/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2085226A (en) * | 1980-10-14 | 1982-04-21 | Intel Corp | Floating gate eprom cells |
EP0060408A1 (en) * | 1981-02-27 | 1982-09-22 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read only memory |
US4780424A (en) * | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
DE4105636A1 (en) * | 1990-02-22 | 1991-08-29 | Mitsubishi Electric Corp | ELECTRICALLY PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREFOR |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0730239A2 (en) * | 1995-02-28 | 1996-09-04 | International Business Machines Corporation | Method and apparatus for telephone modification of documents |
EP0730239A3 (en) * | 1995-02-28 | 2000-08-16 | International Business Machines Corporation | Method and apparatus for telephone modification of documents |
Also Published As
Publication number | Publication date |
---|---|
KR940702645A (en) | 1994-08-20 |
US5371393A (en) | 1994-12-06 |
US5198381A (en) | 1993-03-30 |
JPH06510637A (en) | 1994-11-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100192551B1 (en) | Semiconductor memory device and fabrication method of the same | |
US5471422A (en) | EEPROM cell with isolation transistor and methods for making and operating the same | |
US7202125B2 (en) | Low-voltage, multiple thin-gate oxide and low-resistance gate electrode | |
KR100274491B1 (en) | Spacer Flash Cell Process | |
US5640031A (en) | Spacer flash cell process | |
US6760258B2 (en) | Means to erase a low voltage programmable and erasable flash EEPROM | |
US5789297A (en) | Method of making EEPROM cell device with polyspacer floating gate | |
US6168995B1 (en) | Method of fabricating a split gate memory cell | |
US5422292A (en) | Process for fabricating split gate flash EEPROM memory | |
US5198381A (en) | Method of making an E2 PROM cell with improved tunneling properties having two implant stages | |
KR0165855B1 (en) | Method and apparatus for forming a side wall contact in a nonvolatile electrically alterable memory cell | |
KR100270577B1 (en) | Method of manufacturing a flash memory cell | |
US6916708B2 (en) | Method of forming a floating gate for a stacked gate flash memory device | |
US6242306B1 (en) | Dual bit isolation scheme for flash memory devices having polysilicon floating gates | |
US7186615B2 (en) | Method of forming a floating gate for a split-gate flash memory device | |
US6329254B1 (en) | Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method | |
EP0612108B1 (en) | Double polysilicon EEPROM cell and corresponding manufacturing process | |
US6548855B1 (en) | Non-volatile memory dielectric as charge pump dielectric | |
WO1994022171A1 (en) | Single polysilicon layer e2prom cell | |
US20030100157A1 (en) | Flash memory with protruded floating gate | |
KR890003830B1 (en) | Poly silicon eeprom cell of making method | |
KR19980022101A (en) | Ipyrom Cell Device with Police Phase Floating Gate | |
KR20060000790A (en) | Method of manufacturing flash memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL SE |
|
122 | Ep: pct application non-entry in european phase |